1 2015-07-03 Alan Modra <amodra@gmail.com>
3 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
4 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
5 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
7 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
8 Cesar Philippidis <cesar@codesourcery.com>
10 * nios2-dis.c (nios2_extract_opcode): New.
11 (nios2_disassembler_state): New.
12 (nios2_find_opcode_hash): Use mach parameter to select correct
14 (nios2_print_insn_arg): Extend to support new R2 argument letters
16 (print_insn_nios2): Check for 16-bit instruction at end of memory.
17 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
18 (NIOS2_NUM_OPCODES): Rename to...
19 (NIOS2_NUM_R1_OPCODES): This.
20 (nios2_r2_opcodes): New.
21 (NIOS2_NUM_R2_OPCODES): New.
22 (nios2_num_r2_opcodes): New.
23 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
24 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
25 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
26 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
27 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
29 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
31 * i386-dis.c (OP_Mwaitx): New.
32 (rm_table): Add monitorx/mwaitx.
33 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
34 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
35 (operand_type_init): Add CpuMWAITX.
36 * i386-opc.h (CpuMWAITX): New.
37 (i386_cpu_flags): Add cpumwaitx.
38 * i386-opc.tbl: Add monitorx and mwaitx.
39 * i386-init.h: Regenerated.
40 * i386-tbl.h: Likewise.
42 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
44 * ppc-opc.c (insert_ls): Test for invalid LS operands.
45 (insert_esync): New function.
46 (LS, WC): Use insert_ls.
47 (ESYNC): Use insert_esync.
49 2015-06-22 Nick Clifton <nickc@redhat.com>
51 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
52 requested region lies beyond it.
53 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
54 looking for 32-bit insns.
55 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
57 * sh-dis.c (print_insn_sh): Likewise.
58 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
59 blocks of instructions.
60 * vax-dis.c (print_insn_vax): Check that the requested address
61 does not clash with the stop_vma.
63 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
65 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
66 * ppc-opc.c (FXM4): Add non-zero optional value.
69 (insert_fxm): Handle new default operand value.
70 (extract_fxm): Likewise.
71 (insert_tbr): Likewise.
72 (extract_tbr): Likewise.
74 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
76 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
78 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
80 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
82 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
84 * ppc-opc.c: Add comment accidentally removed by old commit.
87 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
89 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
91 2015-06-04 Nick Clifton <nickc@redhat.com>
94 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
96 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
98 * arm-dis.c (arm_opcodes): Add "setpan".
99 (thumb_opcodes): Add "setpan".
101 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
103 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
106 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
108 * aarch64-tbl.h (aarch64_feature_rdma): New.
110 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
111 * aarch64-asm-2.c: Regenerate.
112 * aarch64-dis-2.c: Regenerate.
113 * aarch64-opc-2.c: Regenerate.
115 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
117 * aarch64-tbl.h (aarch64_feature_lor): New.
119 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
121 * aarch64-asm-2.c: Regenerate.
122 * aarch64-dis-2.c: Regenerate.
123 * aarch64-opc-2.c: Regenerate.
125 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
127 * aarch64-opc.c (F_ARCHEXT): New.
128 (aarch64_sys_regs): Add "pan".
129 (aarch64_sys_reg_supported_p): New.
130 (aarch64_pstatefields): Add "pan".
131 (aarch64_pstatefield_supported_p): New.
133 2015-06-01 Jan Beulich <jbeulich@suse.com>
135 * i386-tbl.h: Regenerate.
137 2015-06-01 Jan Beulich <jbeulich@suse.com>
139 * i386-dis.c (print_insn): Swap rounding mode specifier and
140 general purpose register in Intel mode.
142 2015-06-01 Jan Beulich <jbeulich@suse.com>
144 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
145 * i386-tbl.h: Regenerate.
147 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
149 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
150 * i386-init.h: Regenerated.
152 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
155 * i386-dis.c: Add comments for '@'.
156 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
157 (enum x86_64_isa): New.
159 (print_i386_disassembler_options): Add amd64 and intel64.
160 (print_insn): Handle amd64 and intel64.
162 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
163 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
164 * i386-opc.h (AMD64): New.
165 (CpuIntel64): Likewise.
166 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
167 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
168 Mark direct call/jmp without Disp16|Disp32 as Intel64.
169 * i386-init.h: Regenerated.
170 * i386-tbl.h: Likewise.
172 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
174 * ppc-opc.c (IH) New define.
175 (powerpc_opcodes) <wait>: Do not enable for POWER7.
176 <tlbie>: Add RS operand for POWER7.
177 <slbia>: Add IH operand for POWER6.
179 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
181 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
184 * i386-tbl.h: Regenerated.
186 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
188 * configure.ac: Support bfd_iamcu_arch.
189 * disassemble.c (disassembler): Support bfd_iamcu_arch.
190 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
191 CPU_IAMCU_COMPAT_FLAGS.
192 (cpu_flags): Add CpuIAMCU.
193 * i386-opc.h (CpuIAMCU): New.
194 (i386_cpu_flags): Add cpuiamcu.
195 * configure: Regenerated.
196 * i386-init.h: Likewise.
197 * i386-tbl.h: Likewise.
199 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
202 * i386-dis.c (X86_64_E8): New.
203 (X86_64_E9): Likewise.
204 Update comments on 'T', 'U', 'V'. Add comments for '^'.
205 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
206 (x86_64_table): Add X86_64_E8 and X86_64_E9.
207 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
209 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
212 2015-04-30 DJ Delorie <dj@redhat.com>
214 * disassemble.c (disassembler): Choose suitable disassembler based
216 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
217 it to decode mul/div insns.
218 * rl78-decode.c: Regenerate.
219 * rl78-dis.c (print_insn_rl78): Rename to...
220 (print_insn_rl78_common): ...this, take ISA parameter.
221 (print_insn_rl78): New.
222 (print_insn_rl78_g10): New.
223 (print_insn_rl78_g13): New.
224 (print_insn_rl78_g14): New.
225 (rl78_get_disassembler): New.
227 2015-04-29 Nick Clifton <nickc@redhat.com>
229 * po/fr.po: Updated French translation.
231 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
233 * ppc-opc.c (DCBT_EO): New define.
234 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
238 <waitrsv>: Do not enable for POWER7 and later.
239 <waitimpl>: Likewise.
240 <dcbt>: Default to the two operand form of the instruction for all
241 "old" cpus. For "new" cpus, use the operand ordering that matches
242 whether the cpu is server or embedded.
245 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
247 * s390-opc.c: New instruction type VV0UU2.
248 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
251 2015-04-23 Jan Beulich <jbeulich@suse.com>
253 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
254 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
255 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
256 (vfpclasspd, vfpclassps): Add %XZ.
258 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
260 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
261 (PREFIX_UD_REPZ): Likewise.
262 (PREFIX_UD_REPNZ): Likewise.
263 (PREFIX_UD_DATA): Likewise.
264 (PREFIX_UD_ADDR): Likewise.
265 (PREFIX_UD_LOCK): Likewise.
267 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
269 * i386-dis.c (prefix_requirement): Removed.
270 (print_insn): Don't set prefix_requirement. Check
271 dp->prefix_requirement instead of prefix_requirement.
273 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
276 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
277 (PREFIX_MOD_0_0FC7_REG_6): This.
278 (PREFIX_MOD_3_0FC7_REG_6): New.
279 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
280 (prefix_table): Replace PREFIX_0FC7_REG_6 with
281 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
282 PREFIX_MOD_3_0FC7_REG_7.
283 (mod_table): Replace PREFIX_0FC7_REG_6 with
284 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
285 PREFIX_MOD_3_0FC7_REG_7.
287 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
289 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
290 (PREFIX_MANDATORY_REPNZ): Likewise.
291 (PREFIX_MANDATORY_DATA): Likewise.
292 (PREFIX_MANDATORY_ADDR): Likewise.
293 (PREFIX_MANDATORY_LOCK): Likewise.
294 (PREFIX_MANDATORY): Likewise.
295 (PREFIX_UD_SHIFT): Set to 8
296 (PREFIX_UD_REPZ): Updated.
297 (PREFIX_UD_REPNZ): Likewise.
298 (PREFIX_UD_DATA): Likewise.
299 (PREFIX_UD_ADDR): Likewise.
300 (PREFIX_UD_LOCK): Likewise.
301 (PREFIX_IGNORED_SHIFT): New.
302 (PREFIX_IGNORED_REPZ): Likewise.
303 (PREFIX_IGNORED_REPNZ): Likewise.
304 (PREFIX_IGNORED_DATA): Likewise.
305 (PREFIX_IGNORED_ADDR): Likewise.
306 (PREFIX_IGNORED_LOCK): Likewise.
307 (PREFIX_OPCODE): Likewise.
308 (PREFIX_IGNORED): Likewise.
309 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
310 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
311 (three_byte_table): Likewise.
312 (mod_table): Likewise.
313 (mandatory_prefix): Renamed to ...
314 (prefix_requirement): This.
315 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
316 Update PREFIX_90 entry.
317 (get_valid_dis386): Check prefix_requirement to see if a prefix
319 (print_insn): Replace mandatory_prefix with prefix_requirement.
321 2015-04-15 Renlin Li <renlin.li@arm.com>
323 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
324 use it for ssat and ssat16.
325 (print_insn_thumb32): Add handle case for 'D' control code.
327 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
328 H.J. Lu <hongjiu.lu@intel.com>
330 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
331 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
332 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
333 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
334 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
335 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
336 Fill prefix_requirement field.
337 (struct dis386): Add prefix_requirement field.
338 (dis386): Fill prefix_requirement field.
339 (dis386_twobyte): Ditto.
340 (twobyte_has_mandatory_prefix_: Remove.
341 (reg_table): Fill prefix_requirement field.
342 (prefix_table): Ditto.
343 (x86_64_table): Ditto.
344 (three_byte_table): Ditto.
347 (vex_len_table): Ditto.
348 (vex_w_table): Ditto.
351 (print_insn): Use prefix_requirement.
352 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
353 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
356 2015-03-30 Mike Frysinger <vapier@gentoo.org>
358 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
360 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
362 * Makefile.in: Regenerated.
364 2015-03-25 Anton Blanchard <anton@samba.org>
366 * ppc-dis.c (disassemble_init_powerpc): Only initialise
367 powerpc_opcd_indices and vle_opcd_indices once.
369 2015-03-25 Anton Blanchard <anton@samba.org>
371 * ppc-opc.c (powerpc_opcodes): Add slbfee.
373 2015-03-24 Terry Guo <terry.guo@arm.com>
375 * arm-dis.c (opcode32): Updated to use new arm feature struct.
376 (opcode16): Likewise.
377 (coprocessor_opcodes): Replace bit with feature struct.
378 (neon_opcodes): Likewise.
379 (arm_opcodes): Likewise.
380 (thumb_opcodes): Likewise.
381 (thumb32_opcodes): Likewise.
382 (print_insn_coprocessor): Likewise.
383 (print_insn_arm): Likewise.
384 (select_arm_features): Follow new feature struct.
386 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
388 * i386-dis.c (rm_table): Add clzero.
389 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
390 Add CPU_CLZERO_FLAGS.
391 (cpu_flags): Add CpuCLZERO.
392 * i386-opc.h: Add CpuCLZERO.
393 * i386-opc.tbl: Add clzero.
394 * i386-init.h: Re-generated.
395 * i386-tbl.h: Re-generated.
397 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
399 * mips-opc.c (decode_mips_operand): Fix constraint issues
400 with u and y operands.
402 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
404 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
406 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
408 * s390-opc.c: Add new IBM z13 instructions.
409 * s390-opc.txt: Likewise.
411 2015-03-10 Renlin Li <renlin.li@arm.com>
413 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
414 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
416 * aarch64-asm-2.c: Regenerate.
417 * aarch64-dis-2.c: Likewise.
418 * aarch64-opc-2.c: Likewise.
420 2015-03-03 Jiong Wang <jiong.wang@arm.com>
422 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
424 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
426 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
428 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
429 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
431 2015-02-23 Vinay <Vinay.G@kpit.com>
433 * rl78-decode.opc (MOV): Added space between two operands for
434 'mov' instruction in index addressing mode.
435 * rl78-decode.c: Regenerate.
437 2015-02-19 Pedro Alves <palves@redhat.com>
439 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
441 2015-02-10 Pedro Alves <palves@redhat.com>
442 Tom Tromey <tromey@redhat.com>
444 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
445 microblaze_and, microblaze_xor.
446 * microblaze-opc.h (opcodes): Adjust.
448 2015-01-28 James Bowman <james.bowman@ftdichip.com>
450 * Makefile.am: Add FT32 files.
451 * configure.ac: Handle FT32.
452 * disassemble.c (disassembler): Call print_insn_ft32.
453 * ft32-dis.c: New file.
454 * ft32-opc.c: New file.
455 * Makefile.in: Regenerate.
456 * configure: Regenerate.
457 * po/POTFILES.in: Regenerate.
459 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
461 * nds32-asm.c (keyword_sr): Add new system registers.
463 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
465 * s390-dis.c (s390_extract_operand): Support vector register
467 (s390_print_insn_with_opcode): Support new operands types and add
468 new handling of optional operands.
469 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
470 and include opcode/s390.h instead.
471 (struct op_struct): New field `flags'.
472 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
473 (dumpTable): Dump flags.
474 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
476 * s390-opc.c: Add new operands types, instruction formats, and
478 (s390_opformats): Add new formats for .insn.
479 * s390-opc.txt: Add new instructions.
481 2015-01-01 Alan Modra <amodra@gmail.com>
483 Update year range in copyright notice of all files.
485 For older changes see ChangeLog-2014
487 Copyright (C) 2015 Free Software Foundation, Inc.
489 Copying and distribution of this file, with or without modification,
490 are permitted in any medium without royalty provided the copyright
491 notice and this notice are preserved.
497 version-control: never