opcodes/ChangeLog

   1 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
   4         with an esize parameter.
   5         (operand_general_constraint_met_p): Update accordingly.
   6         Fix misindented code.
   7         * aarch64-asm.c (aarch64_ins_limm): Update call to
   8         aarch64_logical_immediate_p.
   9
  10 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  11
  12         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
  13
  14 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  15
  16         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
  17
  18 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
  19
  20         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
  21
  22 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
  23
  24         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
  25         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
  26         xor3>: Delete mnemonics.
  27         <cp_abort>: Rename mnemonic from ...
  28         <cpabort>: ...to this.
  29         <setb>: Change to a X form instruction.
  30         <sync>: Change to 1 operand form.
  31         <copy>: Delete mnemonic.
  32         <copy_first>: Rename mnemonic from ...
  33         <copy>: ...to this.
  34         <paste, paste.>: Delete mnemonics.
  35         <paste_last>: Rename mnemonic from ...
  36         <paste.>: ...to this.
  37
  38 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  39
  40         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
  41
  42 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  43
  44         * s390-mkopc.c (main): Support alternate arch strings.
  45
  46 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
  47
  48         * s390-opc.txt: Fix kmctr instruction type.
  49
  50 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
  51
  52         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
  53         * i386-init.h: Regenerated.
  54
  55 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
  56
  57         * opcodes/arc-dis.c (print_insn_arc): Changed.
  58
  59 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
  60
  61         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
  62         camellia_fl.
  63
  64 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  65
  66         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
  67         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
  68         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
  69
  70 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
  71
  72         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
  73         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
  74         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
  75         PREFIX_MOD_3_0FAE_REG_4.
  76         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
  77         PREFIX_MOD_3_0FAE_REG_4.
  78         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
  79         (cpu_flags): Add CpuPTWRITE.
  80         * i386-opc.h (CpuPTWRITE): New.
  81         (i386_cpu_flags): Add cpuptwrite.
  82         * i386-opc.tbl: Add ptwrite instruction.
  83         * i386-init.h: Regenerated.
  84         * i386-tbl.h: Likewise.
  85
  86 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  87
  88         * arc-dis.h: Wrap around in extern "C".
  89
  90 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  91
  92         * aarch64-tbl.h (V8_2_INSN): New macro.
  93         (aarch64_opcode_table): Use it.
  94
  95 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  96
  97         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
  98         CORE_INSN, __FP_INSN and SIMD_INSN.
  99
 100 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 101
 102         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 103         (aarch64_opcode_table): Update uses accordingly.
 104
 105 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 106         Kwok Cheung Yeung  <kcy@codesourcery.com>
 107
 108         opcodes/
 109         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 110         'e_cmplwi' to 'e_cmpli' instead.
 111         (OPVUPRT, OPVUPRT_MASK): Define.
 112         (powerpc_opcodes): Add E200Z4 insns.
 113         (vle_opcodes): Add context save/restore insns.
 114
 115 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 116
 117         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 118         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 119         "j".
 120
 121 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 122
 123         * arc-nps400-tbl.h: Change block comments to GNU format.
 124         * arc-dis.c: Add new globals addrtypenames,
 125         addrtypenames_max, and addtypeunknown.
 126         (get_addrtype): New function.
 127         (print_insn_arc): Print colons and address types when
 128         required.
 129         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 130         define insert and extract functions for all address types.
 131         (arc_operands): Add operands for colon and all address
 132         types.
 133         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 134         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 135         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 136         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 137         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 138         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 139
 140 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 141
 142         * configure: Regenerated.
 143
 144 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 145
 146         * arc-dis.c (skipclass): New structure.
 147         (decodelist): New variable.
 148         (is_compatible_p): New function.
 149         (new_element): Likewise.
 150         (skip_class_p): Likewise.
 151         (find_format_from_table): Use skip_class_p function.
 152         (find_format): Decode first the extension instructions.
 153         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 154         e_flags.
 155         (parse_option): New function.
 156         (parse_disassembler_options): Likewise.
 157         (print_arc_disassembler_options): Likewise.
 158         (print_insn_arc): Use parse_disassembler_options function.  Proper
 159         select ARCv2 cpu variant.
 160         * disassemble.c (disassembler_usage): Add ARC disassembler
 161         options.
 162
 163 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 164
 165         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 166         annotation from the "nal" entry and reorder it beyond "bltzal".
 167
 168 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 169
 170         * sparc-opc.c (ldtxa): New macro.
 171         (sparc_opcodes): Use the macro defined above to add entries for
 172         the LDTXA instructions.
 173         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 174         instruction.
 175
 176 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 177
 178         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 179         and "jmpc".
 180
 181 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 184         (movzb): Adjust to cover all permitted suffixes.
 185         (movzw): New.
 186         * i386-tbl.h: Re-generate.
 187
 188 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 189
 190         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 191         (lgdt): Remove Tbyte from non-64-bit variant.
 192         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 193         xsaves64, xsavec64): Remove Disp16.
 194         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 195         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 196         64-bit variants.
 197         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 198         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 199         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 200         64-bit variants.
 201         * i386-tbl.h: Re-generate.
 202
 203 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 204
 205         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 206         * i386-tbl.h: Re-generate.
 207
 208 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 209
 210         * arm-dis.c (print_insn): Fix typo in comment.
 211
 212 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 213
 214         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 215         range of ldst_elemlist operands.
 216         (print_register_list): Use PRIi64 to print the index.
 217         (aarch64_print_operand): Likewise.
 218
 219 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 220
 221         * mcore-opc.h: Remove sentinal.
 222         * mcore-dis.c (print_insn_mcore): Adjust.
 223
 224 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 225
 226         * arc-opc.c: Correct description of availability of NPS400
 227         features.
 228
 229 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 230
 231         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 232         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 233         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 234         xor3>: New mnemonics.
 235         <setb>: Change to a VX form instruction.
 236         (insert_sh6): Add support for rldixor.
 237         (extract_sh6): Likewise.
 238
 239 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 240
 241         * arc-ext.h: Wrap in extern C.
 242
 243 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 244
 245         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 246         Use same method for determining instruction length on ARC700 and
 247         NPS-400.
 248         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 249         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 250         with the NPS400 subclass.
 251         * arc-opc.c: Likewise.
 252
 253 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 254
 255         * sparc-opc.c (rdasr): New macro.
 256         (wrasr): Likewise.
 257         (rdpr): Likewise.
 258         (wrpr): Likewise.
 259         (rdhpr): Likewise.
 260         (wrhpr): Likewise.
 261         (sparc_opcodes): Use the macros above to fix and expand the
 262         definition of read/write instructions from/to
 263         asr/privileged/hyperprivileged instructions.
 264         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 265         %hva_mask_nz.  Prefer softint_set and softint_clear over
 266         set_softint and clear_softint.
 267         (print_insn_sparc): Support %ver in Rd.
 268
 269 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 270
 271         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 272         architecture according to the hardware capabilities they require.
 273
 274 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 275
 276         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 277         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 278         bfd_mach_sparc_v9{c,d,e,v,m}.
 279         * sparc-opc.c (MASK_V9C): Define.
 280         (MASK_V9D): Likewise.
 281         (MASK_V9E): Likewise.
 282         (MASK_V9V): Likewise.
 283         (MASK_V9M): Likewise.
 284         (v6): Add MASK_V9{C,D,E,V,M}.
 285         (v6notlet): Likewise.
 286         (v7): Likewise.
 287         (v8): Likewise.
 288         (v9): Likewise.
 289         (v9andleon): Likewise.
 290         (v9a): Likewise.
 291         (v9b): Likewise.
 292         (v9c): Define.
 293         (v9d): Likewise.
 294         (v9e): Likewise.
 295         (v9v): Likewise.
 296         (v9m): Likewise.
 297         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 298
 299 2016-06-15  Nick Clifton  <nickc@redhat.com>
 300
 301         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 302         constants to match expected behaviour.
 303         (nds32_parse_opcode): Likewise.  Also for whitespace.
 304
 305 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 306
 307         * arc-opc.c (extract_rhv1): Extract value from insn.
 308
 309 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 310
 311         * arc-nps400-tbl.h: Add ldbit instruction.
 312         * arc-opc.c: Add flag classes required for ldbit.
 313
 314 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 315
 316         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 317         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 318         support the above instructions.
 319
 320 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 321
 322         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 323         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 324         csma, cbba, zncv, and hofs.
 325         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 326         support the above instructions.
 327
 328 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 329
 330         * arc-nps400-tbl.h: Add andab and orab instructions.
 331
 332 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 333
 334         * arc-nps400-tbl.h: Add addl-like instructions.
 335
 336 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 337
 338         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 339
 340 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 341
 342         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 343         instructions.
 344
 345 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 346
 347         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 348         variable.
 349         (init_disasm): Handle new command line option "insnlength".
 350         (print_s390_disassembler_options): Mention new option in help
 351         output.
 352         (print_insn_s390): Use the encoded insn length when dumping
 353         unknown instructions.
 354
 355 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 356
 357         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 358          to the address and set as symbol address for LDS/ STS immediate operands.
 359
 360 2016-06-07  Alan Modra  <amodra@gmail.com>
 361
 362         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 363         cpu for "vle" to e500.
 364         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 365         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 366         (PPCNONE): Delete, substitute throughout.
 367         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 368         except for major opcode 4 and 31.
 369         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 370
 371 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 372
 373         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 374         ARM_EXT_RAS in relevant entries.
 375
 376 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 377
 378         PR binutils/20196
 379         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 380         opcodes for E6500.
 381
 382 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         PR binutis/18386
 385         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 386         (indir_v_mode): New.
 387         Add comments for '&'.
 388         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 389         (putop): Handle '&'.
 390         (intel_operand_size): Handle indir_v_mode.
 391         (OP_E_register): Likewise.
 392         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 393         64-bit indirect call/jmp for AMD64.
 394         * i386-tbl.h: Regenerated
 395
 396 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 397
 398         * arc-dis.c (struct arc_operand_iterator): New structure.
 399         (find_format_from_table): All the old content from find_format,
 400         with some minor adjustments, and parameter renaming.
 401         (find_format_long_instructions): New function.
 402         (find_format): Rewritten.
 403         (arc_insn_length): Add LSB parameter.
 404         (extract_operand_value): New function.
 405         (operand_iterator_next): New function.
 406         (print_insn_arc): Use new functions to find opcode, and iterator
 407         over operands.
 408         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 409         (extract_nps_3bit_dst_short): New function.
 410         (insert_nps_3bit_src2_short): New function.
 411         (extract_nps_3bit_src2_short): New function.
 412         (insert_nps_bitop1_size): New function.
 413         (extract_nps_bitop1_size): New function.
 414         (insert_nps_bitop2_size): New function.
 415         (extract_nps_bitop2_size): New function.
 416         (insert_nps_bitop_mod4_msb): New function.
 417         (extract_nps_bitop_mod4_msb): New function.
 418         (insert_nps_bitop_mod4_lsb): New function.
 419         (extract_nps_bitop_mod4_lsb): New function.
 420         (insert_nps_bitop_dst_pos3_pos4): New function.
 421         (extract_nps_bitop_dst_pos3_pos4): New function.
 422         (insert_nps_bitop_ins_ext): New function.
 423         (extract_nps_bitop_ins_ext): New function.
 424         (arc_operands): Add new operands.
 425         (arc_long_opcodes): New global array.
 426         (arc_num_long_opcodes): New global.
 427         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 428
 429 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 430
 431         * nds32-asm.h: Add extern "C".
 432         * sh-opc.h: Likewise.
 433
 434 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 435
 436         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 437         0,b,limm to the rflt instruction.
 438
 439 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 440
 441         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 442         constant.
 443
 444 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 445
 446         PR gas/20145
 447         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 448         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 449         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 450         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 451         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 452         * i386-init.h: Regenerated.
 453
 454 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 455
 456         PR gas/20145
 457         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 458         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 459         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 460         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 461         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 462         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 463         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 464         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 465         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 466         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 467         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 468         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 469         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 470         CpuRegMask for AVX512.
 471         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 472         and CpuRegMask.
 473         (set_bitfield_from_cpu_flag_init): New function.
 474         (set_bitfield): Remove const on f.  Call
 475         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 476         * i386-opc.h (CpuRegMMX): New.
 477         (CpuRegXMM): Likewise.
 478         (CpuRegYMM): Likewise.
 479         (CpuRegZMM): Likewise.
 480         (CpuRegMask): Likewise.
 481         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 482         and cpuregmask.
 483         * i386-init.h: Regenerated.
 484         * i386-tbl.h: Likewise.
 485
 486 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 487
 488         PR gas/20154
 489         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 490         (opcode_modifiers): Add AMD64 and Intel64.
 491         (main): Properly verify CpuMax.
 492         * i386-opc.h (CpuAMD64): Removed.
 493         (CpuIntel64): Likewise.
 494         (CpuMax): Set to CpuNo64.
 495         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 496         (AMD64): New.
 497         (Intel64): Likewise.
 498         (i386_opcode_modifier): Add amd64 and intel64.
 499         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 500         on call and jmp.
 501         * i386-init.h: Regenerated.
 502         * i386-tbl.h: Likewise.
 503
 504 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 505
 506         PR gas/20154
 507         * i386-gen.c (main): Fail if CpuMax is incorrect.
 508         * i386-opc.h (CpuMax): Set to CpuIntel64.
 509         * i386-tbl.h: Regenerated.
 510
 511 2016-05-27  Nick Clifton  <nickc@redhat.com>
 512
 513         PR target/20150
 514         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 515         (msp430dis_opcode_unsigned): New function.
 516         (msp430dis_opcode_signed): New function.
 517         (msp430_singleoperand): Use the new opcode reading functions.
 518         Only disassenmble bytes if they were successfully read.
 519         (msp430_doubleoperand): Likewise.
 520         (msp430_branchinstr): Likewise.
 521         (msp430x_callx_instr): Likewise.
 522         (print_insn_msp430): Check that it is safe to read bytes before
 523         attempting disassembly.  Use the new opcode reading functions.
 524
 525 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 526
 527         * ppc-opc.c (CY): New define.  Document it.
 528         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 529
 530 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 531
 532         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 533         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 534         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 535         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 536         CPU_ANY_AVX_FLAGS.
 537         * i386-init.h: Regenerated.
 538
 539 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 540
 541         PR gas/20141
 542         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 543         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 544         * i386-init.h: Regenerated.
 545
 546 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 547
 548         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 549         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 550         * i386-init.h: Regenerated.
 551
 552 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 553
 554         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 555         information.
 556         (print_insn_arc): Set insn_type information.
 557         * arc-opc.c (C_CC): Add F_CLASS_COND.
 558         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 559         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 560         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 561         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 562         (brne, brne_s, jeq_s, jne_s): Likewise.
 563
 564 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 565
 566         * arc-tbl.h (neg): New instruction variant.
 567
 568 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 569
 570         * arc-dis.c (find_format, find_format, get_auxreg)
 571         (print_insn_arc): Changed.
 572         * arc-ext.h (INSERT_XOP): Likewise.
 573
 574 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 575
 576         * tic54x-dis.c (sprint_mmr): Adjust.
 577         * tic54x-opc.c: Likewise.
 578
 579 2016-05-19  Alan Modra  <amodra@gmail.com>
 580
 581         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 582
 583 2016-05-19  Alan Modra  <amodra@gmail.com>
 584
 585         * ppc-opc.c: Formatting.
 586         (NSISIGNOPT): Define.
 587         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 588
 589 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 590
 591         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 592         replacing references to `micromips_ase' throughout.
 593         (_print_insn_mips): Don't use file-level microMIPS annotation to
 594         determine the disassembly mode with the symbol table.
 595
 596 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 597
 598         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 599
 600 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 601
 602         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 603         mips64r6.
 604         * mips-opc.c (D34): New macro.
 605         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 606
 607 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 608
 609         * i386-dis.c (prefix_table): Add RDPID instruction.
 610         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 611         (cpu_flags): Add RDPID bitfield.
 612         * i386-opc.h (enum): Add RDPID element.
 613         (i386_cpu_flags): Add RDPID field.
 614         * i386-opc.tbl: Add RDPID instruction.
 615         * i386-init.h: Regenerate.
 616         * i386-tbl.h: Regenerate.
 617
 618 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 619
 620         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 621         branch type of a symbol.
 622         (print_insn): Likewise.
 623
 624 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 625
 626         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 627         Mainline Security Extensions instructions.
 628         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 629         Extensions instructions.
 630         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 631         instructions.
 632         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 633         special registers.
 634
 635 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 636
 637         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 638
 639 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 640
 641         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 642         (arcExtMap_genOpcode): Likewise.
 643         * arc-opc.c (arg_32bit_rc): Define new variable.
 644         (arg_32bit_u6): Likewise.
 645         (arg_32bit_limm): Likewise.
 646
 647 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 648
 649         * aarch64-gen.c (VERIFIER): Define.
 650         * aarch64-opc.c (VERIFIER): Define.
 651         (verify_ldpsw): Use static linkage.
 652         * aarch64-opc.h (verify_ldpsw): Remove.
 653         * aarch64-tbl.h: Use VERIFIER for verifiers.
 654
 655 2016-04-28  Nick Clifton  <nickc@redhat.com>
 656
 657         PR target/19722
 658         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 659         * aarch64-opc.c (verify_ldpsw): New function.
 660         * aarch64-opc.h (verify_ldpsw): New prototype.
 661         * aarch64-tbl.h: Add initialiser for verifier field.
 662         (LDPSW): Set verifier to verify_ldpsw.
 663
 664 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 665
 666         PR binutils/19983
 667         PR binutils/19984
 668         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 669         smaller than address size.
 670
 671 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 672
 673         * alpha-dis.c: Regenerate.
 674         * crx-dis.c: Likewise.
 675         * disassemble.c: Likewise.
 676         * epiphany-opc.c: Likewise.
 677         * fr30-opc.c: Likewise.
 678         * frv-opc.c: Likewise.
 679         * ip2k-opc.c: Likewise.
 680         * iq2000-opc.c: Likewise.
 681         * lm32-opc.c: Likewise.
 682         * lm32-opinst.c: Likewise.
 683         * m32c-opc.c: Likewise.
 684         * m32r-opc.c: Likewise.
 685         * m32r-opinst.c: Likewise.
 686         * mep-opc.c: Likewise.
 687         * mt-opc.c: Likewise.
 688         * or1k-opc.c: Likewise.
 689         * or1k-opinst.c: Likewise.
 690         * tic80-opc.c: Likewise.
 691         * xc16x-opc.c: Likewise.
 692         * xstormy16-opc.c: Likewise.
 693
 694 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 695
 696         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 697         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 698         calcsd, and calcxd instructions.
 699         * arc-opc.c (insert_nps_bitop_size): Delete.
 700         (extract_nps_bitop_size): Delete.
 701         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 702         (extract_nps_qcmp_m3): Define.
 703         (extract_nps_qcmp_m2): Define.
 704         (extract_nps_qcmp_m1): Define.
 705         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 706         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 707         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 708         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 709         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 710         NPS_QCMP_M3.
 711
 712 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 713
 714         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 715
 716 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 717
 718         * Makefile.in: Regenerated with automake 1.11.6.
 719         * aclocal.m4: Likewise.
 720
 721 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 722
 723         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 724         instructions.
 725         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 726         (extract_nps_cmem_uimm16): New function.
 727         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 728
 729 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 730
 731         * arc-dis.c (arc_insn_length): New function.
 732         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 733         (find_format): Change insnLen parameter to unsigned.
 734
 735 2016-04-13  Nick Clifton  <nickc@redhat.com>
 736
 737         PR target/19937
 738         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 739         the LD.B and LD.BU instructions.
 740
 741 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 742
 743         * arc-dis.c (find_format): Check for extension flags.
 744         (print_flags): New function.
 745         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 746         .extAuxRegister.
 747         * arc-ext.c (arcExtMap_coreRegName): Use
 748         LAST_EXTENSION_CORE_REGISTER.
 749         (arcExtMap_coreReadWrite): Likewise.
 750         (dump_ARC_extmap): Update printing.
 751         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 752         (arc_aux_regs): Add cpu field.
 753         * arc-regs.h: Add cpu field, lower case name aux registers.
 754
 755 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 756
 757         * arc-tbl.h: Add rtsc, sleep with no arguments.
 758
 759 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 760
 761         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 762         Initialize.
 763         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 764         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 765         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 766         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 767         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 768         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 769         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 770         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 771         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 772         (arc_opcode arc_opcodes): Null terminate the array.
 773         (arc_num_opcodes): Remove.
 774         * arc-ext.h (INSERT_XOP): Define.
 775         (extInstruction_t): Likewise.
 776         (arcExtMap_instName): Delete.
 777         (arcExtMap_insn): New function.
 778         (arcExtMap_genOpcode): Likewise.
 779         * arc-ext.c (ExtInstruction): Remove.
 780         (create_map): Zero initialize instruction fields.
 781         (arcExtMap_instName): Remove.
 782         (arcExtMap_insn): New function.
 783         (dump_ARC_extmap): More info while debuging.
 784         (arcExtMap_genOpcode): New function.
 785         * arc-dis.c (find_format): New function.
 786         (print_insn_arc): Use find_format.
 787         (arc_get_disassembler): Enable dump_ARC_extmap only when
 788         debugging.
 789
 790 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 791
 792         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 793         instruction bits out.
 794
 795 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 796
 797         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 798         * arc-opc.c (arc_flag_operands): Add new flags.
 799         (arc_flag_classes): Add new classes.
 800
 801 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 802
 803         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 804
 805 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 806
 807         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 808         encode1, rflt, crc16, and crc32 instructions.
 809         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 810         (arc_flag_classes): Add C_NPS_R.
 811         (insert_nps_bitop_size_2b): New function.
 812         (extract_nps_bitop_size_2b): Likewise.
 813         (insert_nps_bitop_uimm8): Likewise.
 814         (extract_nps_bitop_uimm8): Likewise.
 815         (arc_operands): Add new operand entries.
 816
 817 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 818
 819         * arc-regs.h: Add a new subclass field.  Add double assist
 820         accumulator register values.
 821         * arc-tbl.h: Use DPA subclass to mark the double assist
 822         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 823         * arc-opc.c (RSP): Define instead of SP.
 824         (arc_aux_regs): Add the subclass field.
 825
 826 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 827
 828         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 829
 830 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 831
 832         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 833         NPS_R_SRC1.
 834
 835 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 836
 837         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 838         issues.  No functional changes.
 839
 840 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 841
 842         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 843         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 844         (RTT): Remove duplicate.
 845         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 846         (PCT_CONFIG*): Remove.
 847         (D1L, D1H, D2H, D2L): Define.
 848
 849 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 850
 851         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 852
 853 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 854
 855         * arc-tbl.h (invld07): Remove.
 856         * arc-ext-tbl.h: New file.
 857         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 858         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 859
 860 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 861
 862         Fix -Wstack-usage warnings.
 863         * aarch64-dis.c (print_operands): Substitute size.
 864         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 865
 866 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 867
 868         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 869         to get a proper diagnostic when an invalid ASR register is used.
 870
 871 2016-03-22  Nick Clifton  <nickc@redhat.com>
 872
 873         * configure: Regenerate.
 874
 875 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 876
 877         * arc-nps400-tbl.h: New file.
 878         * arc-opc.c: Add top level comment.
 879         (insert_nps_3bit_dst): New function.
 880         (extract_nps_3bit_dst): New function.
 881         (insert_nps_3bit_src2): New function.
 882         (extract_nps_3bit_src2): New function.
 883         (insert_nps_bitop_size): New function.
 884         (extract_nps_bitop_size): New function.
 885         (arc_flag_operands): Add nps400 entries.
 886         (arc_flag_classes): Add nps400 entries.
 887         (arc_operands): Add nps400 entries.
 888         (arc_opcodes): Add nps400 include.
 889
 890 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 891
 892         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 893         the new class enum values.
 894
 895 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 896
 897         * arc-dis.c (print_insn_arc): Handle nps400.
 898
 899 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 900
 901         * arc-opc.c (BASE): Delete.
 902
 903 2016-03-18  Nick Clifton  <nickc@redhat.com>
 904
 905         PR target/19721
 906         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 907         of MOV insn that aliases an ORR insn.
 908
 909 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 910
 911         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 912
 913 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 914
 915         * mcore-opc.h: Add const qualifiers.
 916         * microblaze-opc.h (struct op_code_struct): Likewise.
 917         * sh-opc.h: Likewise.
 918         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 919         (tic4x_print_op): Likewise.
 920
 921 2016-03-02  Alan Modra  <amodra@gmail.com>
 922
 923         * or1k-desc.h: Regenerate.
 924         * fr30-ibld.c: Regenerate.
 925         * rl78-decode.c: Regenerate.
 926
 927 2016-03-01  Nick Clifton  <nickc@redhat.com>
 928
 929         PR target/19747
 930         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 931
 932 2016-02-24  Renlin Li  <renlin.li@arm.com>
 933
 934         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 935         (print_insn_coprocessor): Support fp16 instructions.
 936
 937 2016-02-24  Renlin Li  <renlin.li@arm.com>
 938
 939         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 940         vminnm, vrint(mpna).
 941
 942 2016-02-24  Renlin Li  <renlin.li@arm.com>
 943
 944         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 945         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 946
 947 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 948
 949         * i386-dis.c (print_insn): Parenthesize expression to prevent
 950         truncated addresses.
 951         (OP_J): Likewise.
 952
 953 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 954             Janek van Oirschot  <jvanoirs@synopsys.com>
 955
 956         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 957         variable.
 958
 959 2016-02-04  Nick Clifton  <nickc@redhat.com>
 960
 961         PR target/19561
 962         * msp430-dis.c (print_insn_msp430): Add a special case for
 963         decoding an RRC instruction with the ZC bit set in the extension
 964         word.
 965
 966 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 967
 968         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 969         * epiphany-ibld.c: Regenerate.
 970         * fr30-ibld.c: Regenerate.
 971         * frv-ibld.c: Regenerate.
 972         * ip2k-ibld.c: Regenerate.
 973         * iq2000-ibld.c: Regenerate.
 974         * lm32-ibld.c: Regenerate.
 975         * m32c-ibld.c: Regenerate.
 976         * m32r-ibld.c: Regenerate.
 977         * mep-ibld.c: Regenerate.
 978         * mt-ibld.c: Regenerate.
 979         * or1k-ibld.c: Regenerate.
 980         * xc16x-ibld.c: Regenerate.
 981         * xstormy16-ibld.c: Regenerate.
 982
 983 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 984
 985         * epiphany-dis.c: Regenerated from latest cpu files.
 986
 987 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 988
 989         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 990         test bit.
 991
 992 2016-01-25  Renlin Li  <renlin.li@arm.com>
 993
 994         * arm-dis.c (mapping_symbol_for_insn): New function.
 995         (find_ifthen_state): Call mapping_symbol_for_insn().
 996
 997 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 998
 999         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1000         of MSR UAO immediate operand.
1001
1002 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1003
1004         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1005         instruction support.
1006
1007 2016-01-17  Alan Modra  <amodra@gmail.com>
1008
1009         * configure: Regenerate.
1010
1011 2016-01-14  Nick Clifton  <nickc@redhat.com>
1012
1013         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1014         instructions that can support stack pointer operations.
1015         * rl78-decode.c: Regenerate.
1016         * rl78-dis.c: Fix display of stack pointer in MOVW based
1017         instructions.
1018
1019 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1020
1021         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1022         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1023         erxtatus_el1 and erxaddr_el1.
1024
1025 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1026
1027         * arm-dis.c (arm_opcodes): Add "esb".
1028         (thumb_opcodes): Likewise.
1029
1030 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1031
1032         * ppc-opc.c <xscmpnedp>: Delete.
1033         <xvcmpnedp>: Likewise.
1034         <xvcmpnedp.>: Likewise.
1035         <xvcmpnesp>: Likewise.
1036         <xvcmpnesp.>: Likewise.
1037
1038 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1039
1040         PR gas/13050
1041         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1042         addition to ISA_A.
1043
1044 2016-01-01  Alan Modra  <amodra@gmail.com>
1045
1046         Update year range in copyright notice of all files.
1047
1048 For older changes see ChangeLog-2015
1049 \f
1050 Copyright (C) 2016 Free Software Foundation, Inc.
1051
1052 Copying and distribution of this file, with or without modification,
1053 are permitted in any medium without royalty provided the copyright
1054 notice and this notice are preserved.
1055
1056 Local Variables:
1057 mode: change-log
1058 left-margin: 8
1059 fill-column: 74
1060 version-control: never
1061 End: