opcodes/ChangeLog

   1 2013-12-17  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
   2
   3         * i386-dis.c (MOD_FF_REG_3): New.
   4         (MOD_FF_REG_5): Likewise.
   5         (mod_table): Add MOD_FF_REG_3 and MOD_FF_REG_5.
   6         (reg_table): Use MOD_FF_REG_3 and MOD_FF_REG_5.
   7
   8 2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
   9
  10         * mips-dis.c: Add mips_cp1_names pointer.
  11         (mips_cp1_names_numeric): New array.
  12         (mips_cp1_names_mips3264): New array.
  13         (mips_arch_choice): Add cp1_names.
  14         (mips_arch_choices): Add relevant cp1 register name array to each of
  15         the elements.
  16         (set_default_mips_dis_options): Add support for setting up the
  17         mips_cp1_names pointer.
  18         (parse_mips_dis_option): Add support for the cp1-names command line
  19         variable.  Also setup the mips_cp1_names pointer.
  20         (print_reg): Print out name of the cp1 register.
  21
  22 2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
  23
  24         * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
  25         +v and +w.
  26         (micromips_opcodes): Reduced element index range for sldi, splati,
  27         copy_s, copy_u, insert and insve instructions.
  28         * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
  29         +v and +w.
  30         (mips_builtin_opcodes): Reduced element index range for sldi, splati,
  31         copy_s, copy_u, insert and insve instructions.
  32
  33 2013-12-13  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
  34
  35         * nds32-dis.c (mnemonic_96): Fix typo.
  36
  37 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  38             Wei-Cheng Wang  <cole945@gmail.com>
  39
  40         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c
  41         and nds32-dis.c.
  42         * Makefile.in: Regenerate.
  43         * configure.in: Add case for bfd_nds32_arch.
  44         * configure: Regenerate.
  45         * disassemble.c (ARCH_nds32): Define.
  46         * nds32-asm.c: New file for nds32.
  47         * nds32-asm.h: New file for nds32.
  48         * nds32-dis.c: New file for nds32.
  49         * nds32-opc.h: New file for nds32.
  50
  51 2013-12-05  Nick Clifton  <nickc@redhat.com>
  52
  53         * s390-mkopc.c (dumpTable): Provide a format string to printf so
  54         that compiling with -Werror=format-security does not produce an
  55         error.
  56
  57 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  58
  59         * aarch64-opc.c (aarch64_pstatefields): Update.
  60
  61 2013-11-19  Catherine Moore  <clm@codesourcery.com>
  62
  63         * micromips-opc.c (LM): Define.
  64         (micromips_opcodes): Add LM to load instructions.
  65         * mips-opc.c (prefe): Add LM attribute.
  66
  67 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
  68
  69         Revert
  70
  71         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  72
  73         * aarch64-opc.c (CPENT): New define.
  74         (F_READONLY, F_WRITEONLY): Likewise.
  75         (aarch64_sys_regs): Add trace unit registers.
  76         (aarch64_sys_reg_readonly_p): New function.
  77         (aarch64_sys_reg_writeonly_p): Ditto.
  78
  79 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  80
  81         * aarch64-opc.c (CPENT): New define.
  82         (F_READONLY, F_WRITEONLY): Likewise.
  83         (aarch64_sys_regs): Add trace unit registers.
  84         (aarch64_sys_reg_readonly_p): New function.
  85         (aarch64_sys_reg_writeonly_p): Ditto.
  86
  87 2013-11-15  Maciej W. Rozycki  <macro@codesourcery.com>
  88
  89         * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
  90         "mtcr".
  91
  92 2013-11-11  Catherine Moore  <clm@codesourcery.com>
  93
  94         * mips-dis.c (print_insn_mips): Use
  95         INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
  96         (print_insn_micromips): Likewise.
  97         * mips-opc.c (LDD): Remove.
  98         (CLD): Include INSN_LOAD_MEMORY.
  99         (LM): New.
 100         (mips_builtin_opcodes): Use LM instead of LDD.
 101         Add LM to load instructions.
 102
 103 2013-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 104
 105         PR gas/16140
 106         * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
 107         * i386-init.h: Regenerated.
 108
 109 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 110
 111         * aarch64-opc.c (F_DEPRECATED): New macro.
 112         (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
 113         F_DEPRECATED.
 114         (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
 115         AARCH64_OPND_SYSREG.
 116
 117 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 118
 119         * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
 120         (convert_from_csel): Likewise.
 121         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 122         AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
 123         (aarch64_print_operand): Handle AARCH64_OPND_COND1.
 124         * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
 125         COND for cinc, cset, cinv, csetm and cneg.
 126         (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
 127         * aarch64-asm-2.c: Re-generated.
 128         * aarch64-dis-2.c: Ditto.
 129         * aarch64-opc-2.c: Ditto.
 130
 131 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 132
 133         * aarch64-opc.c (set_syntax_error): New function.
 134         (operand_general_constraint_met_p): Replace set_other_error
 135         with set_syntax_error.
 136
 137 2013-10-30  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 138
 139         * s390-dis.c (init_disasm): Default to full 'zarch' opcode
 140         availability even for 31-bit programs.
 141
 142 2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 143
 144         * arm-dis.c (neon_opcodes): Adjust print string for vshll.
 145
 146 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 147
 148         * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
 149         +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
 150         +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 151         (MSA): New define.
 152         (MSA64): New define.
 153         (micromips_opcodes): Add MSA instructions.
 154         * mips-dis.c (msa_control_names): New array.
 155         (mips_abi_choice): Add ASE_MSA to mips32r2.
 156         Remove ASE_MDMX from mips64r2.
 157         Add ASE_MSA and ASE_MSA64 to mips64r2.
 158         (parse_mips_dis_option): Handle -Mmsa.
 159         (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
 160         (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
 161         (print_mips_disassembler_options): Print -Mmsa.
 162         * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
 163         +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 164         (MSA): New define.
 165         (MSA64): New define.
 166         (mips_builtin_op): Add MSA instructions.
 167
 168 2013-10-13  Sandra Loosemore  <sandra@codesourcery.com>
 169
 170         * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
 171         as the primary name of r30.
 172
 173 2013-10-12  Jan Beulich <jbeulich@suse.com>
 174
 175         * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
 176         default case.
 177         (OP_E_register): Move v_bnd_mode alongside m_mode.
 178         * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
 179         Drop Reg16 and Disp16. Add NoRex64.
 180         (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
 181         * i386-tbl.h: Re-generate.
 182
 183 2013-10-10  Sean Keys <skeys@ipdatasys.com>
 184
 185         * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
 186         table.
 187         * xgate-dis.c (print_insn): Refactor to work with table change.
 188
 189 2013-10-10  Roland McGrath  <mcgrathr@google.com>
 190
 191         * i386-dis.c (oappend_maybe_intel): New function.
 192         (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
 193         (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
 194         (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
 195
 196         * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
 197         possible compiler warnings when the union's initializer is
 198         actually meant for the 'preg' enum typed member.
 199         * crx-opc.c (REG): Likewise.
 200
 201         * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
 202         Remove duplicate const qualifier.
 203
 204 2013-10-08  Jan Beulich <jbeulich@suse.com>
 205
 206         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
 207         (clflush): Use Anysize instead of Byte|Unspecified.
 208         (prefetch*): Likewise.
 209         * i386-tbl.h: Re-generate.
 210
 211 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 212
 213         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
 214
 215 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 216
 217         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
 218         * i386-init.h: Regenerated.
 219
 220 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 221
 222         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
 223         * i386-init.h: Regenerated.
 224
 225 2013-09-20  Alan Modra  <amodra@gmail.com>
 226
 227         * configure: Regenerate.
 228
 229 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 230
 231         * s390-opc.txt (clih): Make the immediate unsigned.
 232
 233 2013-09-04  Roland McGrath  <mcgrathr@google.com>
 234
 235         PR gas/15914
 236         * arm-dis.c (arm_opcodes): Add udf.
 237         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
 238         (thumb32_opcodes): Add udf.w.
 239         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
 240
 241 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 242
 243         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
 244         For the load fp integer instructions only the suppression flag was
 245         new with z196 version.
 246
 247 2013-08-28  Nick Clifton  <nickc@redhat.com>
 248
 249         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
 250         immediate is not suitable for the 32-bit ABI.
 251
 252 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
 253
 254         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
 255         replacing NODS.
 256
 257 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 258
 259         PR binutils/15834
 260         * aarch64-asm.c: Fix typos.
 261         * aarch64-dis.c: Likewise.
 262         * msp430-dis.c: Likewise.
 263
 264 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 265
 266         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
 267         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
 268         Use +H rather than +C for the real "dext".
 269         * mips-opc.c (mips_builtin_opcodes): Likewise.
 270
 271 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 272
 273         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
 274         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
 275         and OPTIONAL_MAPPED_REG.
 276         * mips-opc.c (decode_mips_operand): Likewise.
 277         * mips16-opc.c (decode_mips16_operand): Likewise.
 278         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
 279
 280 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
 281
 282         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
 283         (PREFIX_EVEX_0F3A3F): Likewise.
 284         * i386-dis-evex.h (evex_table): Updated.
 285
 286 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
 287
 288         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
 289         VCLIPW.
 290
 291 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
 292             Konrad Eisele  <konrad@gaisler.com>
 293
 294         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
 295         bfd_mach_sparc.
 296         * sparc-opc.c (MASK_LEON): Define.
 297         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
 298         (letandleon): New macro.
 299         (v9andleon): Likewise.
 300         (sparc_opc): Add leon.
 301         (umac): Enable for letandleon.
 302         (smac): Likewise.
 303         (casa): Enable for v9andleon.
 304         (cas): Likewise.
 305         (casl): Likewise.
 306
 307 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 308             Richard Sandiford  <rdsandiford@googlemail.com>
 309
 310         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 311         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 312         (print_vu0_channel): New function.
 313         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 314         (print_insn_args): Handle '#'.
 315         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 316         * mips-opc.c (mips_vu0_channel_mask): New constant.
 317         (decode_mips_operand): Handle new VU0 operand types.
 318         (VU0, VU0CH): New macros.
 319         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 320         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 321         Use "+6" rather than "G" for QMFC2 and QMTC2.
 322
 323 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 324
 325         * mips-formats.h (PCREL): Reorder parameters and update the definition
 326         to match new mips_pcrel_operand layout.
 327         (JUMP, JALX, BRANCH): Update accordingly.
 328         * mips16-opc.c (decode_mips16_operand): Likewise.
 329
 330 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 331
 332         * micromips-opc.c (WR_s): Delete.
 333
 334 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 335
 336         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 337         New macros.
 338         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 339         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 340         (mips_builtin_opcodes): Use the new position-based read-write flags
 341         instead of field-based ones.  Use UDI for "udi..." instructions.
 342         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 343         New macros.
 344         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 345         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 346         (WR_SP, RD_16): New macros.
 347         (RD_SP): Redefine as an INSN2_* flag.
 348         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 349         (mips16_opcodes): Use the new position-based read-write flags
 350         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 351         pinfo2 field.
 352         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 353         New macros.
 354         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 355         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 356         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 357         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 358         (micromips_opcodes): Use the new position-based read-write flags
 359         instead of field-based ones.
 360         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 361         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 362         of field-based flags.
 363
 364 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 365
 366         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 367         (WR_SP): Replace with...
 368         (MOD_SP): ...this.
 369         (mips16_opcodes): Update accordingly.
 370         * mips-dis.c (print_insn_mips16): Likewise.
 371
 372 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 373
 374         * mips16-opc.c (mips16_opcodes): Reformat.
 375
 376 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 377
 378         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 379         for operands that are hard-coded to $0.
 380         * micromips-opc.c (micromips_opcodes): Likewise.
 381
 382 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 383
 384         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 385         for the single-operand forms of JALR and JALR.HB.
 386         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 387         and JALRS.HB.
 388
 389 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 390
 391         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 392         instructions.  Fix them to use WR_MACC instead of WR_CC and
 393         add missing RD_MACCs.
 394
 395 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 396
 397         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 398
 399 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 400
 401         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 402
 403 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 404             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 405             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 406             Sergey Lega  <sergey.s.lega@intel.com>
 407             Anna Tikhonova  <anna.tikhonova@intel.com>
 408             Ilya Tocar  <ilya.tocar@intel.com>
 409             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 410             Ilya Verbin  <ilya.verbin@intel.com>
 411             Kirill Yukhin  <kirill.yukhin@intel.com>
 412             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 413
 414         * i386-dis-evex.h: New.
 415         * i386-dis.c (OP_Rounding): New.
 416         (VPCMP_Fixup): New.
 417         (OP_Mask): New.
 418         (Rdq): New.
 419         (XMxmmq): New.
 420         (EXdScalarS): New.
 421         (EXymm): New.
 422         (EXEvexHalfBcstXmmq): New.
 423         (EXxmm_mdq): New.
 424         (EXEvexXGscat): New.
 425         (EXEvexXNoBcst): New.
 426         (VPCMP): New.
 427         (EXxEVexR): New.
 428         (EXxEVexS): New.
 429         (XMask): New.
 430         (MaskG): New.
 431         (MaskE): New.
 432         (MaskR): New.
 433         (MaskVex): New.
 434         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 435         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 436         evex_rounding_mode, evex_sae_mode, mask_mode.
 437         (USE_EVEX_TABLE): New.
 438         (EVEX_TABLE): New.
 439         (EVEX enum): New.
 440         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 441         REG_EVEX_0F38C7.
 442         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 443         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 444         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 445         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 446         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 447         MOD_EVEX_0F38C7_REG_6.
 448         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 449         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 450         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 451         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 452         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 453         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 454         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 455         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 456         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 457         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 458         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 459         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 460         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 461         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 462         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 463         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 464         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 465         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 466         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 467         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 468         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 469         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 470         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 471         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 472         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 473         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 474         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 475         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 476         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 477         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 478         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 479         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 480         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 481         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 482         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 483         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 484         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 485         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 486         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 487         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 488         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 489         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 490         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 491         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 492         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 493         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 494         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 495         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 496         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 497         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 498         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 499         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 500         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 501         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 502         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 503         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 504         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 505         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 506         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 507         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 508         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 509         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 510         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 511         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 512         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 513         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 514         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 515         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 516         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 517         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 518         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 519         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 520         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 521         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 522         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 523         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 524         PREFIX_EVEX_0F3A55.
 525         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 526         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 527         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 528         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 529         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 530         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 531         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 532         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 533         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 534         VEX_W_0F3A32_P_2_LEN_0.
 535         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 536         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 537         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 538         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 539         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 540         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 541         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 542         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 543         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 544         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 545         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 546         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 547         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 548         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 549         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 550         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 551         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 552         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 553         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 554         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 555         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 556         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 557         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 558         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 559         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 560         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 561         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 562         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 563         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 564         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 565         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 566         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 567         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 568         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 569         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 570         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 571         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 572         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 573         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 574         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 575         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 576         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 577         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 578         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 579         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 580         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 581         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 582         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 583         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 584         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 585         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 586         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 587         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 588         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 589         (struct vex): Add fields evex, r, v, mask_register_specifier,
 590         zeroing, ll, b.
 591         (intel_names_xmm): Add upper 16 registers.
 592         (att_names_xmm): Ditto.
 593         (intel_names_ymm): Ditto.
 594         (att_names_ymm): Ditto.
 595         (names_zmm): New.
 596         (intel_names_zmm): Ditto.
 597         (att_names_zmm): Ditto.
 598         (names_mask): Ditto.
 599         (intel_names_mask): Ditto.
 600         (att_names_mask): Ditto.
 601         (names_rounding): Ditto.
 602         (names_broadcast): Ditto.
 603         (x86_64_table): Add escape to evex-table.
 604         (reg_table): Include reg_table evex-entries from
 605         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 606         (prefix_table): Add entries for new instructions.
 607         (vex_table): Ditto.
 608         (vex_len_table): Ditto.
 609         (vex_w_table): Ditto.
 610         (mod_table): Ditto.
 611         (get_valid_dis386): Properly handle new instructions.
 612         (print_insn): Handle zmm and mask registers, print mask operand.
 613         (intel_operand_size): Support EVEX, new modes and sizes.
 614         (OP_E_register): Handle new modes.
 615         (OP_E_memory): Ditto.
 616         (OP_G): Ditto.
 617         (OP_XMM): Ditto.
 618         (OP_EX): Ditto.
 619         (OP_VEX): Ditto.
 620         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 621         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 622         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 623         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 624         CpuAVX512PF and CpuVREX.
 625         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 626         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 627         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 628         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 629         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 630         * i386-init.h: Regenerate.
 631         * i386-opc.h (CpuAVX512F): New.
 632         (CpuAVX512CD): New.
 633         (CpuAVX512ER): New.
 634         (CpuAVX512PF): New.
 635         (CpuVREX): New.
 636         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 637         cpuavx512pf and cpuvrex fields.
 638         (VecSIB): Add VecSIB512.
 639         (EVex): New.
 640         (Masking): New.
 641         (VecESize): New.
 642         (Broadcast): New.
 643         (StaticRounding): New.
 644         (SAE): New.
 645         (Disp8MemShift): New.
 646         (NoDefMask): New.
 647         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 648         staticrounding, sae, disp8memshift and nodefmask.
 649         (RegZMM): New.
 650         (Zmmword): Ditto.
 651         (Vec_Disp8): Ditto.
 652         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 653         fields.
 654         (RegVRex): New.
 655         * i386-opc.tbl: Add AVX512 instructions.
 656         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 657         registers, mask registers.
 658         * i386-tbl.h: Regenerate.
 659
 660 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 661
 662         PR gas/15220
 663         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 664         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 665
 666 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 667
 668         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 669         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 670         PREFIX_0F3ACC.
 671         (prefix_table): Updated.
 672         (three_byte_table): Likewise.
 673         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 674         (cpu_flags): Add CpuSHA.
 675         (i386_cpu_flags): Add cpusha.
 676         * i386-init.h: Regenerate.
 677         * i386-opc.h (CpuSHA): New.
 678         (CpuUnused): Restored.
 679         (i386_cpu_flags): Add cpusha.
 680         * i386-opc.tbl: Add SHA instructions.
 681         * i386-tbl.h: Regenerate.
 682
 683 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 684             Kirill Yukhin  <kirill.yukhin@intel.com>
 685             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 686
 687         * i386-dis.c (BND_Fixup): New.
 688         (Ebnd): New.
 689         (Ev_bnd): New.
 690         (Gbnd): New.
 691         (BND): New.
 692         (v_bnd_mode): New.
 693         (bnd_mode): New.
 694         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 695         MOD_0F1B_PREFIX_1.
 696         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 697         (dis tables): Replace XX with BND for near branch and call
 698         instructions.
 699         (prefix_table): Add new entries.
 700         (mod_table): Likewise.
 701         (names_bnd): New.
 702         (intel_names_bnd): New.
 703         (att_names_bnd): New.
 704         (BND_PREFIX): New.
 705         (prefix_name): Handle BND_PREFIX.
 706         (print_insn): Initialize names_bnd.
 707         (intel_operand_size): Handle new modes.
 708         (OP_E_register): Likewise.
 709         (OP_E_memory): Likewise.
 710         (OP_G): Likewise.
 711         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 712         (cpu_flags): Add CpuMPX.
 713         (operand_type_init): Add RegBND.
 714         (opcode_modifiers): Add BNDPrefixOk.
 715         (operand_types): Add RegBND.
 716         * i386-init.h: Regenerate.
 717         * i386-opc.h (CpuMPX): New.
 718         (CpuUnused): Comment out.
 719         (i386_cpu_flags): Add cpumpx.
 720         (BNDPrefixOk): New.
 721         (i386_opcode_modifier): Add bndprefixok.
 722         (RegBND): New.
 723         (i386_operand_type): Add regbnd.
 724         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 725         Add MPX instructions and bnd prefix.
 726         * i386-reg.tbl: Add bnd0-bnd3 registers.
 727         * i386-tbl.h: Regenerate.
 728
 729 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 730
 731         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 732         ATTRIBUTE_UNUSED.
 733
 734 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 735
 736         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 737         special rules.
 738         * Makefile.in: Regenerate.
 739         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 740         all fields.  Reformat.
 741
 742 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 743
 744         * mips16-opc.c: Include mips-formats.h.
 745         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 746         static arrays.
 747         (decode_mips16_operand): New function.
 748         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 749         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 750         Abort for OP_SAVE_RESTORE_LIST.
 751         (print_mips16_insn_arg): Change interface.  Use mips_operand
 752         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 753         (print_insn_mips16): ...here.  Call init_print_arg_state.
 754         Update the call to print_mips16_insn_arg.
 755
 756 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 757
 758         * mips-formats.h: New file.
 759         * mips-opc.c: Include mips-formats.h.
 760         (reg_0_map): New static array.
 761         (decode_mips_operand): New function.
 762         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 763         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 764         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 765         (int_c_map): New static arrays.
 766         (decode_micromips_operand): New function.
 767         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 768         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 769         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 770         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 771         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 772         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 773         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 774         (print_reg): New function.
 775         (mips_print_arg_state): New structure.
 776         (init_print_arg_state, print_insn_arg): New functions.
 777         (print_insn_args): Change interface and use mips_operand structures.
 778         Delete GET_OP_S.  Move GET_OP definition to...
 779         (print_insn_mips): ...here.  Update the call to print_insn_args.
 780         (print_insn_micromips): Use print_insn_args.
 781
 782 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 783
 784         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 785         in macros.
 786
 787 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 788
 789         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 790         ADDA.S, MULA.S and SUBA.S.
 791
 792 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 793
 794         PR gas/13572
 795         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 796         * i386-tbl.h: Regenerated.
 797
 798 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 799
 800         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 801         and SD A(B) macros up.
 802         * micromips-opc.c (micromips_opcodes): Likewise.
 803
 804 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 805
 806         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 807         instructions.
 808
 809 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 810
 811         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 812         MDMX-like instructions.
 813         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 814         printing "Q" operands for INSN_5400 instructions.
 815
 816 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 817
 818         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 819         "+S" for "cins".
 820         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 821         Combine cases.
 822
 823 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 824
 825         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 826         "jalx".
 827         * mips16-opc.c (mips16_opcodes): Likewise.
 828         * micromips-opc.c (micromips_opcodes): Likewise.
 829         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 830         (print_insn_mips16): Handle "+i".
 831         (print_insn_micromips): Likewise.  Conditionally preserve the
 832         ISA bit for "a" but not for "+i".
 833
 834 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 835
 836         * micromips-opc.c (WR_mhi): Rename to..
 837         (WR_mh): ...this.
 838         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 839         "mh,mi" with "mh".
 840         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 841         (micromips_to_32_reg_h_map1): ...this.
 842         (micromips_to_32_reg_i_map): Rename to...
 843         (micromips_to_32_reg_h_map2): ...this.
 844         (print_micromips_insn): Remove "mi" case.  Print both registers
 845         in the pair for "mh".
 846
 847 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 848
 849         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 850         * micromips-opc.c (micromips_opcodes): Likewise.
 851         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 852         and "+T" handling.  Check for a "0" suffix when deciding whether to
 853         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 854
 855 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 856
 857         * s390-opc.c (J12_12, J24_24): New macros.
 858         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 859         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 860         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 861
 862 2013-07-04  Alan Modra  <amodra@gmail.com>
 863
 864         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 865
 866 2013-06-26  Nick Clifton  <nickc@redhat.com>
 867
 868         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 869         field when checking for type 2 nop.
 870         * rx-decode.c: Regenerate.
 871
 872 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 873
 874         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 875         and "movep" macros.
 876
 877 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 878
 879         * mips-dis.c (is_mips16_plt_tail): New function.
 880         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 881         word.
 882         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 883
 884 2013-06-21  DJ Delorie  <dj@redhat.com>
 885
 886         * msp430-decode.opc: New.
 887         * msp430-decode.c: New/generated.
 888         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 889         (MAINTAINER_CLEANFILES): Likewise.
 890         Add rule to build msp430-decode.c frommsp430decode.opc
 891         using the opc2c program.
 892         * Makefile.in: Regenerate.
 893         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 894         * configure: Regenerate.
 895
 896 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 897
 898         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 899         (SYMTAB_AVAILABLE): Removed.
 900         (#include "elf/aarch64.h): Ditto.
 901
 902 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 903             Maciej W. Rozycki  <macro@codesourcery.com>
 904             Chao-Ying Fu  <fu@mips.com>
 905
 906         * micromips-opc.c (EVA): Define.
 907         (TLBINV): Define.
 908         (micromips_opcodes): Add EVA opcodes.
 909         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 910         (print_insn_args): Handle EVA offsets.
 911         (print_insn_micromips): Likewise.
 912         * mips-opc.c (EVA): Define.
 913         (TLBINV): Define.
 914         (mips_builtin_opcodes): Add EVA opcodes.
 915
 916 2013-06-17  Alan Modra  <amodra@gmail.com>
 917
 918         * Makefile.am (mips-opc.lo): Add rules to create automatic
 919         dependency files.  Pass archdefs.
 920         (micromips-opc.lo, mips16-opc.lo): Likewise.
 921         * Makefile.in: Regenerate.
 922
 923 2013-06-14  DJ Delorie  <dj@redhat.com>
 924
 925         * rx-decode.opc (rx_decode_opcode): Bit operations on
 926         registers are 32-bit operations, not 8-bit operations.
 927         * rx-decode.c: Regenerate.
 928
 929 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 930
 931         * micromips-opc.c (IVIRT): New define.
 932         (IVIRT64): New define.
 933         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 934         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 935
 936         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 937         dmtgc0 to print cp0 names.
 938
 939 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 940
 941         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 942         argument.
 943
 944 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 945             Richard Sandiford  <rdsandiford@googlemail.com>
 946
 947         * micromips-opc.c (D32, D33, MC): Update definitions.
 948         (micromips_opcodes):  Initialize ase field.
 949         * mips-dis.c (mips_arch_choice): Add ase field.
 950         (mips_arch_choices): Initialize ase field.
 951         (set_default_mips_dis_options): Declare and setup mips_ase.
 952         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 953         MT32, MC): Update definitions.
 954         (mips_builtin_opcodes): Initialize ase field.
 955
 956 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 957
 958         * s390-opc.txt (flogr): Require a register pair destination.
 959
 960 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 961
 962         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 963         instruction format.
 964
 965 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 966
 967         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 968
 969 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 970
 971         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 972         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 973         XLS_MASK, PPCVSX2): New defines.
 974         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 975         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 976         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 977         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 978         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 979         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 980         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 981         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 982         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 983         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 984         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 985         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 986         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 987         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 988         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 989         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 990         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 991         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 992         <lxvx, stxvx>: New extended mnemonics.
 993
 994 2013-05-17  Alan Modra  <amodra@gmail.com>
 995
 996         * ia64-raw.tbl: Replace non-ASCII char.
 997         * ia64-waw.tbl: Likewise.
 998         * ia64-asmtab.c: Regenerate.
 999
1000 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
1001
1002         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
1003         * i386-init.h: Regenerated.
1004
1005 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
1006
1007         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
1008         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
1009         check from [0, 255] to [-128, 255].
1010
1011 2013-05-09  Andrew Pinski  <apinski@cavium.com>
1012
1013         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
1014         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
1015         (parse_mips_dis_option): Handle the virt option.
1016         (print_insn_args): Handle "+J".
1017         (print_mips_disassembler_options): Print out message about virt64.
1018         * mips-opc.c (IVIRT): New define.
1019         (IVIRT64): New define.
1020         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
1021         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
1022         Move rfe to the bottom as it conflicts with tlbgp.
1023
1024 2013-05-09  Alan Modra  <amodra@gmail.com>
1025
1026         * ppc-opc.c (extract_vlesi): Properly sign extend.
1027         (extract_vlensi): Likewise.  Comment reason for setting invalid.
1028
1029 2013-05-02  Nick Clifton  <nickc@redhat.com>
1030
1031         * msp430-dis.c: Add support for MSP430X instructions.
1032
1033 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
1034
1035         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
1036         to "eccinj".
1037
1038 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
1039
1040         PR binutils/15369
1041         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
1042         of CGEN_CPU_ENDIAN.
1043         (hash_insns_list): Likewise.
1044
1045 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
1046
1047         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
1048         warning workaround.
1049
1050 2013-04-08  Jan Beulich <jbeulich@suse.com>
1051
1052         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
1053         * i386-tbl.h: Re-generate.
1054
1055 2013-04-06  David S. Miller  <davem@davemloft.net>
1056
1057         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
1058         of an opcode, prefer the one with F_PREFERRED set.
1059         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
1060         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
1061         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
1062         mark existing mnenomics as aliases.  Add "cc" suffix to edge
1063         instructions generating condition codes, mark existing mnenomics
1064         as aliases.  Add "fp" prefix to VIS compare instructions, mark
1065         existing mnenomics as aliases.
1066
1067 2013-04-03  Nick Clifton  <nickc@redhat.com>
1068
1069         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
1070         destination address by subtracting the operand from the current
1071         address.
1072         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
1073         a positive value in the insn.
1074         (extract_u16_loop): Do not negate the returned value.
1075         (D16_LOOP): Add V850_INVERSE_PCREL flag.
1076
1077         (ceilf.sw): Remove duplicate entry.
1078         (cvtf.hs): New entry.
1079         (cvtf.sh): Likewise.
1080         (fmaf.s): Likewise.
1081         (fmsf.s): Likewise.
1082         (fnmaf.s): Likewise.
1083         (fnmsf.s): Likewise.
1084         (maddf.s): Restrict to E3V5 architectures.
1085         (msubf.s): Likewise.
1086         (nmaddf.s): Likewise.
1087         (nmsubf.s): Likewise.
1088
1089 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
1090
1091         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
1092         check address mode.
1093         (print_insn): Pass sizeflag to get_sib.
1094
1095 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
1096
1097         PR binutils/15068
1098         * tic6x-dis.c: Add support for displaying 16-bit insns.
1099
1100 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
1101
1102         PR gas/15095
1103         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1104         individual msb and lsb halves in src1 & src2 fields.  Discard the
1105         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1106         follow what Ti SDK does in that case as any value in the src1
1107         field yields the same output with SDK disassembler.
1108
1109 2013-03-12  Michael Eager <eager@eagercon.com>
1110
1111         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
1112
1113 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1114
1115         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1116
1117 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1118
1119         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1120
1121 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1122
1123         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1124
1125 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1126
1127         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1128         (thumb32_opcodes): Likewise.
1129         (print_insn_thumb32): Handle 'S' control char.
1130
1131 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
1132
1133         * lm32-desc.c: Regenerate.
1134
1135 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1136
1137         * i386-reg.tbl (riz): Add RegRex64.
1138         * i386-tbl.h: Regenerated.
1139
1140 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
1141
1142         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1143         (aarch64_feature_crc): New static.
1144         (CRC): New macro.
1145         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1146         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1147         * aarch64-asm-2.c: Re-generate.
1148         * aarch64-dis-2.c: Ditto.
1149         * aarch64-opc-2.c: Ditto.
1150
1151 2013-02-27  Alan Modra  <amodra@gmail.com>
1152
1153         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1154         * rl78-decode.c: Regenerate.
1155
1156 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
1157
1158         * rl78-decode.opc: Fix encoding of DIVWU insn.
1159         * rl78-decode.c: Regenerate.
1160
1161 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
1162
1163         PR gas/15159
1164         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1165
1166         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1167         (cpu_flags): Add CpuSMAP.
1168
1169         * i386-opc.h (CpuSMAP): New.
1170         (i386_cpu_flags): Add cpusmap.
1171
1172         * i386-opc.tbl: Add clac and stac.
1173
1174         * i386-init.h: Regenerated.
1175         * i386-tbl.h: Likewise.
1176
1177 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
1178
1179         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1180         which also makes the disassembler output be in little
1181         endian like it should be.
1182
1183 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
1184
1185         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1186         fields to NULL.
1187         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1188
1189 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
1190
1191         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1192         section disassembled.
1193
1194 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1195
1196         * arm-dis.c: Update strht pattern.
1197
1198 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
1199
1200         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1201         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
1202         trunc.w.s macro for EE.
1203
1204 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1205             Andrew Jenner <andrew@codesourcery.com>
1206
1207         Based on patches from Altera Corporation.
1208
1209         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1210         nios2-opc.c.
1211         * Makefile.in: Regenerated.
1212         * configure.in: Add case for bfd_nios2_arch.
1213         * configure: Regenerated.
1214         * disassemble.c (ARCH_nios2): Define.
1215         (disassembler): Add case for bfd_arch_nios2.
1216         * nios2-dis.c: New file.
1217         * nios2-opc.c: New file.
1218
1219 2013-02-04  Alan Modra  <amodra@gmail.com>
1220
1221         * po/POTFILES.in: Regenerate.
1222         * rl78-decode.c: Regenerate.
1223         * rx-decode.c: Regenerate.
1224
1225 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1226
1227         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1228         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1229         * aarch64-asm.c (convert_xtl_to_shll): New function.
1230         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1231         calling convert_xtl_to_shll.
1232         * aarch64-dis.c (convert_shll_to_xtl): New function.
1233         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1234         calling convert_shll_to_xtl.
1235         * aarch64-gen.c: Update copyright year.
1236         * aarch64-asm-2.c: Re-generate.
1237         * aarch64-dis-2.c: Re-generate.
1238         * aarch64-opc-2.c: Re-generate.
1239
1240 2013-01-24  Nick Clifton  <nickc@redhat.com>
1241
1242         * v850-dis.c: Add support for e3v5 architecture.
1243         * v850-opc.c: Likewise.
1244
1245 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1246
1247         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1248         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1249         * aarch64-opc.c (operand_general_constraint_met_p): For
1250         AARCH64_MOD_LSL, move the range check on the shift amount before the
1251         alignment check; change to call set_sft_amount_out_of_range_error
1252         instead of set_imm_out_of_range_error.
1253         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1254         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1255         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1256         SIMD_IMM_SFT.
1257
1258 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1259
1260         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1261
1262         * i386-init.h: Regenerated.
1263         * i386-tbl.h: Likewise.
1264
1265 2013-01-15  Nick Clifton  <nickc@redhat.com>
1266
1267         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1268         values.
1269         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1270
1271 2013-01-14  Will Newton <will.newton@imgtec.com>
1272
1273         * metag-dis.c (REG_WIDTH): Increase to 64.
1274
1275 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1276
1277         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1278         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1279         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1280         (SH6): Update.
1281         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1282         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1283         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1284         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1285
1286 2013-01-10  Will Newton <will.newton@imgtec.com>
1287
1288         * Makefile.am: Add Meta.
1289         * configure.in: Add Meta.
1290         * disassemble.c: Add Meta support.
1291         * metag-dis.c: New file.
1292         * Makefile.in: Regenerate.
1293         * configure: Regenerate.
1294
1295 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1296
1297         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1298         (match_opcode): Rename to cr16_match_opcode.
1299
1300 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1301
1302         * mips-dis.c: Add names for CP0 registers of r5900.
1303         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1304         instructions sq and lq.
1305         Add support for MIPS r5900 CPU.
1306         Add support for 128 bit MMI (Multimedia Instructions).
1307         Add support for EE instructions (Emotion Engine).
1308         Disable unsupported floating point instructions (64 bit and
1309         undefined compare operations).
1310         Enable instructions of MIPS ISA IV which are supported by r5900.
1311         Disable 64 bit co processor instructions.
1312         Disable 64 bit multiplication and division instructions.
1313         Disable instructions for co-processor 2 and 3, because these are
1314         not supported (preparation for later VU0 support (Vector Unit)).
1315         Disable cvt.w.s because this behaves like trunc.w.s and the
1316         correct execution can't be ensured on r5900.
1317         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1318         will confuse less developers and compilers.
1319
1320 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1321
1322         * aarch64-opc.c (aarch64_print_operand): Change to print
1323         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1324         in comment.
1325         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1326         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1327         OP_MOV_IMM_WIDE.
1328
1329 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1330
1331         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1332         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1333
1334 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1335
1336         * i386-gen.c (process_copyright): Update copyright year to 2013.
1337
1338 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1339
1340         * cr16-dis.c (match_opcode,make_instruction): Remove static
1341         declaration.
1342         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1343         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1344
1345 For older changes see ChangeLog-2012
1346 \f
1347 Copyright (C) 2013 Free Software Foundation, Inc.
1348
1349 Copying and distribution of this file, with or without modification,
1350 are permitted in any medium without royalty provided the copyright
1351 notice and this notice are preserved.
1352
1353 Local Variables:
1354 mode: change-log
1355 left-margin: 8
1356 fill-column: 74
1357 version-control: never
1358 End: