opcodes/ChangeLog

   1 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
   2
   3         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
   4         <vsx>: Do not use PPC_OPCODE_VSX3;
   5
   6 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
   7
   8         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
   9
  10 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
  11
  12         * i386-dis.c (REG_0F1E_MOD_3): New enum.
  13         (MOD_0F1E_PREFIX_1): Likewise.
  14         (MOD_0F38F5_PREFIX_2): Likewise.
  15         (MOD_0F38F6_PREFIX_0): Likewise.
  16         (RM_0F1E_MOD_3_REG_7): Likewise.
  17         (PREFIX_MOD_0_0F01_REG_5): Likewise.
  18         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  19         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
  20         (PREFIX_0F1E): Likewise.
  21         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
  22         (PREFIX_0F38F5): Likewise.
  23         (dis386_twobyte): Use PREFIX_0F1E.
  24         (reg_table): Add REG_0F1E_MOD_3.
  25         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
  26         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
  27         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
  28         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
  29         (three_byte_table): Use PREFIX_0F38F5.
  30         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
  31         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
  32         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
  33         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
  34         PREFIX_MOD_3_0F01_REG_5_RM_2.
  35         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
  36         (cpu_flags): Add CpuCET.
  37         * i386-opc.h (CpuCET): New enum.
  38         (CpuUnused): Commented out.
  39         (i386_cpu_flags): Add cpucet.
  40         * i386-opc.tbl: Add Intel CET instructions.
  41         * i386-init.h: Regenerated.
  42         * i386-tbl.h: Likewise.
  43
  44 2017-03-06  Alan Modra  <amodra@gmail.com>
  45
  46         PR 21124
  47         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
  48         (extract_raq, extract_ras, extract_rbx): New functions.
  49         (powerpc_operands): Use opposite corresponding insert function.
  50         (Q_MASK): Define.
  51         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
  52         register restriction.
  53
  54 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
  55
  56         * disassemble.c Include "safe-ctype.h".
  57         (disassemble_init_for_target): Handle s390 init.
  58         (remove_whitespace_and_extra_commas): New function.
  59         (disassembler_options_cmp): Likewise.
  60         * arm-dis.c: Include "libiberty.h".
  61         (NUM_ELEM): Delete.
  62         (regnames): Use long disassembler style names.
  63         Add force-thumb and no-force-thumb options.
  64         (NUM_ARM_REGNAMES): Rename from this...
  65         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
  66         (get_arm_regname_num_options): Delete.
  67         (set_arm_regname_option): Likewise.
  68         (get_arm_regnames): Likewise.
  69         (parse_disassembler_options): Likewise.
  70         (parse_arm_disassembler_option): Rename from this...
  71         (parse_arm_disassembler_options): ...to this.  Make static.
  72         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
  73         (print_insn): Use parse_arm_disassembler_options.
  74         (disassembler_options_arm): New function.
  75         (print_arm_disassembler_options): Handle updated regnames.
  76         * ppc-dis.c: Include "libiberty.h".
  77         (ppc_opts): Add "32" and "64" entries.
  78         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
  79         (powerpc_init_dialect): Add break to switch statement.
  80         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
  81         (disassembler_options_powerpc): New function.
  82         (print_ppc_disassembler_options): Use ARRAY_SIZE.
  83         Remove printing of "32" and "64".
  84         * s390-dis.c: Include "libiberty.h".
  85         (init_flag): Remove unneeded variable.
  86         (struct s390_options_t): New structure type.
  87         (options): New structure.
  88         (init_disasm): Rename from this...
  89         (disassemble_init_s390): ...to this.  Add initializations for
  90         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
  91         (print_insn_s390): Delete call to init_disasm.
  92         (disassembler_options_s390): New function.
  93         (print_s390_disassembler_options): Print using information from
  94         struct 'options'.
  95         * po/opcodes.pot: Regenerate.
  96
  97 2017-02-28  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-dis.c (PCMPESTR_Fixup): New.
 100         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 101         (prefix_table): Use PCMPESTR_Fixup.
 102         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 103         PCMPESTR_Fixup.
 104         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 105         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 106         Split 64-bit and non-64-bit variants.
 107         * opcodes/i386-tbl.h: Re-generate.
 108
 109 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 110
 111         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 112         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 113         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 114         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 115         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 116         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 117         (OP_SVE_V_HSD): New macros.
 118         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 119         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 120         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 121         (aarch64_opcode_table): Add new SVE instructions.
 122         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 123         for rotation operands.  Add new SVE operands.
 124         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 125         (ins_sve_quad_index): Likewise.
 126         (ins_imm_rotate): Split into...
 127         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 128         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 129         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 130         functions.
 131         (aarch64_ins_sve_addr_ri_s4): New function.
 132         (aarch64_ins_sve_quad_index): Likewise.
 133         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 134         * aarch64-asm-2.c: Regenerate.
 135         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 136         (ext_sve_quad_index): Likewise.
 137         (ext_imm_rotate): Split into...
 138         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 139         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 140         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 141         functions.
 142         (aarch64_ext_sve_addr_ri_s4): New function.
 143         (aarch64_ext_sve_quad_index): Likewise.
 144         (aarch64_ext_sve_index): Allow quad indices.
 145         (do_misc_decoding): Likewise.
 146         * aarch64-dis-2.c: Regenerate.
 147         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 148         aarch64_field_kinds.
 149         (OPD_F_OD_MASK): Widen by one bit.
 150         (OPD_F_NO_ZR): Bump accordingly.
 151         (get_operand_field_width): New function.
 152         * aarch64-opc.c (fields): Add new SVE fields.
 153         (operand_general_constraint_met_p): Handle new SVE operands.
 154         (aarch64_print_operand): Likewise.
 155         * aarch64-opc-2.c: Regenerate.
 156
 157 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 158
 159         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 160         (aarch64_feature_compnum): ...this.
 161         (SIMD_V8_3): Replace with...
 162         (COMPNUM): ...this.
 163         (CNUM_INSN): New macro.
 164         (aarch64_opcode_table): Use it for the complex number instructions.
 165
 166 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 169
 170 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 171
 172         Add support for associating SPARC ASIs with an architecture level.
 173         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 174         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 175         decoding of SPARC ASIs.
 176
 177 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 178
 179         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 180         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 181
 182 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 183
 184         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 185         1 (instead of to itself). Correct typo.
 186
 187 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 188
 189         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 190         pseudoinstructions.
 191
 192 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 193
 194         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 195         (aarch64_sys_reg_supported_p): Handle them.
 196
 197 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 198
 199         * arc-opc.c (UIMM6_20R): Define.
 200         (SIMM12_20): Use above.
 201         (SIMM12_20R): Define.
 202         (SIMM3_5_S): Use above.
 203         (UIMM7_A32_11R_S): Define.
 204         (UIMM7_9_S): Use above.
 205         (UIMM3_13R_S): Define.
 206         (SIMM11_A32_7_S): Use above.
 207         (SIMM9_8R): Define.
 208         (UIMM10_A32_8_S): Use above.
 209         (UIMM8_8R_S): Define.
 210         (W6): Use above.
 211         (arc_relax_opcodes): Use all above defines.
 212
 213 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 214
 215         * arc-regs.h: Distinguish some of the registers different on
 216         ARC700 and HS38 cpus.
 217
 218 2017-02-14  Alan Modra  <amodra@gmail.com>
 219
 220         PR 21118
 221         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 222         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 223
 224 2017-02-11  Stafford Horne  <shorne@gmail.com>
 225             Alan Modra  <amodra@gmail.com>
 226
 227         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 228         Use insn_bytes_value and insn_int_value directly instead.  Don't
 229         free allocated memory until function exit.
 230
 231 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 232
 233         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 234
 235 2017-02-03  Nick Clifton  <nickc@redhat.com>
 236
 237         PR 21096
 238         * aarch64-opc.c (print_register_list): Ensure that the register
 239         list index will fir into the tb buffer.
 240         (print_register_offset_address): Likewise.
 241         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 242
 243 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 244
 245         PR 21056
 246         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 247         instructions when the previous fetch packet ends with a 32-bit
 248         instruction.
 249
 250 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 251
 252         * pru-opc.c: Remove vague reference to a future GDB port.
 253
 254 2017-01-20  Nick Clifton  <nickc@redhat.com>
 255
 256         * po/ga.po: Updated Irish translation.
 257
 258 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 259
 260         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 261
 262 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 263
 264         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 265         if FETCH_DATA returns 0.
 266         (m68k_scan_mask): Likewise.
 267         (print_insn_m68k): Update code to handle -1 return value.
 268
 269 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 270
 271         * m68k-dis.c (enum print_insn_arg_error): New.
 272         (NEXTBYTE): Replace -3 with
 273         PRINT_INSN_ARG_MEMORY_ERROR.
 274         (NEXTULONG): Likewise.
 275         (NEXTSINGLE): Likewise.
 276         (NEXTDOUBLE): Likewise.
 277         (NEXTDOUBLE): Likewise.
 278         (NEXTPACKED): Likewise.
 279         (FETCH_ARG): Likewise.
 280         (FETCH_DATA): Update comments.
 281         (print_insn_arg): Update comments. Replace magic numbers with
 282         enum.
 283         (match_insn_m68k): Likewise.
 284
 285 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 286
 287         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 288         * i386-dis-evex.h (evex_table): Updated.
 289         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 290         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 291         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 292         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 293         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 294         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 295         * i386-init.h: Regenerate.
 296         * i386-tbl.h: Ditto.
 297
 298 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 299
 300         * msp430-dis.c (msp430_singleoperand): Return -1 if
 301         msp430dis_opcode_signed returns false.
 302         (msp430_doubleoperand): Likewise.
 303         (msp430_branchinstr): Return -1 if
 304         msp430dis_opcode_unsigned returns false.
 305         (msp430x_calla_instr): Likewise.
 306         (print_insn_msp430): Likewise.
 307
 308 2017-01-05  Nick Clifton  <nickc@redhat.com>
 309
 310         PR 20946
 311         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 312         could not be matched.
 313         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 314         NULL.
 315
 316 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 317
 318         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 319         (aarch64_opcode_table): Use RCPC_INSN.
 320
 321 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 322
 323         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 324         extension.
 325         * riscv-opcodes/all-opcodes: Likewise.
 326
 327 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 328
 329         * riscv-dis.c (print_insn_args): Add fall through comment.
 330
 331 2017-01-03  Nick Clifton  <nickc@redhat.com>
 332
 333         * po/sr.po: New Serbian translation.
 334         * configure.ac (ALL_LINGUAS): Add sr.
 335         * configure: Regenerate.
 336
 337 2017-01-02  Alan Modra  <amodra@gmail.com>
 338
 339         * epiphany-desc.h: Regenerate.
 340         * epiphany-opc.h: Regenerate.
 341         * fr30-desc.h: Regenerate.
 342         * fr30-opc.h: Regenerate.
 343         * frv-desc.h: Regenerate.
 344         * frv-opc.h: Regenerate.
 345         * ip2k-desc.h: Regenerate.
 346         * ip2k-opc.h: Regenerate.
 347         * iq2000-desc.h: Regenerate.
 348         * iq2000-opc.h: Regenerate.
 349         * lm32-desc.h: Regenerate.
 350         * lm32-opc.h: Regenerate.
 351         * m32c-desc.h: Regenerate.
 352         * m32c-opc.h: Regenerate.
 353         * m32r-desc.h: Regenerate.
 354         * m32r-opc.h: Regenerate.
 355         * mep-desc.h: Regenerate.
 356         * mep-opc.h: Regenerate.
 357         * mt-desc.h: Regenerate.
 358         * mt-opc.h: Regenerate.
 359         * or1k-desc.h: Regenerate.
 360         * or1k-opc.h: Regenerate.
 361         * xc16x-desc.h: Regenerate.
 362         * xc16x-opc.h: Regenerate.
 363         * xstormy16-desc.h: Regenerate.
 364         * xstormy16-opc.h: Regenerate.
 365
 366 2017-01-02  Alan Modra  <amodra@gmail.com>
 367
 368         Update year range in copyright notice of all files.
 369
 370 For older changes see ChangeLog-2016
 371 \f
 372 Copyright (C) 2017 Free Software Foundation, Inc.
 373
 374 Copying and distribution of this file, with or without modification,
 375 are permitted in any medium without royalty provided the copyright
 376 notice and this notice are preserved.
 377
 378 Local Variables:
 379 mode: change-log
 380 left-margin: 8
 381 fill-column: 74
 382 version-control: never
 383 End: