opcodes/ChangeLog

   1 2017-03-17  Alan Modra  <amodra@gmail.com>
   2
   3         PR 21248
   4         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
   5         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
   6         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
   7
   8 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
   9
  10         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
  11         <c.andi>: Likewise.
  12         <c.addiw> Likewise.
  13
  14 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
  15
  16         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
  17
  18 2017-03-13  Andrew Waterman  <andrew@sifive.com>
  19
  20         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
  21         <srl> Likewise.
  22         <srai> Likewise.
  23         <sra> Likewise.
  24
  25 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  26
  27         * i386-gen.c (opcode_modifiers): Replace S with Load.
  28         * i386-opc.h (S): Removed.
  29         (Load): New.
  30         (i386_opcode_modifier): Replace s with load.
  31         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
  32         and {evex}.  Replace S with Load.
  33         * i386-tbl.h: Regenerated.
  34
  35 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  36
  37         * i386-opc.tbl: Use CpuCET on rdsspq.
  38         * i386-tbl.h: Regenerated.
  39
  40 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
  41
  42         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
  43         <vsx>: Do not use PPC_OPCODE_VSX3;
  44
  45 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
  46
  47         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
  48
  49 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
  50
  51         * i386-dis.c (REG_0F1E_MOD_3): New enum.
  52         (MOD_0F1E_PREFIX_1): Likewise.
  53         (MOD_0F38F5_PREFIX_2): Likewise.
  54         (MOD_0F38F6_PREFIX_0): Likewise.
  55         (RM_0F1E_MOD_3_REG_7): Likewise.
  56         (PREFIX_MOD_0_0F01_REG_5): Likewise.
  57         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  58         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
  59         (PREFIX_0F1E): Likewise.
  60         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
  61         (PREFIX_0F38F5): Likewise.
  62         (dis386_twobyte): Use PREFIX_0F1E.
  63         (reg_table): Add REG_0F1E_MOD_3.
  64         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
  65         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
  66         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
  67         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
  68         (three_byte_table): Use PREFIX_0F38F5.
  69         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
  70         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
  71         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
  72         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
  73         PREFIX_MOD_3_0F01_REG_5_RM_2.
  74         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
  75         (cpu_flags): Add CpuCET.
  76         * i386-opc.h (CpuCET): New enum.
  77         (CpuUnused): Commented out.
  78         (i386_cpu_flags): Add cpucet.
  79         * i386-opc.tbl: Add Intel CET instructions.
  80         * i386-init.h: Regenerated.
  81         * i386-tbl.h: Likewise.
  82
  83 2017-03-06  Alan Modra  <amodra@gmail.com>
  84
  85         PR 21124
  86         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
  87         (extract_raq, extract_ras, extract_rbx): New functions.
  88         (powerpc_operands): Use opposite corresponding insert function.
  89         (Q_MASK): Define.
  90         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
  91         register restriction.
  92
  93 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
  94
  95         * disassemble.c Include "safe-ctype.h".
  96         (disassemble_init_for_target): Handle s390 init.
  97         (remove_whitespace_and_extra_commas): New function.
  98         (disassembler_options_cmp): Likewise.
  99         * arm-dis.c: Include "libiberty.h".
 100         (NUM_ELEM): Delete.
 101         (regnames): Use long disassembler style names.
 102         Add force-thumb and no-force-thumb options.
 103         (NUM_ARM_REGNAMES): Rename from this...
 104         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 105         (get_arm_regname_num_options): Delete.
 106         (set_arm_regname_option): Likewise.
 107         (get_arm_regnames): Likewise.
 108         (parse_disassembler_options): Likewise.
 109         (parse_arm_disassembler_option): Rename from this...
 110         (parse_arm_disassembler_options): ...to this.  Make static.
 111         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 112         (print_insn): Use parse_arm_disassembler_options.
 113         (disassembler_options_arm): New function.
 114         (print_arm_disassembler_options): Handle updated regnames.
 115         * ppc-dis.c: Include "libiberty.h".
 116         (ppc_opts): Add "32" and "64" entries.
 117         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 118         (powerpc_init_dialect): Add break to switch statement.
 119         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 120         (disassembler_options_powerpc): New function.
 121         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 122         Remove printing of "32" and "64".
 123         * s390-dis.c: Include "libiberty.h".
 124         (init_flag): Remove unneeded variable.
 125         (struct s390_options_t): New structure type.
 126         (options): New structure.
 127         (init_disasm): Rename from this...
 128         (disassemble_init_s390): ...to this.  Add initializations for
 129         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 130         (print_insn_s390): Delete call to init_disasm.
 131         (disassembler_options_s390): New function.
 132         (print_s390_disassembler_options): Print using information from
 133         struct 'options'.
 134         * po/opcodes.pot: Regenerate.
 135
 136 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 137
 138         * i386-dis.c (PCMPESTR_Fixup): New.
 139         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 140         (prefix_table): Use PCMPESTR_Fixup.
 141         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 142         PCMPESTR_Fixup.
 143         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 144         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 145         Split 64-bit and non-64-bit variants.
 146         * opcodes/i386-tbl.h: Re-generate.
 147
 148 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 149
 150         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 151         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 152         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 153         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 154         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 155         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 156         (OP_SVE_V_HSD): New macros.
 157         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 158         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 159         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 160         (aarch64_opcode_table): Add new SVE instructions.
 161         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 162         for rotation operands.  Add new SVE operands.
 163         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 164         (ins_sve_quad_index): Likewise.
 165         (ins_imm_rotate): Split into...
 166         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 167         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 168         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 169         functions.
 170         (aarch64_ins_sve_addr_ri_s4): New function.
 171         (aarch64_ins_sve_quad_index): Likewise.
 172         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 173         * aarch64-asm-2.c: Regenerate.
 174         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 175         (ext_sve_quad_index): Likewise.
 176         (ext_imm_rotate): Split into...
 177         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 178         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 179         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 180         functions.
 181         (aarch64_ext_sve_addr_ri_s4): New function.
 182         (aarch64_ext_sve_quad_index): Likewise.
 183         (aarch64_ext_sve_index): Allow quad indices.
 184         (do_misc_decoding): Likewise.
 185         * aarch64-dis-2.c: Regenerate.
 186         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 187         aarch64_field_kinds.
 188         (OPD_F_OD_MASK): Widen by one bit.
 189         (OPD_F_NO_ZR): Bump accordingly.
 190         (get_operand_field_width): New function.
 191         * aarch64-opc.c (fields): Add new SVE fields.
 192         (operand_general_constraint_met_p): Handle new SVE operands.
 193         (aarch64_print_operand): Likewise.
 194         * aarch64-opc-2.c: Regenerate.
 195
 196 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 197
 198         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 199         (aarch64_feature_compnum): ...this.
 200         (SIMD_V8_3): Replace with...
 201         (COMPNUM): ...this.
 202         (CNUM_INSN): New macro.
 203         (aarch64_opcode_table): Use it for the complex number instructions.
 204
 205 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 208
 209 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 210
 211         Add support for associating SPARC ASIs with an architecture level.
 212         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 213         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 214         decoding of SPARC ASIs.
 215
 216 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 219         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 220
 221 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 222
 223         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 224         1 (instead of to itself). Correct typo.
 225
 226 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 227
 228         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 229         pseudoinstructions.
 230
 231 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 232
 233         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 234         (aarch64_sys_reg_supported_p): Handle them.
 235
 236 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 237
 238         * arc-opc.c (UIMM6_20R): Define.
 239         (SIMM12_20): Use above.
 240         (SIMM12_20R): Define.
 241         (SIMM3_5_S): Use above.
 242         (UIMM7_A32_11R_S): Define.
 243         (UIMM7_9_S): Use above.
 244         (UIMM3_13R_S): Define.
 245         (SIMM11_A32_7_S): Use above.
 246         (SIMM9_8R): Define.
 247         (UIMM10_A32_8_S): Use above.
 248         (UIMM8_8R_S): Define.
 249         (W6): Use above.
 250         (arc_relax_opcodes): Use all above defines.
 251
 252 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 253
 254         * arc-regs.h: Distinguish some of the registers different on
 255         ARC700 and HS38 cpus.
 256
 257 2017-02-14  Alan Modra  <amodra@gmail.com>
 258
 259         PR 21118
 260         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 261         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 262
 263 2017-02-11  Stafford Horne  <shorne@gmail.com>
 264             Alan Modra  <amodra@gmail.com>
 265
 266         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 267         Use insn_bytes_value and insn_int_value directly instead.  Don't
 268         free allocated memory until function exit.
 269
 270 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 271
 272         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 273
 274 2017-02-03  Nick Clifton  <nickc@redhat.com>
 275
 276         PR 21096
 277         * aarch64-opc.c (print_register_list): Ensure that the register
 278         list index will fir into the tb buffer.
 279         (print_register_offset_address): Likewise.
 280         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 281
 282 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 283
 284         PR 21056
 285         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 286         instructions when the previous fetch packet ends with a 32-bit
 287         instruction.
 288
 289 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 290
 291         * pru-opc.c: Remove vague reference to a future GDB port.
 292
 293 2017-01-20  Nick Clifton  <nickc@redhat.com>
 294
 295         * po/ga.po: Updated Irish translation.
 296
 297 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 298
 299         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 300
 301 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 302
 303         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 304         if FETCH_DATA returns 0.
 305         (m68k_scan_mask): Likewise.
 306         (print_insn_m68k): Update code to handle -1 return value.
 307
 308 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 309
 310         * m68k-dis.c (enum print_insn_arg_error): New.
 311         (NEXTBYTE): Replace -3 with
 312         PRINT_INSN_ARG_MEMORY_ERROR.
 313         (NEXTULONG): Likewise.
 314         (NEXTSINGLE): Likewise.
 315         (NEXTDOUBLE): Likewise.
 316         (NEXTDOUBLE): Likewise.
 317         (NEXTPACKED): Likewise.
 318         (FETCH_ARG): Likewise.
 319         (FETCH_DATA): Update comments.
 320         (print_insn_arg): Update comments. Replace magic numbers with
 321         enum.
 322         (match_insn_m68k): Likewise.
 323
 324 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 325
 326         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 327         * i386-dis-evex.h (evex_table): Updated.
 328         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 329         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 330         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 331         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 332         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 333         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 334         * i386-init.h: Regenerate.
 335         * i386-tbl.h: Ditto.
 336
 337 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 338
 339         * msp430-dis.c (msp430_singleoperand): Return -1 if
 340         msp430dis_opcode_signed returns false.
 341         (msp430_doubleoperand): Likewise.
 342         (msp430_branchinstr): Return -1 if
 343         msp430dis_opcode_unsigned returns false.
 344         (msp430x_calla_instr): Likewise.
 345         (print_insn_msp430): Likewise.
 346
 347 2017-01-05  Nick Clifton  <nickc@redhat.com>
 348
 349         PR 20946
 350         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 351         could not be matched.
 352         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 353         NULL.
 354
 355 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 356
 357         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 358         (aarch64_opcode_table): Use RCPC_INSN.
 359
 360 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 361
 362         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 363         extension.
 364         * riscv-opcodes/all-opcodes: Likewise.
 365
 366 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 367
 368         * riscv-dis.c (print_insn_args): Add fall through comment.
 369
 370 2017-01-03  Nick Clifton  <nickc@redhat.com>
 371
 372         * po/sr.po: New Serbian translation.
 373         * configure.ac (ALL_LINGUAS): Add sr.
 374         * configure: Regenerate.
 375
 376 2017-01-02  Alan Modra  <amodra@gmail.com>
 377
 378         * epiphany-desc.h: Regenerate.
 379         * epiphany-opc.h: Regenerate.
 380         * fr30-desc.h: Regenerate.
 381         * fr30-opc.h: Regenerate.
 382         * frv-desc.h: Regenerate.
 383         * frv-opc.h: Regenerate.
 384         * ip2k-desc.h: Regenerate.
 385         * ip2k-opc.h: Regenerate.
 386         * iq2000-desc.h: Regenerate.
 387         * iq2000-opc.h: Regenerate.
 388         * lm32-desc.h: Regenerate.
 389         * lm32-opc.h: Regenerate.
 390         * m32c-desc.h: Regenerate.
 391         * m32c-opc.h: Regenerate.
 392         * m32r-desc.h: Regenerate.
 393         * m32r-opc.h: Regenerate.
 394         * mep-desc.h: Regenerate.
 395         * mep-opc.h: Regenerate.
 396         * mt-desc.h: Regenerate.
 397         * mt-opc.h: Regenerate.
 398         * or1k-desc.h: Regenerate.
 399         * or1k-opc.h: Regenerate.
 400         * xc16x-desc.h: Regenerate.
 401         * xc16x-opc.h: Regenerate.
 402         * xstormy16-desc.h: Regenerate.
 403         * xstormy16-opc.h: Regenerate.
 404
 405 2017-01-02  Alan Modra  <amodra@gmail.com>
 406
 407         Update year range in copyright notice of all files.
 408
 409 For older changes see ChangeLog-2016
 410 \f
 411 Copyright (C) 2017 Free Software Foundation, Inc.
 412
 413 Copying and distribution of this file, with or without modification,
 414 are permitted in any medium without royalty provided the copyright
 415 notice and this notice are preserved.
 416
 417 Local Variables:
 418 mode: change-log
 419 left-margin: 8
 420 fill-column: 74
 421 version-control: never
 422 End: