1 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
3 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
4 `bfd_mips_elf_get_abiflags' here.
6 2016-12-16 Nick Clifton <nickc@redhat.com>
8 * arm-dis.c (print_insn_thumb32): Fix compile time warning
9 computing value_in_comment.
11 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
13 * mips-dis.c (mips_convert_abiflags_ases): New function.
14 (set_default_mips_dis_options): Also infer ASE flags from ELF
17 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
19 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
20 header flag interpretation code.
22 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
24 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
25 `pinfo2' with SP-relative "sd" entries.
27 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
29 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
32 2016-12-13 Renlin Li <renlin.li@arm.com>
34 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
36 (operand_general_constraint_met_p): Remove case for CP_REG.
37 (aarch64_print_operand): Print CRn, CRm operand using imm field.
38 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
40 (aarch64_opcode_table): Change CRn, CRm operand class and type.
41 * aarch64-opc-2.c : Regenerate.
42 * aarch64-asm-2.c : Likewise.
43 * aarch64-dis-2.c : Likewise.
45 2016-12-12 Yao Qi <yao.qi@linaro.org>
47 * rx-dis.c: Include <setjmp.h>
48 (struct private): New.
49 (rx_get_byte): Check return value of read_memory_func, and
50 call memory_error_func and OPCODES_SIGLONGJMP on error.
51 (print_insn_rx): Call OPCODES_SIGSETJMP.
53 2016-12-12 Yao Qi <yao.qi@linaro.org>
55 * rl78-dis.c: Include <setjmp.h>.
56 (struct private): New.
57 (rl78_get_byte): Check return value of read_memory_func, and
58 call memory_error_func and OPCODES_SIGLONGJMP on error.
59 (print_insn_rl78_common): Call OPCODES_SIGJMP.
61 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
63 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
65 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
67 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
70 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
72 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
73 to separate `extend' and its uninterpreted argument output.
74 Separate hexadecimal halves of undecoded extended instructions
77 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
79 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
80 indentation space across.
82 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
84 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
85 adjustment for PC-relative operations following MIPS16e compact
86 jumps or undefined RR/J(AL)R(C) encodings.
88 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
90 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
91 variable to `reglane_index'.
93 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
95 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
97 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
99 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
101 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
103 * mips16-opc.c (mips16_opcodes): Update comment naming structure
106 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
108 * mips-dis.c (print_mips_disassembler_options): Reformat output.
110 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
112 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
113 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
115 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
117 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
119 2016-12-01 Nick Clifton <nickc@redhat.com>
122 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
125 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
127 * arc-opc.c (insert_ra_chk): New function.
128 (insert_rb_chk): Likewise.
129 (insert_rad): Update text error message.
130 (insert_rcd): Likewise.
131 (insert_rhv2): Likewise.
132 (insert_r0): Likewise.
133 (insert_r1): Likewise.
134 (insert_r2): Likewise.
135 (insert_r3): Likewise.
136 (insert_sp): Likewise.
137 (insert_gp): Likewise.
138 (insert_pcl): Likewise.
139 (insert_blink): Likewise.
140 (insert_ilink1): Likewise.
141 (insert_ilink2): Likewise.
142 (insert_ras): Likewise.
143 (insert_rbs): Likewise.
144 (insert_rcs): Likewise.
145 (insert_simm3s): Likewise.
146 (insert_rrange): Likewise.
147 (insert_fpel): Likewise.
148 (insert_blinkel): Likewise.
149 (insert_pcel): Likewise.
150 (insert_nps_3bit_dst): Likewise.
151 (insert_nps_3bit_dst_short): Likewise.
152 (insert_nps_3bit_src2_short): Likewise.
153 (insert_nps_bitop_size_2b): Likewise.
154 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
159 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
160 * arc-tbl.h (div, divu): All instructions are DIVREM class.
161 Change first insn argument to check for LP_COUNT usage.
163 (ld, ldd): All instructions are LOAD class. Change first insn
164 argument to check for LP_COUNT usage.
165 (st, std): All instructions are STORE class.
166 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
167 Change first insn argument to check for LP_COUNT usage.
168 (mov): All instructions are MOVE class. Change first insn
169 argument to check for LP_COUNT usage.
171 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
173 * arc-dis.c (is_compatible_p): Remove function.
174 (skip_this_opcode): Don't add any decoding class to decode list.
176 (find_format_from_table): Go through all opcodes, and warn if we
177 use a guessed mnemonic.
179 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
180 Amit Pawar <amit.pawar@amd.com>
183 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
186 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
188 * configure: Regenerate.
190 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
192 * sparc-opc.c (HWS_V8): Definition moved from
193 gas/config/tc-sparc.c.
203 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
206 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
208 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
211 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
213 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
214 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
215 (aarch64_opcode_table): Add fcmla and fcadd.
216 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
217 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
218 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
219 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
220 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
221 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
222 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
223 (operand_general_constraint_met_p): Rotate and index range check.
224 (aarch64_print_operand): Handle rotate operand.
225 * aarch64-asm-2.c: Regenerate.
226 * aarch64-dis-2.c: Likewise.
227 * aarch64-opc-2.c: Likewise.
229 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
231 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
232 * aarch64-asm-2.c: Regenerate.
233 * aarch64-dis-2.c: Regenerate.
234 * aarch64-opc-2.c: Regenerate.
236 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
238 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
239 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
240 * aarch64-asm-2.c: Regenerate.
241 * aarch64-dis-2.c: Regenerate.
242 * aarch64-opc-2.c: Regenerate.
244 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
246 * aarch64-tbl.h (QL_X1NIL): New.
247 (arch64_opcode_table): Add ldraa, ldrab.
248 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
249 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
250 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
251 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
252 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
253 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
254 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
255 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
256 (aarch64_print_operand): Likewise.
257 * aarch64-asm-2.c: Regenerate.
258 * aarch64-dis-2.c: Regenerate.
259 * aarch64-opc-2.c: Regenerate.
261 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
263 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
264 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
265 * aarch64-asm-2.c: Regenerate.
266 * aarch64-dis-2.c: Regenerate.
267 * aarch64-opc-2.c: Regenerate.
269 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
271 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
272 (AARCH64_OPERANDS): Add Rm_SP.
273 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
274 * aarch64-asm-2.c: Regenerate.
275 * aarch64-dis-2.c: Regenerate.
276 * aarch64-opc-2.c: Regenerate.
278 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
280 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
281 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
282 autdzb, xpaci, xpacd.
283 * aarch64-asm-2.c: Regenerate.
284 * aarch64-dis-2.c: Regenerate.
285 * aarch64-opc-2.c: Regenerate.
287 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
289 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
290 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
291 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
292 (aarch64_sys_reg_supported_p): Add feature test for new registers.
294 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
296 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
297 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
298 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
300 * aarch64-asm-2.c: Regenerate.
301 * aarch64-dis-2.c: Regenerate.
303 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
305 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
307 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
310 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
311 * i386-dis.c (EdqwS): Removed.
312 (dqw_swap_mode): Likewise.
313 (intel_operand_size): Don't check dqw_swap_mode.
314 (OP_E_register): Likewise.
315 (OP_E_memory): Likewise.
318 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
319 * i386-tbl.h: Regerated.
321 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
323 * i386-opc.tbl: Merge AVX512F vmovq.
324 * i386-tbl.h: Regerated.
326 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
329 * i386-dis.c (THREE_BYTE_0F7A): Removed.
330 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
331 (three_byte_table): Remove THREE_BYTE_0F7A.
333 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
336 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
337 (FGRPd9_4): Replace 1 with 2.
338 (FGRPd9_5): Replace 2 with 3.
339 (FGRPd9_6): Replace 3 with 4.
340 (FGRPd9_7): Replace 4 with 5.
341 (FGRPda_5): Replace 5 with 6.
342 (FGRPdb_4): Replace 6 with 7.
343 (FGRPde_3): Replace 7 with 8.
344 (FGRPdf_4): Replace 8 with 9.
345 (fgrps): Add an entry for Bad_Opcode.
347 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
349 * arc-opc.c (arc_flag_operands): Add F_DI14.
350 (arc_flag_classes): Add C_DI14.
351 * arc-nps400-tbl.h: Add new exc instructions.
353 2016-11-03 Graham Markall <graham.markall@embecosm.com>
355 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
357 * arc-nps-400-tbl.h: Add dcmac instruction.
358 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
359 (insert_nps_rbdouble_64): Added.
360 (extract_nps_rbdouble_64): Added.
361 (insert_nps_proto_size): Added.
362 (extract_nps_proto_size): Added.
364 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
366 * arc-dis.c (struct arc_operand_iterator): Remove all fields
367 relating to long instruction processing, add new limm field.
368 (OPCODE): Rename to...
369 (OPCODE_32BIT_INSN): ...this.
371 (skip_this_opcode): Handle different instruction lengths, update
373 (special_flag_p): Update parameter type.
374 (find_format_from_table): Update for more instruction lengths.
375 (find_format_long_instructions): Delete.
376 (find_format): Update for more instruction lengths.
377 (arc_insn_length): Likewise.
378 (extract_operand_value): Update for more instruction lengths.
379 (operand_iterator_next): Remove code relating to long
381 (arc_opcode_to_insn_type): New function.
382 (print_insn_arc):Update for more instructions lengths.
383 * arc-ext.c (extInstruction_t): Change argument type.
384 * arc-ext.h (extInstruction_t): Change argument type.
385 * arc-fxi.h: Change type unsigned to unsigned long long
386 extensively throughout.
387 * arc-nps400-tbl.h: Add long instructions taken from
388 arc_long_opcodes table in arc-opc.c.
389 * arc-opc.c: Update parameter types on insert/extract handlers.
390 (arc_long_opcodes): Delete.
391 (arc_num_long_opcodes): Delete.
392 (arc_opcode_len): Update for more instruction lengths.
394 2016-11-03 Graham Markall <graham.markall@embecosm.com>
396 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
398 2016-11-03 Graham Markall <graham.markall@embecosm.com>
400 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
402 (find_format_long_instructions): Likewise.
403 * arc-opc.c (arc_opcode_len): New function.
405 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
407 * arc-nps400-tbl.h: Fix some instruction masks.
409 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
411 * i386-dis.c (REG_82): Removed.
412 (X86_64_82_REG_0): Likewise.
413 (X86_64_82_REG_1): Likewise.
414 (X86_64_82_REG_2): Likewise.
415 (X86_64_82_REG_3): Likewise.
416 (X86_64_82_REG_4): Likewise.
417 (X86_64_82_REG_5): Likewise.
418 (X86_64_82_REG_6): Likewise.
419 (X86_64_82_REG_7): Likewise.
421 (dis386): Use X86_64_82 instead of REG_82.
422 (reg_table): Remove REG_82.
423 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
424 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
425 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
428 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
431 * i386-dis.c (REG_82): New.
432 (X86_64_82_REG_0): Likewise.
433 (X86_64_82_REG_1): Likewise.
434 (X86_64_82_REG_2): Likewise.
435 (X86_64_82_REG_3): Likewise.
436 (X86_64_82_REG_4): Likewise.
437 (X86_64_82_REG_5): Likewise.
438 (X86_64_82_REG_6): Likewise.
439 (X86_64_82_REG_7): Likewise.
440 (dis386): Use REG_82.
441 (reg_table): Add REG_82.
442 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
443 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
444 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
446 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
448 * i386-dis.c (REG_82): Renamed to ...
451 (reg_table): Likewise.
453 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
455 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
456 * i386-dis-evex.h (evex_table): Updated.
457 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
458 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
459 (cpu_flags): Add CpuAVX512_4VNNIW.
460 * i386-opc.h (enum): (AVX512_4VNNIW): New.
461 (i386_cpu_flags): Add cpuavx512_4vnniw.
462 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
463 * i386-init.h: Regenerate.
466 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
468 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
469 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
470 * i386-dis-evex.h (evex_table): Updated.
471 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
472 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
473 (cpu_flags): Add CpuAVX512_4FMAPS.
474 (opcode_modifiers): Add ImplicitQuadGroup modifier.
475 * i386-opc.h (AVX512_4FMAP): New.
476 (i386_cpu_flags): Add cpuavx512_4fmaps.
477 (ImplicitQuadGroup): New.
478 (i386_opcode_modifier): Add implicitquadgroup.
479 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
480 * i386-init.h: Regenerate.
483 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
484 Andrew Waterman <andrew@sifive.com>
486 Add support for RISC-V architecture.
487 * configure.ac: Add entry for bfd_riscv_arch.
488 * configure: Regenerate.
489 * disassemble.c (disassembler): Add support for riscv.
490 (disassembler_usage): Likewise.
491 * riscv-dis.c: New file.
492 * riscv-opc.c: New file.
494 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
496 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
497 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
498 (rm_table): Update the RM_0FAE_REG_7 entry.
499 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
500 (cpu_flags): Remove CpuPCOMMIT.
501 * i386-opc.h (CpuPCOMMIT): Removed.
502 (i386_cpu_flags): Remove cpupcommit.
503 * i386-opc.tbl: Remove pcommit.
504 * i386-init.h: Regenerated.
505 * i386-tbl.h: Likewise.
507 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
510 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
511 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
512 32-bit mode. Don't check vex.register_specifier in 32-bit
514 (OP_VEX): Check for invalid mask registers.
516 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
519 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
522 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
525 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
527 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
529 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
530 local variable to `index_regno'.
532 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
534 * arc-tbl.h: Removed any "inv.+" instructions from the table.
536 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
538 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
541 2016-10-11 Jiong Wang <jiong.wang@arm.com>
544 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
546 2016-10-07 Jiong Wang <jiong.wang@arm.com>
549 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
552 2016-10-07 Alan Modra <amodra@gmail.com>
554 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
556 2016-10-06 Alan Modra <amodra@gmail.com>
558 * aarch64-opc.c: Spell fall through comments consistently.
559 * i386-dis.c: Likewise.
560 * aarch64-dis.c: Add missing fall through comments.
561 * aarch64-opc.c: Likewise.
562 * arc-dis.c: Likewise.
563 * arm-dis.c: Likewise.
564 * i386-dis.c: Likewise.
565 * m68k-dis.c: Likewise.
566 * mep-asm.c: Likewise.
567 * ns32k-dis.c: Likewise.
568 * sh-dis.c: Likewise.
569 * tic4x-dis.c: Likewise.
570 * tic6x-dis.c: Likewise.
571 * vax-dis.c: Likewise.
573 2016-10-06 Alan Modra <amodra@gmail.com>
575 * arc-ext.c (create_map): Add missing break.
576 * msp430-decode.opc (encode_as): Likewise.
577 * msp430-decode.c: Regenerate.
579 2016-10-06 Alan Modra <amodra@gmail.com>
581 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
582 * crx-dis.c (print_insn_crx): Likewise.
584 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
587 * i386-dis.c (putop): Don't assign alt twice.
589 2016-09-29 Jiong Wang <jiong.wang@arm.com>
592 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
594 2016-09-29 Alan Modra <amodra@gmail.com>
596 * ppc-opc.c (L): Make compulsory.
597 (LOPT): New, optional form of L.
598 (HTM_R): Define as LOPT.
600 (L32OPT): New, optional for 32-bit L.
601 (L2OPT): New, 2-bit L for dcbf.
604 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
605 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
607 <tlbiel, tlbie>: Use LOPT.
608 <wclr, wclrall>: Use L2.
610 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
612 * Makefile.in: Regenerate.
613 * configure: Likewise.
615 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
617 * arc-ext-tbl.h (EXTINSN2OPF): Define.
618 (EXTINSN2OP): Use EXTINSN2OPF.
619 (bspeekm, bspop, modapp): New extension instructions.
620 * arc-opc.c (F_DNZ_ND): Define.
625 * arc-tbl.h (dbnz): New instruction.
626 (prealloc): Allow it for ARC EM.
629 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
631 * aarch64-opc.c (print_immediate_offset_address): Print spaces
632 after commas in addresses.
633 (aarch64_print_operand): Likewise.
635 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
637 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
638 rather than "should be" or "expected to be" in error messages.
640 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
642 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
643 (print_mnemonic_name): ...here.
644 (print_comment): New function.
645 (print_aarch64_insn): Call it.
646 * aarch64-opc.c (aarch64_conds): Add SVE names.
647 (aarch64_print_operand): Print alternative condition names in
650 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
652 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
653 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
654 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
655 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
656 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
657 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
658 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
659 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
660 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
661 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
662 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
663 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
664 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
665 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
666 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
667 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
668 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
669 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
670 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
671 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
672 (OP_SVE_XWU, OP_SVE_XXU): New macros.
673 (aarch64_feature_sve): New variable.
675 (_SVE_INSN): Likewise.
676 (aarch64_opcode_table): Add SVE instructions.
677 * aarch64-opc.h (extract_fields): Declare.
678 * aarch64-opc-2.c: Regenerate.
679 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
680 * aarch64-asm-2.c: Regenerate.
681 * aarch64-dis.c (extract_fields): Make global.
682 (do_misc_decoding): Handle the new SVE aarch64_ops.
683 * aarch64-dis-2.c: Regenerate.
685 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
687 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
688 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
690 * aarch64-opc.c (fields): Add corresponding entries.
691 * aarch64-asm.c (aarch64_get_variant): New function.
692 (aarch64_encode_variant_using_iclass): Likewise.
693 (aarch64_opcode_encode): Call it.
694 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
695 (aarch64_opcode_decode): Call it.
697 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
699 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
700 and FP register operands.
701 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
702 (FLD_SVE_Vn): New aarch64_field_kinds.
703 * aarch64-opc.c (fields): Add corresponding entries.
704 (aarch64_print_operand): Handle the new SVE core and FP register
706 * aarch64-opc-2.c: Regenerate.
707 * aarch64-asm-2.c: Likewise.
708 * aarch64-dis-2.c: Likewise.
710 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
712 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
714 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
715 * aarch64-opc.c (fields): Add corresponding entry.
716 (operand_general_constraint_met_p): Handle the new SVE FP immediate
718 (aarch64_print_operand): Likewise.
719 * aarch64-opc-2.c: Regenerate.
720 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
721 (ins_sve_float_zero_one): New inserters.
722 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
723 (aarch64_ins_sve_float_half_two): Likewise.
724 (aarch64_ins_sve_float_zero_one): Likewise.
725 * aarch64-asm-2.c: Regenerate.
726 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
727 (ext_sve_float_zero_one): New extractors.
728 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
729 (aarch64_ext_sve_float_half_two): Likewise.
730 (aarch64_ext_sve_float_zero_one): Likewise.
731 * aarch64-dis-2.c: Regenerate.
733 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
735 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
736 integer immediate operands.
737 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
738 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
739 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
740 * aarch64-opc.c (fields): Add corresponding entries.
741 (operand_general_constraint_met_p): Handle the new SVE integer
743 (aarch64_print_operand): Likewise.
744 (aarch64_sve_dupm_mov_immediate_p): New function.
745 * aarch64-opc-2.c: Regenerate.
746 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
747 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
748 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
749 (aarch64_ins_limm): ...here.
750 (aarch64_ins_inv_limm): New function.
751 (aarch64_ins_sve_aimm): Likewise.
752 (aarch64_ins_sve_asimm): Likewise.
753 (aarch64_ins_sve_limm_mov): Likewise.
754 (aarch64_ins_sve_shlimm): Likewise.
755 (aarch64_ins_sve_shrimm): Likewise.
756 * aarch64-asm-2.c: Regenerate.
757 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
758 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
759 * aarch64-dis.c (decode_limm): New function, split out from...
760 (aarch64_ext_limm): ...here.
761 (aarch64_ext_inv_limm): New function.
762 (decode_sve_aimm): Likewise.
763 (aarch64_ext_sve_aimm): Likewise.
764 (aarch64_ext_sve_asimm): Likewise.
765 (aarch64_ext_sve_limm_mov): Likewise.
766 (aarch64_top_bit): Likewise.
767 (aarch64_ext_sve_shlimm): Likewise.
768 (aarch64_ext_sve_shrimm): Likewise.
769 * aarch64-dis-2.c: Regenerate.
771 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
773 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
775 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
776 the AARCH64_MOD_MUL_VL entry.
777 (value_aligned_p): Cope with non-power-of-two alignments.
778 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
779 (print_immediate_offset_address): Likewise.
780 (aarch64_print_operand): Likewise.
781 * aarch64-opc-2.c: Regenerate.
782 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
783 (ins_sve_addr_ri_s9xvl): New inserters.
784 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
785 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
786 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
787 * aarch64-asm-2.c: Regenerate.
788 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
789 (ext_sve_addr_ri_s9xvl): New extractors.
790 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
791 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
792 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
793 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
794 * aarch64-dis-2.c: Regenerate.
796 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
798 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
800 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
801 (FLD_SVE_xs_22): New aarch64_field_kinds.
802 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
803 (get_operand_specific_data): New function.
804 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
805 FLD_SVE_xs_14 and FLD_SVE_xs_22.
806 (operand_general_constraint_met_p): Handle the new SVE address
808 (sve_reg): New array.
809 (get_addr_sve_reg_name): New function.
810 (aarch64_print_operand): Handle the new SVE address operands.
811 * aarch64-opc-2.c: Regenerate.
812 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
813 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
814 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
815 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
816 (aarch64_ins_sve_addr_rr_lsl): Likewise.
817 (aarch64_ins_sve_addr_rz_xtw): Likewise.
818 (aarch64_ins_sve_addr_zi_u5): Likewise.
819 (aarch64_ins_sve_addr_zz): Likewise.
820 (aarch64_ins_sve_addr_zz_lsl): Likewise.
821 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
822 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
823 * aarch64-asm-2.c: Regenerate.
824 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
825 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
826 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
827 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
828 (aarch64_ext_sve_addr_ri_u6): Likewise.
829 (aarch64_ext_sve_addr_rr_lsl): Likewise.
830 (aarch64_ext_sve_addr_rz_xtw): Likewise.
831 (aarch64_ext_sve_addr_zi_u5): Likewise.
832 (aarch64_ext_sve_addr_zz): Likewise.
833 (aarch64_ext_sve_addr_zz_lsl): Likewise.
834 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
835 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
836 * aarch64-dis-2.c: Regenerate.
838 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
840 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
841 AARCH64_OPND_SVE_PATTERN_SCALED.
842 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
843 * aarch64-opc.c (fields): Add a corresponding entry.
844 (set_multiplier_out_of_range_error): New function.
845 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
846 (operand_general_constraint_met_p): Handle
847 AARCH64_OPND_SVE_PATTERN_SCALED.
848 (print_register_offset_address): Use PRIi64 to print the
850 (aarch64_print_operand): Likewise. Handle
851 AARCH64_OPND_SVE_PATTERN_SCALED.
852 * aarch64-opc-2.c: Regenerate.
853 * aarch64-asm.h (ins_sve_scale): New inserter.
854 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
855 * aarch64-asm-2.c: Regenerate.
856 * aarch64-dis.h (ext_sve_scale): New inserter.
857 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
858 * aarch64-dis-2.c: Regenerate.
860 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
862 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
863 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
864 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
865 (FLD_SVE_prfop): Likewise.
866 * aarch64-opc.c: Include libiberty.h.
867 (aarch64_sve_pattern_array): New variable.
868 (aarch64_sve_prfop_array): Likewise.
869 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
870 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
871 AARCH64_OPND_SVE_PRFOP.
872 * aarch64-asm-2.c: Regenerate.
873 * aarch64-dis-2.c: Likewise.
874 * aarch64-opc-2.c: Likewise.
876 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
878 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
879 AARCH64_OPND_QLF_P_[ZM].
880 (aarch64_print_operand): Print /z and /m where appropriate.
882 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
884 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
885 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
886 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
887 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
888 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
889 * aarch64-opc.c (fields): Add corresponding entries here.
890 (operand_general_constraint_met_p): Check that SVE register lists
891 have the correct length. Check the ranges of SVE index registers.
892 Check for cases where p8-p15 are used in 3-bit predicate fields.
893 (aarch64_print_operand): Handle the new SVE operands.
894 * aarch64-opc-2.c: Regenerate.
895 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
896 * aarch64-asm.c (aarch64_ins_sve_index): New function.
897 (aarch64_ins_sve_reglist): Likewise.
898 * aarch64-asm-2.c: Regenerate.
899 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
900 * aarch64-dis.c (aarch64_ext_sve_index): New function.
901 (aarch64_ext_sve_reglist): Likewise.
902 * aarch64-dis-2.c: Regenerate.
904 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
906 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
907 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
908 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
909 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
912 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
914 * aarch64-opc.c (get_offset_int_reg_name): New function.
915 (print_immediate_offset_address): Likewise.
916 (print_register_offset_address): Take the base and offset
917 registers as parameters.
918 (aarch64_print_operand): Update caller accordingly. Use
919 print_immediate_offset_address.
921 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
923 * aarch64-opc.c (BANK): New macro.
924 (R32, R64): Take a register number as argument
927 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
929 * aarch64-opc.c (print_register_list): Add a prefix parameter.
930 (aarch64_print_operand): Update accordingly.
932 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
934 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
936 * aarch64-asm.h (ins_fpimm): New inserter.
937 * aarch64-asm.c (aarch64_ins_fpimm): New function.
938 * aarch64-asm-2.c: Regenerate.
939 * aarch64-dis.h (ext_fpimm): New extractor.
940 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
941 (aarch64_ext_fpimm): New function.
942 * aarch64-dis-2.c: Regenerate.
944 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
946 * aarch64-asm.c: Include libiberty.h.
947 (insert_fields): New function.
948 (aarch64_ins_imm): Use it.
949 * aarch64-dis.c (extract_fields): New function.
950 (aarch64_ext_imm): Use it.
952 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
954 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
955 with an esize parameter.
956 (operand_general_constraint_met_p): Update accordingly.
957 Fix misindented code.
958 * aarch64-asm.c (aarch64_ins_limm): Update call to
959 aarch64_logical_immediate_p.
961 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
963 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
965 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
967 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
969 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
971 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
973 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
975 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
976 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
977 xor3>: Delete mnemonics.
978 <cp_abort>: Rename mnemonic from ...
979 <cpabort>: ...to this.
980 <setb>: Change to a X form instruction.
981 <sync>: Change to 1 operand form.
982 <copy>: Delete mnemonic.
983 <copy_first>: Rename mnemonic from ...
985 <paste, paste.>: Delete mnemonics.
986 <paste_last>: Rename mnemonic from ...
987 <paste.>: ...to this.
989 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
991 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
993 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
995 * s390-mkopc.c (main): Support alternate arch strings.
997 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
999 * s390-opc.txt: Fix kmctr instruction type.
1001 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1003 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1004 * i386-init.h: Regenerated.
1006 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1008 * opcodes/arc-dis.c (print_insn_arc): Changed.
1010 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1012 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1015 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1017 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1018 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1019 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1021 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1023 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1024 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1025 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1026 PREFIX_MOD_3_0FAE_REG_4.
1027 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1028 PREFIX_MOD_3_0FAE_REG_4.
1029 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1030 (cpu_flags): Add CpuPTWRITE.
1031 * i386-opc.h (CpuPTWRITE): New.
1032 (i386_cpu_flags): Add cpuptwrite.
1033 * i386-opc.tbl: Add ptwrite instruction.
1034 * i386-init.h: Regenerated.
1035 * i386-tbl.h: Likewise.
1037 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1039 * arc-dis.h: Wrap around in extern "C".
1041 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1043 * aarch64-tbl.h (V8_2_INSN): New macro.
1044 (aarch64_opcode_table): Use it.
1046 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1048 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1049 CORE_INSN, __FP_INSN and SIMD_INSN.
1051 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1053 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1054 (aarch64_opcode_table): Update uses accordingly.
1056 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1057 Kwok Cheung Yeung <kcy@codesourcery.com>
1060 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1061 'e_cmplwi' to 'e_cmpli' instead.
1062 (OPVUPRT, OPVUPRT_MASK): Define.
1063 (powerpc_opcodes): Add E200Z4 insns.
1064 (vle_opcodes): Add context save/restore insns.
1066 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1068 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1069 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1072 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1074 * arc-nps400-tbl.h: Change block comments to GNU format.
1075 * arc-dis.c: Add new globals addrtypenames,
1076 addrtypenames_max, and addtypeunknown.
1077 (get_addrtype): New function.
1078 (print_insn_arc): Print colons and address types when
1080 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1081 define insert and extract functions for all address types.
1082 (arc_operands): Add operands for colon and all address
1084 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1085 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1086 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1087 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1088 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1089 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1091 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1093 * configure: Regenerated.
1095 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1097 * arc-dis.c (skipclass): New structure.
1098 (decodelist): New variable.
1099 (is_compatible_p): New function.
1100 (new_element): Likewise.
1101 (skip_class_p): Likewise.
1102 (find_format_from_table): Use skip_class_p function.
1103 (find_format): Decode first the extension instructions.
1104 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1106 (parse_option): New function.
1107 (parse_disassembler_options): Likewise.
1108 (print_arc_disassembler_options): Likewise.
1109 (print_insn_arc): Use parse_disassembler_options function. Proper
1110 select ARCv2 cpu variant.
1111 * disassemble.c (disassembler_usage): Add ARC disassembler
1114 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1116 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1117 annotation from the "nal" entry and reorder it beyond "bltzal".
1119 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1121 * sparc-opc.c (ldtxa): New macro.
1122 (sparc_opcodes): Use the macro defined above to add entries for
1123 the LDTXA instructions.
1124 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1127 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1129 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1132 2016-07-01 Jan Beulich <jbeulich@suse.com>
1134 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1135 (movzb): Adjust to cover all permitted suffixes.
1137 * i386-tbl.h: Re-generate.
1139 2016-07-01 Jan Beulich <jbeulich@suse.com>
1141 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1142 (lgdt): Remove Tbyte from non-64-bit variant.
1143 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1144 xsaves64, xsavec64): Remove Disp16.
1145 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1146 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1148 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1149 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1150 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1152 * i386-tbl.h: Re-generate.
1154 2016-07-01 Jan Beulich <jbeulich@suse.com>
1156 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1157 * i386-tbl.h: Re-generate.
1159 2016-06-30 Yao Qi <yao.qi@linaro.org>
1161 * arm-dis.c (print_insn): Fix typo in comment.
1163 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1165 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1166 range of ldst_elemlist operands.
1167 (print_register_list): Use PRIi64 to print the index.
1168 (aarch64_print_operand): Likewise.
1170 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1172 * mcore-opc.h: Remove sentinal.
1173 * mcore-dis.c (print_insn_mcore): Adjust.
1175 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1177 * arc-opc.c: Correct description of availability of NPS400
1180 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1182 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1183 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1184 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1185 xor3>: New mnemonics.
1186 <setb>: Change to a VX form instruction.
1187 (insert_sh6): Add support for rldixor.
1188 (extract_sh6): Likewise.
1190 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1192 * arc-ext.h: Wrap in extern C.
1194 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1196 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1197 Use same method for determining instruction length on ARC700 and
1199 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1200 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1201 with the NPS400 subclass.
1202 * arc-opc.c: Likewise.
1204 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1206 * sparc-opc.c (rdasr): New macro.
1212 (sparc_opcodes): Use the macros above to fix and expand the
1213 definition of read/write instructions from/to
1214 asr/privileged/hyperprivileged instructions.
1215 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1216 %hva_mask_nz. Prefer softint_set and softint_clear over
1217 set_softint and clear_softint.
1218 (print_insn_sparc): Support %ver in Rd.
1220 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1222 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1223 architecture according to the hardware capabilities they require.
1225 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1227 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1228 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1229 bfd_mach_sparc_v9{c,d,e,v,m}.
1230 * sparc-opc.c (MASK_V9C): Define.
1231 (MASK_V9D): Likewise.
1232 (MASK_V9E): Likewise.
1233 (MASK_V9V): Likewise.
1234 (MASK_V9M): Likewise.
1235 (v6): Add MASK_V9{C,D,E,V,M}.
1236 (v6notlet): Likewise.
1240 (v9andleon): Likewise.
1248 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1250 2016-06-15 Nick Clifton <nickc@redhat.com>
1252 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1253 constants to match expected behaviour.
1254 (nds32_parse_opcode): Likewise. Also for whitespace.
1256 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1258 * arc-opc.c (extract_rhv1): Extract value from insn.
1260 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1262 * arc-nps400-tbl.h: Add ldbit instruction.
1263 * arc-opc.c: Add flag classes required for ldbit.
1265 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1267 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1268 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1269 support the above instructions.
1271 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1273 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1274 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1275 csma, cbba, zncv, and hofs.
1276 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1277 support the above instructions.
1279 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1281 * arc-nps400-tbl.h: Add andab and orab instructions.
1283 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1285 * arc-nps400-tbl.h: Add addl-like instructions.
1287 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1289 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1291 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1293 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1296 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1298 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1300 (init_disasm): Handle new command line option "insnlength".
1301 (print_s390_disassembler_options): Mention new option in help
1303 (print_insn_s390): Use the encoded insn length when dumping
1304 unknown instructions.
1306 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1308 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1309 to the address and set as symbol address for LDS/ STS immediate operands.
1311 2016-06-07 Alan Modra <amodra@gmail.com>
1313 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1314 cpu for "vle" to e500.
1315 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1316 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1317 (PPCNONE): Delete, substitute throughout.
1318 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1319 except for major opcode 4 and 31.
1320 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1322 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1324 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1325 ARM_EXT_RAS in relevant entries.
1327 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1330 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1333 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1336 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1337 (indir_v_mode): New.
1338 Add comments for '&'.
1339 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1340 (putop): Handle '&'.
1341 (intel_operand_size): Handle indir_v_mode.
1342 (OP_E_register): Likewise.
1343 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1344 64-bit indirect call/jmp for AMD64.
1345 * i386-tbl.h: Regenerated
1347 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1349 * arc-dis.c (struct arc_operand_iterator): New structure.
1350 (find_format_from_table): All the old content from find_format,
1351 with some minor adjustments, and parameter renaming.
1352 (find_format_long_instructions): New function.
1353 (find_format): Rewritten.
1354 (arc_insn_length): Add LSB parameter.
1355 (extract_operand_value): New function.
1356 (operand_iterator_next): New function.
1357 (print_insn_arc): Use new functions to find opcode, and iterator
1359 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1360 (extract_nps_3bit_dst_short): New function.
1361 (insert_nps_3bit_src2_short): New function.
1362 (extract_nps_3bit_src2_short): New function.
1363 (insert_nps_bitop1_size): New function.
1364 (extract_nps_bitop1_size): New function.
1365 (insert_nps_bitop2_size): New function.
1366 (extract_nps_bitop2_size): New function.
1367 (insert_nps_bitop_mod4_msb): New function.
1368 (extract_nps_bitop_mod4_msb): New function.
1369 (insert_nps_bitop_mod4_lsb): New function.
1370 (extract_nps_bitop_mod4_lsb): New function.
1371 (insert_nps_bitop_dst_pos3_pos4): New function.
1372 (extract_nps_bitop_dst_pos3_pos4): New function.
1373 (insert_nps_bitop_ins_ext): New function.
1374 (extract_nps_bitop_ins_ext): New function.
1375 (arc_operands): Add new operands.
1376 (arc_long_opcodes): New global array.
1377 (arc_num_long_opcodes): New global.
1378 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1380 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1382 * nds32-asm.h: Add extern "C".
1383 * sh-opc.h: Likewise.
1385 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1387 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1388 0,b,limm to the rflt instruction.
1390 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1392 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1395 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1398 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1399 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1400 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1401 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1402 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1403 * i386-init.h: Regenerated.
1405 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1408 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1409 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1410 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1411 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1412 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1413 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1414 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1415 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1416 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1417 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1418 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1419 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1420 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1421 CpuRegMask for AVX512.
1422 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1424 (set_bitfield_from_cpu_flag_init): New function.
1425 (set_bitfield): Remove const on f. Call
1426 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1427 * i386-opc.h (CpuRegMMX): New.
1428 (CpuRegXMM): Likewise.
1429 (CpuRegYMM): Likewise.
1430 (CpuRegZMM): Likewise.
1431 (CpuRegMask): Likewise.
1432 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1434 * i386-init.h: Regenerated.
1435 * i386-tbl.h: Likewise.
1437 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1440 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1441 (opcode_modifiers): Add AMD64 and Intel64.
1442 (main): Properly verify CpuMax.
1443 * i386-opc.h (CpuAMD64): Removed.
1444 (CpuIntel64): Likewise.
1445 (CpuMax): Set to CpuNo64.
1446 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1448 (Intel64): Likewise.
1449 (i386_opcode_modifier): Add amd64 and intel64.
1450 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1452 * i386-init.h: Regenerated.
1453 * i386-tbl.h: Likewise.
1455 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1458 * i386-gen.c (main): Fail if CpuMax is incorrect.
1459 * i386-opc.h (CpuMax): Set to CpuIntel64.
1460 * i386-tbl.h: Regenerated.
1462 2016-05-27 Nick Clifton <nickc@redhat.com>
1465 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1466 (msp430dis_opcode_unsigned): New function.
1467 (msp430dis_opcode_signed): New function.
1468 (msp430_singleoperand): Use the new opcode reading functions.
1469 Only disassenmble bytes if they were successfully read.
1470 (msp430_doubleoperand): Likewise.
1471 (msp430_branchinstr): Likewise.
1472 (msp430x_callx_instr): Likewise.
1473 (print_insn_msp430): Check that it is safe to read bytes before
1474 attempting disassembly. Use the new opcode reading functions.
1476 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1478 * ppc-opc.c (CY): New define. Document it.
1479 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1481 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1483 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1484 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1485 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1486 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1488 * i386-init.h: Regenerated.
1490 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1493 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1494 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1495 * i386-init.h: Regenerated.
1497 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1499 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1500 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1501 * i386-init.h: Regenerated.
1503 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1505 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1507 (print_insn_arc): Set insn_type information.
1508 * arc-opc.c (C_CC): Add F_CLASS_COND.
1509 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1510 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1511 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1512 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1513 (brne, brne_s, jeq_s, jne_s): Likewise.
1515 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1517 * arc-tbl.h (neg): New instruction variant.
1519 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1521 * arc-dis.c (find_format, find_format, get_auxreg)
1522 (print_insn_arc): Changed.
1523 * arc-ext.h (INSERT_XOP): Likewise.
1525 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1527 * tic54x-dis.c (sprint_mmr): Adjust.
1528 * tic54x-opc.c: Likewise.
1530 2016-05-19 Alan Modra <amodra@gmail.com>
1532 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1534 2016-05-19 Alan Modra <amodra@gmail.com>
1536 * ppc-opc.c: Formatting.
1537 (NSISIGNOPT): Define.
1538 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1540 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1542 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1543 replacing references to `micromips_ase' throughout.
1544 (_print_insn_mips): Don't use file-level microMIPS annotation to
1545 determine the disassembly mode with the symbol table.
1547 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1549 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1551 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1553 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1555 * mips-opc.c (D34): New macro.
1556 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1558 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1560 * i386-dis.c (prefix_table): Add RDPID instruction.
1561 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1562 (cpu_flags): Add RDPID bitfield.
1563 * i386-opc.h (enum): Add RDPID element.
1564 (i386_cpu_flags): Add RDPID field.
1565 * i386-opc.tbl: Add RDPID instruction.
1566 * i386-init.h: Regenerate.
1567 * i386-tbl.h: Regenerate.
1569 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1571 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1572 branch type of a symbol.
1573 (print_insn): Likewise.
1575 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1577 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1578 Mainline Security Extensions instructions.
1579 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1580 Extensions instructions.
1581 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1583 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1586 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1588 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1590 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1592 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1593 (arcExtMap_genOpcode): Likewise.
1594 * arc-opc.c (arg_32bit_rc): Define new variable.
1595 (arg_32bit_u6): Likewise.
1596 (arg_32bit_limm): Likewise.
1598 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1600 * aarch64-gen.c (VERIFIER): Define.
1601 * aarch64-opc.c (VERIFIER): Define.
1602 (verify_ldpsw): Use static linkage.
1603 * aarch64-opc.h (verify_ldpsw): Remove.
1604 * aarch64-tbl.h: Use VERIFIER for verifiers.
1606 2016-04-28 Nick Clifton <nickc@redhat.com>
1609 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1610 * aarch64-opc.c (verify_ldpsw): New function.
1611 * aarch64-opc.h (verify_ldpsw): New prototype.
1612 * aarch64-tbl.h: Add initialiser for verifier field.
1613 (LDPSW): Set verifier to verify_ldpsw.
1615 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1619 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1620 smaller than address size.
1622 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1624 * alpha-dis.c: Regenerate.
1625 * crx-dis.c: Likewise.
1626 * disassemble.c: Likewise.
1627 * epiphany-opc.c: Likewise.
1628 * fr30-opc.c: Likewise.
1629 * frv-opc.c: Likewise.
1630 * ip2k-opc.c: Likewise.
1631 * iq2000-opc.c: Likewise.
1632 * lm32-opc.c: Likewise.
1633 * lm32-opinst.c: Likewise.
1634 * m32c-opc.c: Likewise.
1635 * m32r-opc.c: Likewise.
1636 * m32r-opinst.c: Likewise.
1637 * mep-opc.c: Likewise.
1638 * mt-opc.c: Likewise.
1639 * or1k-opc.c: Likewise.
1640 * or1k-opinst.c: Likewise.
1641 * tic80-opc.c: Likewise.
1642 * xc16x-opc.c: Likewise.
1643 * xstormy16-opc.c: Likewise.
1645 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1647 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1648 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1649 calcsd, and calcxd instructions.
1650 * arc-opc.c (insert_nps_bitop_size): Delete.
1651 (extract_nps_bitop_size): Delete.
1652 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1653 (extract_nps_qcmp_m3): Define.
1654 (extract_nps_qcmp_m2): Define.
1655 (extract_nps_qcmp_m1): Define.
1656 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1657 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1658 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1659 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1660 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1663 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1665 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1667 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1669 * Makefile.in: Regenerated with automake 1.11.6.
1670 * aclocal.m4: Likewise.
1672 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1674 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1676 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1677 (extract_nps_cmem_uimm16): New function.
1678 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1680 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1682 * arc-dis.c (arc_insn_length): New function.
1683 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1684 (find_format): Change insnLen parameter to unsigned.
1686 2016-04-13 Nick Clifton <nickc@redhat.com>
1689 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1690 the LD.B and LD.BU instructions.
1692 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1694 * arc-dis.c (find_format): Check for extension flags.
1695 (print_flags): New function.
1696 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1698 * arc-ext.c (arcExtMap_coreRegName): Use
1699 LAST_EXTENSION_CORE_REGISTER.
1700 (arcExtMap_coreReadWrite): Likewise.
1701 (dump_ARC_extmap): Update printing.
1702 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1703 (arc_aux_regs): Add cpu field.
1704 * arc-regs.h: Add cpu field, lower case name aux registers.
1706 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1708 * arc-tbl.h: Add rtsc, sleep with no arguments.
1710 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1712 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1714 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1715 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1716 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1717 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1718 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1719 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1720 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1721 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1722 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1723 (arc_opcode arc_opcodes): Null terminate the array.
1724 (arc_num_opcodes): Remove.
1725 * arc-ext.h (INSERT_XOP): Define.
1726 (extInstruction_t): Likewise.
1727 (arcExtMap_instName): Delete.
1728 (arcExtMap_insn): New function.
1729 (arcExtMap_genOpcode): Likewise.
1730 * arc-ext.c (ExtInstruction): Remove.
1731 (create_map): Zero initialize instruction fields.
1732 (arcExtMap_instName): Remove.
1733 (arcExtMap_insn): New function.
1734 (dump_ARC_extmap): More info while debuging.
1735 (arcExtMap_genOpcode): New function.
1736 * arc-dis.c (find_format): New function.
1737 (print_insn_arc): Use find_format.
1738 (arc_get_disassembler): Enable dump_ARC_extmap only when
1741 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1743 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1744 instruction bits out.
1746 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1748 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1749 * arc-opc.c (arc_flag_operands): Add new flags.
1750 (arc_flag_classes): Add new classes.
1752 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1754 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1756 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1758 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1759 encode1, rflt, crc16, and crc32 instructions.
1760 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1761 (arc_flag_classes): Add C_NPS_R.
1762 (insert_nps_bitop_size_2b): New function.
1763 (extract_nps_bitop_size_2b): Likewise.
1764 (insert_nps_bitop_uimm8): Likewise.
1765 (extract_nps_bitop_uimm8): Likewise.
1766 (arc_operands): Add new operand entries.
1768 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1770 * arc-regs.h: Add a new subclass field. Add double assist
1771 accumulator register values.
1772 * arc-tbl.h: Use DPA subclass to mark the double assist
1773 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1774 * arc-opc.c (RSP): Define instead of SP.
1775 (arc_aux_regs): Add the subclass field.
1777 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1779 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1781 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1783 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1786 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1788 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1789 issues. No functional changes.
1791 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1793 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1794 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1795 (RTT): Remove duplicate.
1796 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1797 (PCT_CONFIG*): Remove.
1798 (D1L, D1H, D2H, D2L): Define.
1800 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1802 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1804 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1806 * arc-tbl.h (invld07): Remove.
1807 * arc-ext-tbl.h: New file.
1808 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1809 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1811 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1813 Fix -Wstack-usage warnings.
1814 * aarch64-dis.c (print_operands): Substitute size.
1815 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1817 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1819 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1820 to get a proper diagnostic when an invalid ASR register is used.
1822 2016-03-22 Nick Clifton <nickc@redhat.com>
1824 * configure: Regenerate.
1826 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1828 * arc-nps400-tbl.h: New file.
1829 * arc-opc.c: Add top level comment.
1830 (insert_nps_3bit_dst): New function.
1831 (extract_nps_3bit_dst): New function.
1832 (insert_nps_3bit_src2): New function.
1833 (extract_nps_3bit_src2): New function.
1834 (insert_nps_bitop_size): New function.
1835 (extract_nps_bitop_size): New function.
1836 (arc_flag_operands): Add nps400 entries.
1837 (arc_flag_classes): Add nps400 entries.
1838 (arc_operands): Add nps400 entries.
1839 (arc_opcodes): Add nps400 include.
1841 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1843 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1844 the new class enum values.
1846 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1848 * arc-dis.c (print_insn_arc): Handle nps400.
1850 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1852 * arc-opc.c (BASE): Delete.
1854 2016-03-18 Nick Clifton <nickc@redhat.com>
1857 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1858 of MOV insn that aliases an ORR insn.
1860 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1862 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1864 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1866 * mcore-opc.h: Add const qualifiers.
1867 * microblaze-opc.h (struct op_code_struct): Likewise.
1868 * sh-opc.h: Likewise.
1869 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1870 (tic4x_print_op): Likewise.
1872 2016-03-02 Alan Modra <amodra@gmail.com>
1874 * or1k-desc.h: Regenerate.
1875 * fr30-ibld.c: Regenerate.
1876 * rl78-decode.c: Regenerate.
1878 2016-03-01 Nick Clifton <nickc@redhat.com>
1881 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1883 2016-02-24 Renlin Li <renlin.li@arm.com>
1885 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1886 (print_insn_coprocessor): Support fp16 instructions.
1888 2016-02-24 Renlin Li <renlin.li@arm.com>
1890 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1891 vminnm, vrint(mpna).
1893 2016-02-24 Renlin Li <renlin.li@arm.com>
1895 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1896 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1898 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1900 * i386-dis.c (print_insn): Parenthesize expression to prevent
1901 truncated addresses.
1904 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1905 Janek van Oirschot <jvanoirs@synopsys.com>
1907 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1910 2016-02-04 Nick Clifton <nickc@redhat.com>
1913 * msp430-dis.c (print_insn_msp430): Add a special case for
1914 decoding an RRC instruction with the ZC bit set in the extension
1917 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1919 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1920 * epiphany-ibld.c: Regenerate.
1921 * fr30-ibld.c: Regenerate.
1922 * frv-ibld.c: Regenerate.
1923 * ip2k-ibld.c: Regenerate.
1924 * iq2000-ibld.c: Regenerate.
1925 * lm32-ibld.c: Regenerate.
1926 * m32c-ibld.c: Regenerate.
1927 * m32r-ibld.c: Regenerate.
1928 * mep-ibld.c: Regenerate.
1929 * mt-ibld.c: Regenerate.
1930 * or1k-ibld.c: Regenerate.
1931 * xc16x-ibld.c: Regenerate.
1932 * xstormy16-ibld.c: Regenerate.
1934 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1936 * epiphany-dis.c: Regenerated from latest cpu files.
1938 2016-02-01 Michael McConville <mmcco@mykolab.com>
1940 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1943 2016-01-25 Renlin Li <renlin.li@arm.com>
1945 * arm-dis.c (mapping_symbol_for_insn): New function.
1946 (find_ifthen_state): Call mapping_symbol_for_insn().
1948 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1950 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1951 of MSR UAO immediate operand.
1953 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1955 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1956 instruction support.
1958 2016-01-17 Alan Modra <amodra@gmail.com>
1960 * configure: Regenerate.
1962 2016-01-14 Nick Clifton <nickc@redhat.com>
1964 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1965 instructions that can support stack pointer operations.
1966 * rl78-decode.c: Regenerate.
1967 * rl78-dis.c: Fix display of stack pointer in MOVW based
1970 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1972 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1973 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1974 erxtatus_el1 and erxaddr_el1.
1976 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1978 * arm-dis.c (arm_opcodes): Add "esb".
1979 (thumb_opcodes): Likewise.
1981 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1983 * ppc-opc.c <xscmpnedp>: Delete.
1984 <xvcmpnedp>: Likewise.
1985 <xvcmpnedp.>: Likewise.
1986 <xvcmpnesp>: Likewise.
1987 <xvcmpnesp.>: Likewise.
1989 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1992 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1995 2016-01-01 Alan Modra <amodra@gmail.com>
1997 Update year range in copyright notice of all files.
1999 For older changes see ChangeLog-2015
2001 Copyright (C) 2016 Free Software Foundation, Inc.
2003 Copying and distribution of this file, with or without modification,
2004 are permitted in any medium without royalty provided the copyright
2005 notice and this notice are preserved.
2011 version-control: never