opcodes/ChangeLog

   1 2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
   2
   3         * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
   4         stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
   5         ARM_EXT_V8.
   6         (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
   7
   8 2015-12-22  Yoshinori Sato <ysato@users.sourceforge.jp>
   9
  10 opcodes/
  11         * rx-decode.opc (movco): Use uniqe id.
  12         (movli): Likewise.
  13         (stnz): Condition fix.
  14         (mvtacgu): Destination fix.
  15         * rx-decode.c: Regenerate.
  16
  17 2015-12-14  Yoshinori Sato <ysato@users.sourceforge.jp>
  18
  19         * rx-deocde.opc: Add new instructions pattern.
  20         * rx-deocde.c: Regenerate.
  21         * rx-dis.c (register_name): Add new register.
  22
  23 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  24
  25         * aarch64-asm-2.c: Regenerate.
  26         * aarch64-dis-2.c: Regenerate.
  27         * aarch64-opc-2.c: Regenerate.
  28         * aarch64-tbl.h (QL_SSHIFT_H): New.
  29         (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
  30         and fcvtzu to the Adv.SIMD scalar shift by immediate group.
  31
  32 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  33
  34         * aarch64-asm-2.c: Regenerate.
  35         * aarch64-dis-2.c: Regenerate.
  36         * aarch64-opc-2.c: Regenerate.
  37         * aarch64-tbl.h (QL_VSHIFT_H): New.
  38         (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
  39         and fcvtzu to the Adv.SIMD shift by immediate group.
  40
  41 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  42
  43         * aarch64-asm-2.c: Regenerate.
  44         * aarch64-dis-2.c: Regenerate.
  45         * aarch64-opc-2.c: Regenerate.
  46         * aarch64-tbl.h (QL_SISD_PAIR_H): New.
  47         (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
  48         fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
  49
  50 2015-12-14  Matthew Wahab  <matthew.wahab@arm.coM>
  51
  52         * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
  53         and adjust calculation to ignore qualifier for type 2H.
  54         * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
  55
  56 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  57
  58         * aarch64-asm-2.c: Regenerate.
  59         * aarch64-dis-2.c: Regenerate.
  60         * aarch64-opc-2.c: Regenerate.
  61         * aarch64-tbl.h (QL_SIMD_IMM_H): New.
  62         (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
  63         modified immediate group.
  64
  65 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  66
  67         * aarch64-asm-2.c: Regenerate.
  68         * aarch64-dis-2.c: Regenerate.
  69         * aarch64-opc-2.c: Regenerate.
  70         * aarch64-tbl.h (QL_XLANES_FP_H): New.
  71         (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
  72         fminnmv, fminv to the Adv.SIMD across lanes group.
  73
  74 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  75
  76         * aarch64-asm-2.c: Regenerate.
  77         * aarch64-dis-2.c: Regenerate.
  78         * aarch64-opc-2.c: Regenerate.
  79         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
  80         fmls, fmul and fmulx to the scalar indexed element group.
  81
  82 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  83
  84         * aarch64-asm-2.c: Regenerate.
  85         * aarch64-dis-2.c: Regenerate.
  86         * aarch64-opc-2.c: Regenerate.
  87         * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
  88         (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
  89         fmulx to the vector indexed element group.
  90
  91 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  92
  93         * aarch64-asm-2.c: Regenerate.
  94         * aarch64-dis-2.c: Regenerate.
  95         * aarch64-opc-2.c: Regenerate.
  96         * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
  97         (QL_S_2SAMEH): New.
  98         (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
  99         fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
 100         frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
 101         fcvtzu and frsqrte to the scalar two register misc. group.
 102
 103 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 104
 105         * aarch64-asm-2.c: Regenerate.
 106         * aarch64-dis-2.c: Regenerate.
 107         * aarch64-opc-2.c: Regenerate.
 108         * aarch64-tbl.h (QL_V2SAMEH): New.
 109         (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
 110         fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
 111         frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
 112         fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
 113         and fsqrt to the vector register misc. group.
 114
 115 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 116
 117         * aarch64-asm-2.c: Regenerate.
 118         * aarch64-dis-2.c: Regenerate.
 119         * aarch64-opc-2.c: Regenerate.
 120         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
 121         fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
 122         to the scalar three same group.
 123
 124 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 125
 126         * aarch64-asm-2.c: Regenerate.
 127         * aarch64-dis-2.c: Regenerate.
 128         * aarch64-opc-2.c: Regenerate.
 129         * aarch64-tbl.h (QL_V3SAMEH): New.
 130         (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
 131         fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
 132         fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
 133         fcmgt, facgt and fminp to the vector three same group.
 134
 135 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 136
 137         * aarch64-tbl.h (aarch64_feature_simd_f16): New.
 138         (SIMD_F16): New.
 139
 140 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 141
 142         * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
 143         removed statement.
 144         (aarch64_pstatefield_supported_p): Move feature checks for AT
 145         registers ..
 146         (aarch64_sys_ins_reg_supported_p): .. to here.
 147
 148 2015-12-12  Alan Modra  <amodra@gmail.com>
 149
 150         PR 19359
 151         * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
 152         (powerpc_opcodes): Remove single-operand mfcr.
 153
 154 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 155
 156         * aarch64-asm.c (aarch64_ins_hint): New.
 157         * aarch64-asm.h (aarch64_ins_hint): Declare.
 158         * aarch64-dis.c (aarch64_ext_hint): New.
 159         * aarch64-dis.h (aarch64_ext_hint): Declare.
 160         * aarch64-opc-2.c: Regenerate.
 161         * aarch64-opc.c (aarch64_hint_options): New.
 162         * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
 163
 164 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 165
 166         * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
 167
 168 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 169
 170         * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
 171         pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
 172         pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
 173         pmscr_el2.
 174         (aarch64_sys_reg_supported_p): Add architecture feature tests for
 175         the new registers.
 176
 177 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 178
 179         * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
 180         (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
 181         feature test for "s1e1rp" and "s1e1wp".
 182
 183 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 184
 185         * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
 186         (aarch64_sys_ins_reg_supported_p): New.
 187
 188 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 189
 190         * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
 191         with aarch64_sys_ins_reg_has_xt.
 192         (aarch64_ext_sysins_op): Likewise.
 193         * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
 194         (F_HASXT): New.
 195         (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
 196         (aarch64_sys_regs_dc): Likewise.
 197         (aarch64_sys_regs_at): Likewise.
 198         (aarch64_sys_regs_tlbi): Likewise.
 199         (aarch64_sys_ins_reg_has_xt): New.
 200
 201 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 202
 203         * aarch64-opc.c (aarch64_sys_regs): Add "uao".
 204         (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
 205         (aarch64_pstatefields): Add "uao".
 206         (aarch64_pstatefield_supported_p): Add checks for "uao".
 207
 208 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 209
 210         * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
 211         "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
 212         "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
 213         (aarch64_sys_reg_supported_p): Add architecture feature tests for
 214         new registers.
 215
 216 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 217
 218         * aarch64-asm-2.c: Regenerate.
 219         * aarch64-dis-2.c: Regenerate.
 220         * aarch64-tbl.h (aarch64_feature_ras): New.
 221         (RAS): New.
 222         (aarch64_opcode_table): Add "esb".
 223
 224 2015-12-09  H.J. Lu  <hongjiu.lu@intel.com>
 225
 226         * i386-dis.c (MOD_0F01_REG_5): New.
 227         (RM_0F01_REG_5): Likewise.
 228         (reg_table): Use MOD_0F01_REG_5.
 229         (mod_table): Add MOD_0F01_REG_5.
 230         (rm_table): Add RM_0F01_REG_5.
 231         * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
 232         (cpu_flags): Add CpuOSPKE.
 233         * i386-opc.h (CpuOSPKE): New.
 234         (i386_cpu_flags): Add cpuospke.
 235         * i386-opc.tbl: Add rdpkru and wrpkru instructions.
 236         * i386-init.h: Regenerated.
 237         * i386-tbl.h: Likewise.
 238
 239 2015-12-07  DJ Delorie  <dj@redhat.com>
 240
 241         * rl78-decode.opc: Enable MULU for all ISAs.
 242         * rl78-decode.c: Regenerate.
 243
 244 2015-12-07  Alan Modra  <amodra@gmail.com>
 245
 246         * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
 247         major opcode/xop.
 248
 249 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
 250
 251         * arc-dis.c (special_flag_p): Match full mnemonic.
 252         * arc-opc.c (print_insn_arc): Check section size to read
 253         appropriate number of bytes. Fix printing.
 254         * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
 255         arguments.
 256
 257 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 258
 259         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
 260         <ldah>: ... to this.
 261
 262 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 263
 264         * aarch64-asm-2.c: Regenerate.
 265         * aarch64-dis-2.c: Regenerate.
 266         * aarch64-opc-2.c: Regenerate.
 267         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
 268         (QL_INT2FP_H, QL_FP2INT_H): New.
 269         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
 270         (QL_DST_H): New.
 271         (QL_FCCMP_H): New.
 272         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
 273         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
 274         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
 275         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
 276         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
 277         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
 278         fcsel.
 279
 280 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 281
 282         * aarch64-opc.c (half_conv_t): New.
 283         (expand_fp_imm): Replace is_dp flag with the parameter size to
 284         specify the number of bytes for the required expansion.  Treat
 285         a 16-bit expansion like a 32-bit expansion.  Add check for an
 286         unsupported size request.  Update comment.
 287         (aarch64_print_operand): Update to support 16-bit floating point
 288         values.  Update for changes to expand_fp_imm.
 289
 290 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 291
 292         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
 293         (FP_F16): New.
 294
 295 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 296
 297         * aarch64-asm-2.c: Regenerate.
 298         * aarch64-dis-2.c: Regenerate.
 299         * aarch64-opc-2.c: Regenerate.
 300         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
 301         "rev64".
 302
 303 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 304
 305         * aarch64-asm-2.c: Regenerate.
 306         * aarch64-asm.c (convert_bfc_to_bfm): New.
 307         (convert_to_real): Add case for OP_BFC.
 308         * aarch64-dis-2.c: Regenerate.
 309         * aarch64-dis.c: (convert_bfm_to_bfc): New.
 310         (convert_to_alias): Add case for OP_BFC.
 311         * aarch64-opc-2.c: Regenerate.
 312         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
 313         to allow width operand in three-operand instructions.
 314         * aarch64-tbl.h (QL_BF1): New.
 315         (aarch64_feature_v8_2): New.
 316         (ARMV8_2): New.
 317         (aarch64_opcode_table): Add "bfc".
 318
 319 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 320
 321         * aarch64-asm-2.c: Regenerate.
 322         * aarch64-dis-2.c: Regenerate.
 323         * aarch64-dis.c: Weaken assert.
 324         * aarch64-gen.c: Include the instruction in the list of its
 325         possible aliases.
 326
 327 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 328
 329         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
 330         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
 331         feature test.
 332
 333 2015-11-23  Tristan Gingold  <gingold@adacore.com>
 334
 335         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
 336
 337 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
 338
 339         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
 340         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
 341         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
 342         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
 343         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
 344         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
 345         cnthv_ctl_el2, cnthv_cval_el2.
 346         (aarch64_sys_reg_supported_p): Update for the new system
 347         registers.
 348
 349 2015-11-20  Nick Clifton  <nickc@redhat.com>
 350
 351         PR binutils/19224
 352         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
 353
 354 2015-11-20  Nick Clifton  <nickc@redhat.com>
 355
 356         * po/zh_CN.po: Updated simplified Chinese translation.
 357
 358 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 359
 360         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 361         of MSR PAN immediate operand.
 362
 363 2015-11-16  Nick Clifton  <nickc@redhat.com>
 364
 365         * rx-dis.c (condition_names): Replace always and never with
 366         invalid, since the always/never conditions can never be legal.
 367
 368 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 369
 370         * configure: Regenerate.
 371
 372 2015-11-11  Alan Modra  <amodra@gmail.com>
 373             Peter Bergner <bergner@vnet.ibm.com>
 374
 375         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 376         Add PPC_OPCODE_VSX3 to the vsx entry.
 377         (powerpc_init_dialect): Set default dialect to power9.
 378         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 379         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 380         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 381         (insert_esync): Test for illegal L operand value.
 382         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 383         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 384         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 385         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 386         PPCVSX3): New defines.
 387         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 388         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 389         <mcrxr>: Use XBFRARB_MASK.
 390         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 391         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 392         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 393         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 394         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 395         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 396         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 397         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 398         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 399         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 400         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 401         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 402         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 403         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 404         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 405         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 406         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 407         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 408         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 409         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 410         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 411         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 412         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 413         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 414         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 415         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 416         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 417         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 418         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 419         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 420         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 421         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 422
 423 2015-11-02  Nick Clifton  <nickc@redhat.com>
 424
 425         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 426         instructions.
 427         * rx-decode.c: Regenerate.
 428
 429 2015-11-02  Nick Clifton  <nickc@redhat.com>
 430
 431         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 432         type to RX_Operand_Zero_Indirect.
 433         * rx-decode.c: Regenerate.
 434         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 435
 436 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 437
 438         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 439         noaliases_p.  Update comments.  Pass noaliases_p rather than
 440         no_aliases to aarch64_opcode_decode.
 441         (print_insn_aarch64_word): Pass no_aliases to
 442         aarch64_decode_insn.
 443
 444 2015-10-27  Vinay  <Vinay.G@kpit.com>
 445
 446         PR binutils/19159
 447         * rl78-decode.opc (MOV): Added offset to DE register in index
 448         addressing mode.
 449         * rl78-decode.c: Regenerate.
 450
 451 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 452
 453         PR binutils/19158
 454         * rl78-decode.opc: Add 's' print operator to instructions that
 455         access system registers.
 456         * rl78-decode.c: Regenerate.
 457         * rl78-dis.c (print_insn_rl78_common): Decode all system
 458         registers.
 459
 460 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 461
 462         PR binutils/19157
 463         * rl78-decode.opc: Add 'a' print operator to mov instructions
 464         using stack pointer plus index addressing.
 465         * rl78-decode.c: Regenerate.
 466
 467 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 468
 469         * s390-opc.c: Fix comment.
 470         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 471         trtt to RRF_U0RER since the second parameter does not need to be a
 472         register pair.
 473
 474 2015-10-08  Nick Clifton  <nickc@redhat.com>
 475
 476         * arc-dis.c (print_insn_arc): Initiallise insn array.
 477
 478 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 479
 480         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 481         'name' rather than 'template'.
 482         * aarch64-opc.c (aarch64_print_operand): Likewise.
 483
 484 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 485
 486         * arc-dis.c: Revamped file for ARC support
 487         * arc-dis.h: Likewise.
 488         * arc-ext.c: Likewise.
 489         * arc-ext.h: Likewise.
 490         * arc-opc.c: Likewise.
 491         * arc-fxi.h: New file.
 492         * arc-regs.h: Likewise.
 493         * arc-tbl.h: Likewise.
 494
 495 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 496
 497         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 498         argument insn type to aarch64_insn.  Rename to ...
 499         (aarch64_decode_insn): ... it.
 500         (print_insn_aarch64_word): Caller updated.
 501
 502 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 503
 504         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 505         (print_insn_aarch64_word): Caller updated.
 506
 507 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 508
 509         * s390-mkopc.c (main): Parse htm and vx flag.
 510         * s390-opc.txt: Mark instructions from the hardware transactional
 511         memory and vector facilities with the "htm"/"vx" flag.
 512
 513 2015-09-28  Nick Clifton  <nickc@redhat.com>
 514
 515         * po/de.po: Updated German translation.
 516
 517 2015-09-28  Tom Rix  <tom@bumblecow.com>
 518
 519         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 520
 521 2015-09-23  Nick Clifton  <nickc@redhat.com>
 522
 523         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 524         function.
 525         * tic30-dis.c (print_branch): Likewise.
 526         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 527         value before left shifting.
 528         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 529         * hppa-dis.c (print_insn_hppa): Likewise.
 530         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 531         array.
 532         * msp430-dis.c (msp430_singleoperand): Likewise.
 533         (msp430_doubleoperand): Likewise.
 534         (print_insn_msp430): Likewise.
 535         * nds32-asm.c (parse_operand): Likewise.
 536         * sh-opc.h (MASK): Likewise.
 537         * v850-dis.c (get_operand_value): Likewise.
 538
 539 2015-09-22  Nick Clifton  <nickc@redhat.com>
 540
 541         * rx-decode.opc (bwl): Use RX_Bad_Size.
 542         (sbwl): Likewise.
 543         (ubwl): Likewise.  Rename to ubw.
 544         (uBWL): Rename to uBW.
 545         Replace all references to uBWL with uBW.
 546         * rx-decode.c: Regenerate.
 547         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 548         (opsize_names): Likewise.
 549         (print_insn_rx): Detect and report RX_Bad_Size.
 550
 551 2015-09-22  Anton Blanchard  <anton@samba.org>
 552
 553         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 554
 555 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 556
 557         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 558         %pmcdper.
 559
 560 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 561
 562         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 563
 564 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 565
 566         PR binutils/18257
 567         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 568         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 569         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 570         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 571         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 572         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 573         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 574         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 575         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 576         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 577         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 578         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 579         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 580         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 581         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 582         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 583         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 584         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 585         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 586         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 587         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 588         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 589         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 590         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 591         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 592         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 593         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 594         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 595         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 596         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 597         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 598         (vex_w_table): Replace terminals with MOD_TABLE entries for
 599         most of mask instructions.
 600
 601 2015-08-17  Alan Modra  <amodra@gmail.com>
 602
 603         * cgen.sh: Trim trailing space from cgen output.
 604         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 605         (print_dis_table): Likewise.
 606         * opc2c.c (dump_lines): Likewise.
 607         (orig_filename): Warning fix.
 608         * ia64-asmtab.c: Regenerate.
 609
 610 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 611
 612         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 613         and higher with ARM instruction set will now mark the 26-bit
 614         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 615         (arm_opcodes): Fix for unpredictable nop being recognized as a
 616         teq.
 617
 618 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 619
 620         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 621         based on 'or' is first.
 622         * mips-opc.c (mips_builtin_opcodes): Ditto.
 623
 624 2015-08-11  Nick Clifton  <nickc@redhat.com>
 625
 626         PR 18800
 627         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 628         instruction.
 629
 630 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 631
 632         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 633
 634 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 635
 636         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 637         * i386-init.h: Regenerated.
 638
 639 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 640
 641         PR binutils/13571
 642         * i386-dis.c (MOD_0FC3): New.
 643         (PREFIX_0FC3): Renamed to ...
 644         (PREFIX_MOD_0_0FC3): This.
 645         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 646         (prefix_table): Replace Ma with Ev on movntiS.
 647         (mod_table): Add MOD_0FC3.
 648
 649 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 650
 651         * configure: Regenerated.
 652
 653 2015-07-23  Alan Modra  <amodra@gmail.com>
 654
 655         PR 18708
 656         * i386-dis.c (get64): Avoid signed integer overflow.
 657
 658 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 659
 660         PR binutils/18631
 661         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 662         "EXEvexHalfBcstXmmq" for the second operand.
 663         (EVEX_W_0F79_P_2): Likewise.
 664         (EVEX_W_0F7A_P_2): Likewise.
 665         (EVEX_W_0F7B_P_2): Likewise.
 666
 667 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 668
 669         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 670         float bitfield format.
 671         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 672         quarter float bitfield format.
 673
 674 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 675
 676         * configure: Regenerated.
 677
 678 2015-07-03  Alan Modra  <amodra@gmail.com>
 679
 680         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 681         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 682         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 683
 684 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 685             Cesar Philippidis  <cesar@codesourcery.com>
 686
 687         * nios2-dis.c (nios2_extract_opcode): New.
 688         (nios2_disassembler_state): New.
 689         (nios2_find_opcode_hash): Use mach parameter to select correct
 690         disassembler state.
 691         (nios2_print_insn_arg): Extend to support new R2 argument letters
 692         and formats.
 693         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 694         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 695         (NIOS2_NUM_OPCODES): Rename to...
 696         (NIOS2_NUM_R1_OPCODES): This.
 697         (nios2_r2_opcodes): New.
 698         (NIOS2_NUM_R2_OPCODES): New.
 699         (nios2_num_r2_opcodes): New.
 700         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 701         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 702         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 703         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 704         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 705
 706 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 707
 708         * i386-dis.c (OP_Mwaitx): New.
 709         (rm_table): Add monitorx/mwaitx.
 710         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 711         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 712         (operand_type_init): Add CpuMWAITX.
 713         * i386-opc.h (CpuMWAITX): New.
 714         (i386_cpu_flags): Add cpumwaitx.
 715         * i386-opc.tbl: Add monitorx and mwaitx.
 716         * i386-init.h: Regenerated.
 717         * i386-tbl.h: Likewise.
 718
 719 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 720
 721         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 722         (insert_esync): New function.
 723         (LS, WC): Use insert_ls.
 724         (ESYNC): Use insert_esync.
 725
 726 2015-06-22  Nick Clifton  <nickc@redhat.com>
 727
 728         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 729         requested region lies beyond it.
 730         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 731         looking for 32-bit insns.
 732         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 733         data.
 734         * sh-dis.c (print_insn_sh): Likewise.
 735         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 736         blocks of instructions.
 737         * vax-dis.c (print_insn_vax): Check that the requested address
 738         does not clash with the stop_vma.
 739
 740 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 741
 742         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 743         * ppc-opc.c (FXM4): Add non-zero optional value.
 744         (TBR): Likewise.
 745         (SXL): Likewise.
 746         (insert_fxm): Handle new default operand value.
 747         (extract_fxm): Likewise.
 748         (insert_tbr): Likewise.
 749         (extract_tbr): Likewise.
 750
 751 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 752
 753         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 754
 755 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 756
 757         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 758
 759 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 760
 761         * ppc-opc.c: Add comment accidentally removed by old commit.
 762         (MTMSRD_L): Delete.
 763
 764 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 765
 766         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 767
 768 2015-06-04  Nick Clifton  <nickc@redhat.com>
 769
 770         PR 18474
 771         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 772
 773 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 774
 775         * arm-dis.c (arm_opcodes): Add "setpan".
 776         (thumb_opcodes): Add "setpan".
 777
 778 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 779
 780         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 781         macros.
 782
 783 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 784
 785         * aarch64-tbl.h (aarch64_feature_rdma): New.
 786         (RDMA): New.
 787         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 788         * aarch64-asm-2.c: Regenerate.
 789         * aarch64-dis-2.c: Regenerate.
 790         * aarch64-opc-2.c: Regenerate.
 791
 792 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 793
 794         * aarch64-tbl.h (aarch64_feature_lor): New.
 795         (LOR): New.
 796         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 797         "stllrb", "stllrh".
 798         * aarch64-asm-2.c: Regenerate.
 799         * aarch64-dis-2.c: Regenerate.
 800         * aarch64-opc-2.c: Regenerate.
 801
 802 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 803
 804         * aarch64-opc.c (F_ARCHEXT): New.
 805         (aarch64_sys_regs): Add "pan".
 806         (aarch64_sys_reg_supported_p): New.
 807         (aarch64_pstatefields): Add "pan".
 808         (aarch64_pstatefield_supported_p): New.
 809
 810 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 811
 812         * i386-tbl.h: Regenerate.
 813
 814 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-dis.c (print_insn): Swap rounding mode specifier and
 817         general purpose register in Intel mode.
 818
 819 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 820
 821         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 822         * i386-tbl.h: Regenerate.
 823
 824 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 825
 826         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 827         * i386-init.h: Regenerated.
 828
 829 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 830
 831         PR binutis/18386
 832         * i386-dis.c: Add comments for '@'.
 833         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 834         (enum x86_64_isa): New.
 835         (isa64): Likewise.
 836         (print_i386_disassembler_options): Add amd64 and intel64.
 837         (print_insn): Handle amd64 and intel64.
 838         (putop): Handle '@'.
 839         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 840         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 841         * i386-opc.h (AMD64): New.
 842         (CpuIntel64): Likewise.
 843         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 844         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 845         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 846         * i386-init.h: Regenerated.
 847         * i386-tbl.h: Likewise.
 848
 849 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 850
 851         * ppc-opc.c (IH) New define.
 852         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 853         <tlbie>: Add RS operand for POWER7.
 854         <slbia>: Add IH operand for POWER6.
 855
 856 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 857
 858         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 859         direct branch.
 860         (jmp): Likewise.
 861         * i386-tbl.h: Regenerated.
 862
 863 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 864
 865         * configure.ac: Support bfd_iamcu_arch.
 866         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 867         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 868         CPU_IAMCU_COMPAT_FLAGS.
 869         (cpu_flags): Add CpuIAMCU.
 870         * i386-opc.h (CpuIAMCU): New.
 871         (i386_cpu_flags): Add cpuiamcu.
 872         * configure: Regenerated.
 873         * i386-init.h: Likewise.
 874         * i386-tbl.h: Likewise.
 875
 876 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 877
 878         PR binutis/18386
 879         * i386-dis.c (X86_64_E8): New.
 880         (X86_64_E9): Likewise.
 881         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 882         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 883         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 884         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 885         (putop): Handle '^'.
 886         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 887         REX_W.
 888
 889 2015-04-30  DJ Delorie  <dj@redhat.com>
 890
 891         * disassemble.c (disassembler): Choose suitable disassembler based
 892         on E_ABI.
 893         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 894         it to decode mul/div insns.
 895         * rl78-decode.c: Regenerate.
 896         * rl78-dis.c (print_insn_rl78): Rename to...
 897         (print_insn_rl78_common): ...this, take ISA parameter.
 898         (print_insn_rl78): New.
 899         (print_insn_rl78_g10): New.
 900         (print_insn_rl78_g13): New.
 901         (print_insn_rl78_g14): New.
 902         (rl78_get_disassembler): New.
 903
 904 2015-04-29  Nick Clifton  <nickc@redhat.com>
 905
 906         * po/fr.po: Updated French translation.
 907
 908 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 909
 910         * ppc-opc.c (DCBT_EO): New define.
 911         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 912         <lharx>: Likewise.
 913         <stbcx.>: Likewise.
 914         <sthcx.>: Likewise.
 915         <waitrsv>: Do not enable for POWER7 and later.
 916         <waitimpl>: Likewise.
 917         <dcbt>: Default to the two operand form of the instruction for all
 918         "old" cpus.  For "new" cpus, use the operand ordering that matches
 919         whether the cpu is server or embedded.
 920         <dcbtst>: Likewise.
 921
 922 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 923
 924         * s390-opc.c: New instruction type VV0UU2.
 925         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 926         and WFC.
 927
 928 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 929
 930         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 931         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 932         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 933         (vfpclasspd, vfpclassps): Add %XZ.
 934
 935 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 936
 937         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 938         (PREFIX_UD_REPZ): Likewise.
 939         (PREFIX_UD_REPNZ): Likewise.
 940         (PREFIX_UD_DATA): Likewise.
 941         (PREFIX_UD_ADDR): Likewise.
 942         (PREFIX_UD_LOCK): Likewise.
 943
 944 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 945
 946         * i386-dis.c (prefix_requirement): Removed.
 947         (print_insn): Don't set prefix_requirement.  Check
 948         dp->prefix_requirement instead of prefix_requirement.
 949
 950 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 951
 952         PR binutils/17898
 953         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 954         (PREFIX_MOD_0_0FC7_REG_6): This.
 955         (PREFIX_MOD_3_0FC7_REG_6): New.
 956         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 957         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 958         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 959         PREFIX_MOD_3_0FC7_REG_7.
 960         (mod_table): Replace PREFIX_0FC7_REG_6 with
 961         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 962         PREFIX_MOD_3_0FC7_REG_7.
 963
 964 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 965
 966         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 967         (PREFIX_MANDATORY_REPNZ): Likewise.
 968         (PREFIX_MANDATORY_DATA): Likewise.
 969         (PREFIX_MANDATORY_ADDR): Likewise.
 970         (PREFIX_MANDATORY_LOCK): Likewise.
 971         (PREFIX_MANDATORY): Likewise.
 972         (PREFIX_UD_SHIFT): Set to 8
 973         (PREFIX_UD_REPZ): Updated.
 974         (PREFIX_UD_REPNZ): Likewise.
 975         (PREFIX_UD_DATA): Likewise.
 976         (PREFIX_UD_ADDR): Likewise.
 977         (PREFIX_UD_LOCK): Likewise.
 978         (PREFIX_IGNORED_SHIFT): New.
 979         (PREFIX_IGNORED_REPZ): Likewise.
 980         (PREFIX_IGNORED_REPNZ): Likewise.
 981         (PREFIX_IGNORED_DATA): Likewise.
 982         (PREFIX_IGNORED_ADDR): Likewise.
 983         (PREFIX_IGNORED_LOCK): Likewise.
 984         (PREFIX_OPCODE): Likewise.
 985         (PREFIX_IGNORED): Likewise.
 986         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 987         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 988         (three_byte_table): Likewise.
 989         (mod_table): Likewise.
 990         (mandatory_prefix): Renamed to ...
 991         (prefix_requirement): This.
 992         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 993         Update PREFIX_90 entry.
 994         (get_valid_dis386): Check prefix_requirement to see if a prefix
 995         should be ignored.
 996         (print_insn): Replace mandatory_prefix with prefix_requirement.
 997
 998 2015-04-15  Renlin Li  <renlin.li@arm.com>
 999
1000         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
1001         use it for ssat and ssat16.
1002         (print_insn_thumb32): Add handle case for 'D' control code.
1003
1004 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
1005             H.J. Lu  <hongjiu.lu@intel.com>
1006
1007         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
1008         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
1009         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
1010         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
1011         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
1012         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
1013         Fill prefix_requirement field.
1014         (struct dis386): Add prefix_requirement field.
1015         (dis386): Fill prefix_requirement field.
1016         (dis386_twobyte): Ditto.
1017         (twobyte_has_mandatory_prefix_: Remove.
1018         (reg_table): Fill prefix_requirement field.
1019         (prefix_table): Ditto.
1020         (x86_64_table): Ditto.
1021         (three_byte_table): Ditto.
1022         (xop_table): Ditto.
1023         (vex_table): Ditto.
1024         (vex_len_table): Ditto.
1025         (vex_w_table): Ditto.
1026         (mod_table): Ditto.
1027         (bad_opcode): Ditto.
1028         (print_insn): Use prefix_requirement.
1029         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
1030         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
1031         (float_reg): Ditto.
1032
1033 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
1034
1035         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
1036
1037 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1038
1039         * Makefile.in: Regenerated.
1040
1041 2015-03-25  Anton Blanchard  <anton@samba.org>
1042
1043         * ppc-dis.c (disassemble_init_powerpc): Only initialise
1044         powerpc_opcd_indices and vle_opcd_indices once.
1045
1046 2015-03-25  Anton Blanchard  <anton@samba.org>
1047
1048         * ppc-opc.c (powerpc_opcodes): Add slbfee.
1049
1050 2015-03-24  Terry Guo  <terry.guo@arm.com>
1051
1052         * arm-dis.c (opcode32): Updated to use new arm feature struct.
1053         (opcode16): Likewise.
1054         (coprocessor_opcodes): Replace bit with feature struct.
1055         (neon_opcodes): Likewise.
1056         (arm_opcodes): Likewise.
1057         (thumb_opcodes): Likewise.
1058         (thumb32_opcodes): Likewise.
1059         (print_insn_coprocessor): Likewise.
1060         (print_insn_arm): Likewise.
1061         (select_arm_features): Follow new feature struct.
1062
1063 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
1064
1065         * i386-dis.c (rm_table): Add clzero.
1066         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1067         Add CPU_CLZERO_FLAGS.
1068         (cpu_flags): Add CpuCLZERO.
1069         * i386-opc.h: Add CpuCLZERO.
1070         * i386-opc.tbl: Add clzero.
1071         * i386-init.h: Re-generated.
1072         * i386-tbl.h: Re-generated.
1073
1074 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
1075
1076         * mips-opc.c (decode_mips_operand): Fix constraint issues
1077         with u and y operands.
1078
1079 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
1080
1081         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1082
1083 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1084
1085         * s390-opc.c: Add new IBM z13 instructions.
1086         * s390-opc.txt: Likewise.
1087
1088 2015-03-10  Renlin Li  <renlin.li@arm.com>
1089
1090         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1091         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1092         related alias.
1093         * aarch64-asm-2.c: Regenerate.
1094         * aarch64-dis-2.c: Likewise.
1095         * aarch64-opc-2.c: Likewise.
1096
1097 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
1098
1099         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1100
1101 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
1102
1103         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1104         arch_sh_up.
1105         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1106         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1107
1108 2015-02-23  Vinay  <Vinay.G@kpit.com>
1109
1110         * rl78-decode.opc (MOV): Added space between two operands for
1111         'mov' instruction in index addressing mode.
1112         * rl78-decode.c: Regenerate.
1113
1114 2015-02-19  Pedro Alves  <palves@redhat.com>
1115
1116         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1117
1118 2015-02-10  Pedro Alves  <palves@redhat.com>
1119             Tom Tromey  <tromey@redhat.com>
1120
1121         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1122         microblaze_and, microblaze_xor.
1123         * microblaze-opc.h (opcodes): Adjust.
1124
1125 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
1126
1127         * Makefile.am: Add FT32 files.
1128         * configure.ac: Handle FT32.
1129         * disassemble.c (disassembler): Call print_insn_ft32.
1130         * ft32-dis.c: New file.
1131         * ft32-opc.c: New file.
1132         * Makefile.in: Regenerate.
1133         * configure: Regenerate.
1134         * po/POTFILES.in: Regenerate.
1135
1136 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1137
1138         * nds32-asm.c (keyword_sr): Add new system registers.
1139
1140 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1141
1142         * s390-dis.c (s390_extract_operand): Support vector register
1143         operands.
1144         (s390_print_insn_with_opcode): Support new operands types and add
1145         new handling of optional operands.
1146         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1147         and include opcode/s390.h instead.
1148         (struct op_struct): New field `flags'.
1149         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1150         (dumpTable): Dump flags.
1151         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
1152         string.
1153         * s390-opc.c: Add new operands types, instruction formats, and
1154         instruction masks.
1155         (s390_opformats): Add new formats for .insn.
1156         * s390-opc.txt: Add new instructions.
1157
1158 2015-01-01  Alan Modra  <amodra@gmail.com>
1159
1160         Update year range in copyright notice of all files.
1161
1162 For older changes see ChangeLog-2014
1163 \f
1164 Copyright (C) 2015 Free Software Foundation, Inc.
1165
1166 Copying and distribution of this file, with or without modification,
1167 are permitted in any medium without royalty provided the copyright
1168 notice and this notice are preserved.
1169
1170 Local Variables:
1171 mode: change-log
1172 left-margin: 8
1173 fill-column: 74
1174 version-control: never
1175 End: