opcodes/ChangeLog

   1 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-opc.tbl: Remove CheckRegSize from movq.
   4         * i386-tbl.h: Regenerated.
   5
   6 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         * i386-opc.tbl: Remove CheckRegSize from instructions with
   9         0, 1 or fixed operands.
  10         * i386-tbl.h: Regenerated.
  11
  12 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  13
  14         * i386-gen.c (opcode_modifiers): Add CheckRegSize.
  15
  16         * i386-opc.h (CheckRegSize): New.
  17         (i386_opcode_modifier): Add checkregsize.
  18
  19         * i386-opc.tbl: Add CheckRegSize to instructions which
  20         require register size check.
  21         * i386-tbl.h: Regenerated.
  22
  23 2010-10-12  Andreas Schwab  <schwab@linux-m68k.org>
  24
  25         * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
  26
  27 2010-10-11  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  28
  29         * s390-opc.c: Make the instruction masks for the load/store on
  30         condition instructions to cover the condition code mask as well.
  31         * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
  32
  33 2010-10-11  Jan Kratochvil  <jan.kratochvil@redhat.com>
  34             Jiang Jilin  <freephp@gmail.com>
  35
  36         * Makefile.am (libopcodes_a_SOURCES): New as empty.
  37         * Makefile.in: Regenerate.
  38
  39 2010-10-09  Matt Rice  <ratmice@gmail.com>
  40
  41         * fr30-desc.h: Regenerate.
  42         * frv-desc.h: Regenerate.
  43         * ip2k-desc.h: Regenerate.
  44         * iq2000-desc.h: Regenerate.
  45         * lm32-desc.h: Regenerate.
  46         * m32c-desc.h: Regenerate.
  47         * m32r-desc.h: Regenerate.
  48         * mep-desc.h: Regenerate.
  49         * mep-opc.c: Regenerate.
  50         * mt-desc.h: Regenerate.
  51         * openrisc-desc.h: Regenerate.
  52         * xc16x-desc.h: Regenerate.
  53         * xstormy16-desc.h: Regenerate.
  54
  55 2010-10-08  Pierre Muller  <muller@ics.u-strasbg.fr>
  56
  57         Fix build with -DDEBUG=7
  58         * frv-opc.c: Regenerate.
  59         * or32-dis.c (DEBUG): Don't redefine.
  60         (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
  61         Adapt DEBUG code to some type changes throughout.
  62         * or32-opc.c (or32_extract): Likewise.
  63
  64 2010-10-07  Bernd Schmidt  <bernds@codesourcery.com>
  65
  66         * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
  67         in SPKERNEL instructions.
  68
  69 2010-10-02  H.J. Lu  <hongjiu.lu@intel.com>
  70
  71         PR binutils/12076
  72         * i386-dis.c (RMAL): Remove duplicate.
  73
  74 2010-09-30  Pierre Muller  <muller@ics.u-strasbg.fr>
  75
  76         * s390-mkopc.c (main): Exit with error 1 if sscanf fails
  77         to parse all 6 parameters.
  78
  79 2010-09-28  Pierre Muller  <muller@ics.u-strasbg.fr>
  80
  81         * s390-mkopc.c (main): Change description array size to 80.
  82         Add maximum length of 79 to description parsing.
  83
  84 2010-09-27  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
  85
  86         * configure: Regenerate.
  87
  88 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  89
  90         * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
  91         (main): Recognize the new CPU string.
  92         * s390-opc.c: Add new instruction formats and masks.
  93         * s390-opc.txt: Add new z196 instructions.
  94
  95 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  96
  97         * s390-dis.c (print_insn_s390): Pick instruction with most
  98         specific mask.
  99         * s390-opc.c: Add unused bits to the insn mask.
 100         * s390-opc.txt: Reorder some instructions to prefer more recent
 101         versions.
 102
 103 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
 104
 105         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
 106         correction to unaligned PCs while printing comment.
 107
 108 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 109
 110         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
 111         (thumb32_opcodes): Likewise.
 112         (banked_regname): New function.
 113         (print_insn_arm): Add Virtualization Extensions support.
 114         (print_insn_thumb32): Likewise.
 115
 116 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 117
 118         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
 119         ARM state.
 120
 121 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 122
 123         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
 124         (thumb32_opcodes): Likewise.
 125
 126 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 127
 128         * arm-dis.c (arm_opcodes): Add support for pldw.
 129         (thumb32_opcodes): Likewise.
 130
 131 2010-09-22  Robin Getz  <robin.getz@analog.com>
 132
 133         * bfin-dis.c (fmtconst): Cast address to 32bits.
 134
 135 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 136
 137         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
 138
 139 2010-09-22  Robin Getz  <robin.getz@analog.com>
 140
 141         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
 142         Reject P6/P7 to TESTSET.
 143         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
 144         SP onto the stack.
 145         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
 146         P/D fields match all the time.
 147         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
 148         are 0 for accumulator compares.
 149         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
 150         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
 151         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
 152         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 153         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 154         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
 155         insns.
 156         (decode_dagMODim_0): Verify br field for IREG ops.
 157         (decode_LDST_0): Reject preg load into same preg.
 158         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
 159         (print_insn_bfin): Likewise.
 160
 161 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 162
 163         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
 164
 165 2010-09-22  Robin Getz  <robin.getz@analog.com>
 166
 167         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
 168
 169 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 170
 171         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
 172
 173 2010-09-22  Robin Getz  <robin.getz@analog.com>
 174
 175         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
 176         register values greater than 8.
 177         (IS_RESERVEDREG, allreg, mostreg): New helpers.
 178         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
 179         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
 180         (decode_CC2dreg_0): Check valid CC register number.
 181
 182 2010-09-22  Robin Getz  <robin.getz@analog.com>
 183
 184         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
 185
 186 2010-09-22  Robin Getz  <robin.getz@analog.com>
 187
 188         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
 189         (reg_names): Likewise.
 190         (decode_statbits): Likewise; while reformatting to make manageable.
 191
 192 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 193
 194         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
 195         (decode_pseudoOChar_0): New function.
 196         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
 197
 198 2010-09-22  Robin Getz  <robin.getz@analog.com>
 199
 200         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
 201         LSHIFT instead of SHIFT.
 202
 203 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 204
 205         * bfin-dis.c (constant_formats): Constify the whole structure.
 206         (fmtconst): Add const to return value.
 207         (reg_names): Mark const.
 208         (decode_multfunc): Mark s0/s1 as const.
 209         (decode_macfunc): Mark a/sop as const.
 210
 211 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 212
 213         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 214
 215 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 216
 217         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 218         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 219
 220 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 221
 222         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 223         dlx_insn_type array.
 224
 225 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 226
 227         PR binutils/11960
 228         * i386-dis.c (sIv): New.
 229         (dis386): Replace Iq with sIv on "pushT".
 230         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 231         (x86_64_table): Replace {T|}/{P|} with P.
 232         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 233         (OP_sI): Update v_mode.  Remove w_mode.
 234
 235 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 236
 237         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 238         on E500 and E500MC.
 239
 240 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 241
 242         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 243         prefetchw.
 244
 245 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 246
 247         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 248         to processor flags for PENTIUMPRO processors and later.
 249         * i386-opc.h (enum): Add CpuNop.
 250         (i386_cpu_flags): Add cpunop bit.
 251         * i386-opc.tbl: Change nop cpu_flags.
 252         * i386-init.h: Regenerated.
 253         * i386-tbl.h: Likewise.
 254
 255 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 256
 257         * i386-opc.h (enum): Fix typos in comments.
 258
 259 2010-08-06  Alan Modra  <amodra@gmail.com>
 260
 261         * disassemble.c: Formatting.
 262         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 263
 264 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 265
 266         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 267         * i386-tbl.h: Regenerated.
 268
 269 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 270
 271         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 272
 273         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 274         * i386-tbl.h: Regenerated.
 275
 276 2010-07-29  DJ Delorie  <dj@redhat.com>
 277
 278         * rx-decode.opc (SRR): New.
 279         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 280         r0,r0) and NOP3 (max r0,r0) special cases.
 281         * rx-decode.c: Regenerate.
 282
 283 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 284
 285         * i386-dis.c: Add 0F to VEX opcode enums.
 286
 287 2010-07-27  DJ Delorie  <dj@redhat.com>
 288
 289         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 290         (rx_decode_opcode): Likewise.
 291         * rx-decode.c: Regenerate.
 292
 293 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 294             Ina Pandit  <ina.pandit@kpitcummins.com>
 295
 296         * v850-dis.c (v850_sreg_names): Updated structure for system
 297         registers.
 298         (float_cc_names): new structure for condition codes.
 299         (print_value): Update the function that prints value.
 300         (get_operand_value): New function to get the operand value.
 301         (disassemble): Updated to handle the disassembly of instructions.
 302         (print_insn_v850): Updated function to print instruction for different
 303         families.
 304         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 305         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 306         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 307         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 308         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 309         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 310         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 311         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 312         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 313         (v850_operands): Update with the relocation name. Also update
 314         the instructions with specific set of processors.
 315
 316 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 317
 318         * arm-dis.c (print_insn_arm): Add cases for printing more
 319         symbolic operands.
 320         (print_insn_thumb32): Likewise.
 321
 322 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 323
 324         * mips-dis.c (print_insn_mips): Correct branch instruction type
 325         determination.
 326
 327 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 328
 329         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 330         type and delay slot determination.
 331         (print_insn_mips16): Extend branch instruction type and delay
 332         slot determination to cover all instructions.
 333         * mips16-opc.c (BR): Remove macro.
 334         (UBR, CBR): New macros.
 335         (mips16_opcodes): Update branch annotation for "b", "beqz",
 336         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 337         and "jrc".
 338
 339 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 340
 341         AVX Programming Reference (June, 2010)
 342         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 343         * i386-opc.tbl: Likewise.
 344         * i386-tbl.h: Regenerated.
 345
 346 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 347
 348         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 349
 350 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 351
 352         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 353         ppc_cpu_t before inverting.
 354         (ppc_parse_cpu): Likewise.
 355         (print_insn_powerpc): Likewise.
 356
 357 2010-07-03  Alan Modra  <amodra@gmail.com>
 358
 359         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 360         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 361         (PPC64, MFDEC2): Update.
 362         (NON32, NO371): Define.
 363         (powerpc_opcode): Update to not use old opcode flags, and avoid
 364         -m601 duplicates.
 365
 366 2010-07-03  DJ Delorie  <dj@delorie.com>
 367
 368         * m32c-ibld.c: Regenerate.
 369
 370 2010-07-03  Alan Modra  <amodra@gmail.com>
 371
 372         * ppc-opc.c (PWR2COM): Define.
 373         (PPCPWR2): Add PPC_OPCODE_COMMON.
 374         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 375         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 376         "rac" from -mcom.
 377
 378 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 379
 380         AVX Programming Reference (June, 2010)
 381         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 382         (PREFIX_0FAE_REG_1): Likewise.
 383         (PREFIX_0FAE_REG_2): Likewise.
 384         (PREFIX_0FAE_REG_3): Likewise.
 385         (PREFIX_VEX_3813): Likewise.
 386         (PREFIX_VEX_3A1D): Likewise.
 387         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 388         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 389         PREFIX_VEX_3A1D.
 390         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 391         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 392         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 393
 394         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 395         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 396         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 397
 398         * i386-opc.h (CpuXsaveopt): New.
 399         (CpuFSGSBase): Likewise.
 400         (CpuRdRnd): Likewise.
 401         (CpuF16C): Likewise.
 402         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 403         cpuf16c.
 404
 405         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 406         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 407         * i386-init.h: Regenerated.
 408         * i386-tbl.h: Likewise.
 409
 410 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 411
 412         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 413         and mtocrf on EFS.
 414
 415 2010-06-29  Alan Modra  <amodra@gmail.com>
 416
 417         * maxq-dis.c: Delete file.
 418         * Makefile.am: Remove references to maxq.
 419         * configure.in: Likewise.
 420         * disassemble.c: Likewise.
 421         * Makefile.in: Regenerate.
 422         * configure: Regenerate.
 423         * po/POTFILES.in: Regenerate.
 424
 425 2010-06-29  Alan Modra  <amodra@gmail.com>
 426
 427         * mep-dis.c: Regenerate.
 428
 429 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 430
 431         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 432
 433 2010-06-27  Alan Modra  <amodra@gmail.com>
 434
 435         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 436         (decodeInstr): Likewise.
 437         * dlx-dis.c (print_insn_dlx): Likewise.
 438         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 439         * maxq-dis.c (check_move, print_insn): Likewise.
 440         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 441         * msp430-dis.c (msp430_branchinstr): Likewise.
 442         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 443         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 444         * sparc-dis.c (print_insn_sparc): Likewise.
 445         * fr30-asm.c: Regenerate.
 446         * frv-asm.c: Regenerate.
 447         * ip2k-asm.c: Regenerate.
 448         * iq2000-asm.c: Regenerate.
 449         * lm32-asm.c: Regenerate.
 450         * m32c-asm.c: Regenerate.
 451         * m32r-asm.c: Regenerate.
 452         * mep-asm.c: Regenerate.
 453         * mt-asm.c: Regenerate.
 454         * openrisc-asm.c: Regenerate.
 455         * xc16x-asm.c: Regenerate.
 456         * xstormy16-asm.c: Regenerate.
 457
 458 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 459
 460         PR gas/11673
 461         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 462
 463 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 464
 465         PR binutils/11676
 466         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 467
 468 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 469
 470         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 471         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 472         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 473         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 474         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 475         Treat lwsync as msync on e500.
 476
 477 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 478
 479         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 480
 481 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 482
 483         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 484         constants is the same on 32-bit and 64-bit hosts.
 485
 486 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 487
 488         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 489         .short directives so that they can be reassembled.
 490
 491 2010-05-26  Catherine Moore <clm@codesourcery.com>
 492             David Ung  <davidu@mips.com>
 493
 494         * mips-opc.c: Change membership to I1 for instructions ssnop and
 495         ehb.
 496
 497 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 498
 499         * i386-dis.c (sib): New.
 500         (get_sib): Likewise.
 501         (print_insn): Call get_sib.
 502         OP_E_memory): Use sib.
 503
 504 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 505
 506         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 507         * mips-opc.c (I16): Remove.
 508         (mips_builtin_op): Reclassify jalx.
 509
 510 2010-05-19  Alan Modra  <amodra@gmail.com>
 511
 512         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 513         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 514
 515 2010-05-13  Alan Modra  <amodra@gmail.com>
 516
 517         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 518
 519 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 520
 521         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 522         format.
 523         (print_insn_thumb16): Add support for new %W format.
 524
 525 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 526
 527         * Makefile.in: Regenerate with automake 1.11.1.
 528         * aclocal.m4: Ditto.
 529
 530 2010-05-05  Nick Clifton  <nickc@redhat.com>
 531
 532         * po/es.po: Updated Spanish translation.
 533
 534 2010-04-22  Nick Clifton  <nickc@redhat.com>
 535
 536         * po/opcodes.pot: Updated by the Translation project.
 537         * po/vi.po: Updated Vietnamese translation.
 538
 539 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 540
 541         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 542         bits in opcode.
 543
 544 2010-04-09  Nick Clifton  <nickc@redhat.com>
 545
 546         * i386-dis.c (print_insn): Remove unused variable op.
 547         (OP_sI): Remove unused variable mask.
 548
 549 2010-04-07  Alan Modra  <amodra@gmail.com>
 550
 551         * configure: Regenerate.
 552
 553 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 554
 555         * ppc-opc.c (RBOPT): New define.
 556         ("dccci"): Enable for PPCA2.  Make operands optional.
 557         ("iccci"): Likewise.  Do not deprecate for PPC476.
 558
 559 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 560
 561         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 562
 563 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 564
 565         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 566         * Makefile.in: Regenerate.
 567         * configure.in (bfd_tic6x_arch): New.
 568         * configure: Regenerate.
 569         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 570         (disassembler): Handle TI C6X.
 571         * tic6x-dis.c: New.
 572
 573 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 574
 575         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 576
 577 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 578
 579         * dis-buf.c (buffer_read_memory): Give error for reading just
 580         before the start of memory.
 581
 582 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 583             Quentin Neill <quentin.neill@amd.com>
 584
 585         * i386-dis.c (OP_LWP_I): Removed.
 586         (reg_table): Do not use OP_LWP_I, use Iq.
 587         (OP_LWPCB_E): Remove use of names16.
 588         (OP_LWP_E): Same.
 589         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 590         should not set the Vex.length bit.
 591         * i386-tbl.h: Regenerated.
 592
 593 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 594
 595         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 596
 597 2010-02-24  Nick Clifton  <nickc@redhat.com>
 598
 599         PR binutils/6773
 600         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 601         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 602         (thumb32_opcodes): Likewise.
 603
 604 2010-02-15  Nick Clifton  <nickc@redhat.com>
 605
 606         * po/vi.po: Updated Vietnamese translation.
 607
 608 2010-02-12  Doug Evans  <dje@sebabeach.org>
 609
 610         * lm32-opinst.c: Regenerate.
 611
 612 2010-02-11  Doug Evans  <dje@sebabeach.org>
 613
 614         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 615         (print_address): Delete CGEN_PRINT_ADDRESS.
 616         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 617         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 618         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 619         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 620
 621         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 622         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 623         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 624         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 625         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 626         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 627         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 628         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 629         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 630         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 631         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 632         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 633
 634 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 635
 636         * i386-dis.c: Update copyright.
 637         * i386-gen.c: Likewise.
 638         * i386-opc.h: Likewise.
 639         * i386-opc.tbl: Likewise.
 640
 641 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 642             Sebastian Pop  <sebastian.pop@amd.com>
 643
 644         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 645         function to handle 5th imm8 operand.
 646         (PREFIX_VEX_3A48): Added.
 647         (PREFIX_VEX_3A49): Added.
 648         (VEX_W_3A48_P_2): Added.
 649         (VEX_W_3A49_P_2): Added.
 650         (prefix table): Added entries for PREFIX_VEX_3A48
 651         and PREFIX_VEX_3A49.
 652         (vex table): Added entries for VEX_W_3A48_P_2 and
 653         and VEX_W_3A49_P_2.
 654         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 655         for Vec_Imm4 operands.
 656         * i386-opc.h (enum): Added Vec_Imm4.
 657         (i386_operand_type): Added vec_imm4.
 658         * i386-opc.tbl: Add entries for vpermilp[ds].
 659         * i386-init.h: Regenerated.
 660         * i386-tbl.h: Regenerated.
 661
 662 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 663
 664         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 665         and "pwr7".  Move "a2" into alphabetical order.
 666
 667 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 668
 669         * ppc-dis.c (ppc_opts): Add titan entry.
 670         * ppc-opc.c (TITAN, MULHW): Define.
 671         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 672
 673 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 674
 675         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 676         to CPU_BDVER1_FLAGS
 677         * i386-init.h: Regenerated.
 678
 679 2010-02-03  Anthony Green  <green@moxielogic.com>
 680
 681         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 682         0x0f, and make 0x00 an illegal instruction.
 683
 684 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 685
 686         * opcodes/arm-dis.c (struct arm_private_data): New.
 687         (print_insn_coprocessor, print_insn_arm): Update to use struct
 688         arm_private_data.
 689         (is_mapping_symbol, get_map_sym_type): New functions.
 690         (get_sym_code_type): Check the symbol's section.  Do not check
 691         mapping symbols.
 692         (print_insn): Default to disassembling ARM mode code.  Check
 693         for mapping symbols separately from other symbols.  Use
 694         struct arm_private_data.
 695
 696 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 697
 698         * i386-dis.c (EXVexWdqScalar): New.
 699         (vex_scalar_w_dq_mode): Likewise.
 700         (prefix_table): Update entries for PREFIX_VEX_3899,
 701         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 702         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 703         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 704         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 705         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 706         (OP_EX): Likewise.
 707
 708 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 709
 710         * i386-dis.c (XMScalar): New.
 711         (EXdScalar): Likewise.
 712         (EXqScalar): Likewise.
 713         (EXqScalarS): Likewise.
 714         (VexScalar): Likewise.
 715         (EXdVexScalarS): Likewise.
 716         (EXqVexScalarS): Likewise.
 717         (XMVexScalar): Likewise.
 718         (scalar_mode): Likewise.
 719         (d_scalar_mode): Likewise.
 720         (d_scalar_swap_mode): Likewise.
 721         (q_scalar_mode): Likewise.
 722         (q_scalar_swap_mode): Likewise.
 723         (vex_scalar_mode): Likewise.
 724         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 725         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 726         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 727         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 728         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 729         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 730         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 731         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 732         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 733         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 734         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 735         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 736         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 737         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 738         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 739         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 740         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 741         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 742         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 743         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 744         q_scalar_mode, q_scalar_swap_mode.
 745         (OP_XMM): Handle scalar_mode.
 746         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 747         and q_scalar_swap_mode.
 748         (OP_VEX): Handle vex_scalar_mode.
 749
 750 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 751
 752         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 753
 754 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 755
 756         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 757
 758 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 759
 760         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 761
 762 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 763
 764         * i386-dis.c (Bad_Opcode): New.
 765         (bad_opcode): Likewise.
 766         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 767         (dis386_twobyte): Likewise.
 768         (reg_table): Likewise.
 769         (prefix_table): Likewise.
 770         (x86_64_table): Likewise.
 771         (vex_len_table): Likewise.
 772         (vex_w_table): Likewise.
 773         (mod_table): Likewise.
 774         (rm_table): Likewise.
 775         (float_reg): Likewise.
 776         (reg_table): Remove trailing "(bad)" entries.
 777         (prefix_table): Likewise.
 778         (x86_64_table): Likewise.
 779         (vex_len_table): Likewise.
 780         (vex_w_table): Likewise.
 781         (mod_table): Likewise.
 782         (rm_table): Likewise.
 783         (get_valid_dis386): Handle bytemode 0.
 784
 785 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 786
 787         * i386-opc.h (VEXScalar): New.
 788
 789         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 790         instructions.
 791         * i386-tbl.h: Regenerated.
 792
 793 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 794
 795         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 796
 797         * i386-opc.tbl: Add xsave64 and xrstor64.
 798         * i386-tbl.h: Regenerated.
 799
 800 2010-01-20  Nick Clifton  <nickc@redhat.com>
 801
 802         PR 11170
 803         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 804         based post-indexed addressing.
 805
 806 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 807
 808         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 809         * i386-tbl.h: Regenerated.
 810
 811 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 812
 813         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 814         comments.
 815
 816 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 817
 818         * i386-dis.c (names_mm): New.
 819         (intel_names_mm): Likewise.
 820         (att_names_mm): Likewise.
 821         (names_xmm): Likewise.
 822         (intel_names_xmm): Likewise.
 823         (att_names_xmm): Likewise.
 824         (names_ymm): Likewise.
 825         (intel_names_ymm): Likewise.
 826         (att_names_ymm): Likewise.
 827         (print_insn): Set names_mm, names_xmm and names_ymm.
 828         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 829         (OP_XMM): Likewise.
 830         (OP_EM): Likewise.
 831         (OP_EMC): Likewise.
 832         (OP_MXC): Likewise.
 833         (OP_EX): Likewise.
 834         (XMM_Fixup): Likewise.
 835         (OP_VEX): Likewise.
 836         (OP_EX_VexReg): Likewise.
 837         (OP_Vex_2src): Likewise.
 838         (OP_Vex_2src_1): Likewise.
 839         (OP_Vex_2src_2): Likewise.
 840         (OP_REG_VexI4): Likewise.
 841
 842 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 843
 844         * i386-dis.c (print_insn): Update comments.
 845
 846 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 847
 848         * i386-dis.c (rex_original): Removed.
 849         (ckprefix): Remove rex_original.
 850         (print_insn): Update comments.
 851
 852 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 853
 854         * Makefile.in: Regenerate.
 855         * configure: Regenerate.
 856
 857 2010-01-07  Doug Evans  <dje@sebabeach.org>
 858
 859         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 860         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 861         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 862         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 863         * xstormy16-ibld.c: Regenerate.
 864
 865 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 866
 867         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 868         * i386-init.h: Regenerated.
 869
 870 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 871
 872         * arm-dis.c (print_insn): Fixed search for next symbol and data
 873         dumping condition, and the initial mapping symbol state.
 874
 875 2010-01-05  Doug Evans  <dje@sebabeach.org>
 876
 877         * cgen-ibld.in: #include "cgen/basic-modes.h".
 878         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 879         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 880         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 881         * xstormy16-ibld.c: Regenerate.
 882
 883 2010-01-04  Nick Clifton  <nickc@redhat.com>
 884
 885         PR 11123
 886         * arm-dis.c (print_insn_coprocessor): Initialise value.
 887
 888 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 889
 890         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 891
 892 2010-01-02  Doug Evans  <dje@sebabeach.org>
 893
 894         * cgen-asm.in: Update copyright year.
 895         * cgen-dis.in: Update copyright year.
 896         * cgen-ibld.in: Update copyright year.
 897         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 898         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 899         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 900         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 901         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 902         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 903         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 904         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 905         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 906         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 907         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 908         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 909         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 910         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 911         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 912         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 913         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 914         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 915         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 916         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 917         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 918
 919 For older changes see ChangeLog-2009
 920 \f
 921 Local Variables:
 922 mode: change-log
 923 left-margin: 8
 924 fill-column: 74
 925 version-control: never
 926 End: