opcodes/ChangeLog

   1 2018-09-14  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (crc32): Fold byte and word forms.
   4         * i386-tbl.h: Re-generate.
   5
   6 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
   9         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
  10         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
  11         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
  12         * i386-tbl.h: Regenerated.
  13
  14 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  15
  16         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
  17         meaningless.
  18         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
  19         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
  20         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
  21         * i386-tbl.h: Re-generate.
  22
  23 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
  26         AVX512_4VNNIW insns.
  27         * i386-tbl.h: Re-generate.
  28
  29 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  30
  31         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
  32         meaningless.
  33         * i386-tbl.h: Re-generate.
  34
  35 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  36
  37         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
  38         meaningless.
  39         * i386-tbl.h: Re-generate.
  40
  41 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
  44         meaningless.
  45         * i386-tbl.h: Re-generate.
  46
  47 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  48
  49         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
  50         meaningless.
  51         * i386-tbl.h: Re-generate.
  52
  53 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  54
  55         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
  56         meaningless.
  57         * i386-tbl.h: Re-generate.
  58
  59 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
  62         * i386-tbl.h: Re-generate.
  63
  64 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
  67         * i386-tbl.h: Re-generate.
  68
  69 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  70
  71         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
  72         meaningless.
  73         * i386-tbl.h: Re-generate.
  74
  75 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  76
  77         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
  78         meaningless.
  79         * i386-tbl.h: Re-generate.
  80
  81 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  82
  83         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
  84         * i386-tbl.h: Re-generate.
  85
  86 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  87
  88         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
  89         * i386-tbl.h: Re-generate.
  90
  91 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
  94         * i386-tbl.h: Re-generate.
  95
  96 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
  99         meaningless.
 100         * i386-tbl.h: Re-generate.
 101
 102 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 105         meaningless.
 106         * i386-tbl.h: Re-generate.
 107
 108 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 111         meaningless.
 112         * i386-tbl.h: Re-generate.
 113
 114 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 115
 116         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 117         * i386-tbl.h: Re-generate.
 118
 119 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 120
 121         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 122         * i386-tbl.h: Re-generate.
 123
 124 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 125
 126         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 127         * i386-tbl.h: Re-generate.
 128
 129 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 130
 131         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 132         (vpbroadcastw, rdpid): Drop NoRex64.
 133         * i386-tbl.h: Re-generate.
 134
 135 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 138         store templates, adding D.
 139         * i386-tbl.h: Re-generate.
 140
 141 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 142
 143         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 144         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 145         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 146         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 147         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 148         Fold load and store templates where possible, adding D. Drop
 149         IgnoreSize where it was pointlessly present. Drop redundant
 150         *word.
 151         * i386-tbl.h: Re-generate.
 152
 153 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 154
 155         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 156         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 157         (intel_operand_size): Handle v_bndmk_mode.
 158         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 159
 160 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 161
 162         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 163
 164 2018-08-31  Kito Cheng  <kito@andestech.com>
 165
 166         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 167         compressed floating point instructions.
 168
 169 2018-08-30  Kito Cheng  <kito@andestech.com>
 170
 171         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 172         riscv_opcode.xlen_requirement.
 173         * riscv-opc.c (riscv_opcodes): Update for struct change.
 174
 175 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 176
 177         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 178         psr (PWRPSR) instruction.
 179
 180 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 181
 182         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 183
 184 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 185
 186         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 187
 188 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 189
 190         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 191         loongson3a as an alias of gs464 for compatibility.
 192         * mips-opc.c (mips_opcodes): Change Comments.
 193
 194 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 195
 196         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 197         option.
 198         (print_mips_disassembler_options): Document -M loongson-ext.
 199         * mips-opc.c (LEXT2): New macro.
 200         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 201
 202 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 203
 204          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 205          descriptors.
 206          (parse_mips_ase_option): Handle -M loongson-ext option.
 207          (print_mips_disassembler_options): Document -M loongson-ext.
 208          * mips-opc.c (IL3A): Delete.
 209          * mips-opc.c (LEXT): New macro.
 210          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 211          instructions.
 212
 213 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 214
 215         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 216         descriptors.
 217         (parse_mips_ase_option): Handle -M loongson-cam option.
 218         (print_mips_disassembler_options): Document -M loongson-cam.
 219         * mips-opc.c (LCAM): New macro.
 220         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 221         instructions.
 222
 223 2018-08-21  Alan Modra  <amodra@gmail.com>
 224
 225         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 226         (skip_optional_operands): Count optional operands, and update
 227         ppc_optional_operand_value call.
 228         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 229         (extract_vlensi): Likewise.
 230         (extract_fxm): Return default value for missing optional operand.
 231         (extract_ls, extract_raq, extract_tbr): Likewise.
 232         (insert_sxl, extract_sxl): New functions.
 233         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 234         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 235         flag and extra entry.
 236         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 237         extract_sxl.
 238
 239 2018-08-20  Alan Modra  <amodra@gmail.com>
 240
 241         * sh-opc.h (MASK): Simplify.
 242
 243 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 244
 245         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 246         BM_RESERVED0 or BM_RESERVED1
 247         (bm_rel_decode, bm_n_bytes): Ditto.
 248
 249 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 250
 251         * s12z.h: Delete.
 252
 253 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 254
 255         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 256         address with the addr32 prefix and without base nor index
 257         registers.
 258
 259 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 260
 261         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 262         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 263         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 264         (cpu_flags): Add CpuCMOV and CpuFXSR.
 265         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 266         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 267         * i386-init.h: Regenerated.
 268         * i386-tbl.h: Likewise.
 269
 270 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 271
 272         * arc-regs.h: Update auxiliary registers.
 273
 274 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 275
 276         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 277         (RegIP, RegIZ): Define.
 278         * i386-reg.tbl: Adjust comments.
 279         (rip): Use Qword instead of BaseIndex. Use RegIP.
 280         (eip): Use Dword instead of BaseIndex. Use RegIP.
 281         (riz): Add Qword. Use RegIZ.
 282         (eiz): Add Dword. Use RegIZ.
 283         * i386-tbl.h: Re-generate.
 284
 285 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 288         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 289         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 290         * i386-tbl.h: Re-generate.
 291
 292 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-gen.c (operand_types): Remove Mem field.
 295         * i386-opc.h (union i386_operand_type): Remove mem field.
 296         * i386-init.h, i386-tbl.h: Re-generate.
 297
 298 2018-08-01  Alan Modra  <amodra@gmail.com>
 299
 300         * po/POTFILES.in: Regenerate.
 301
 302 2018-07-31  Nick Clifton  <nickc@redhat.com>
 303
 304         * po/sv.po: Updated Swedish translation.
 305
 306 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 309         * i386-init.h, i386-tbl.h: Re-generate.
 310
 311 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 312
 313         * i386-opc.h (ZEROING_MASKING) Rename to ...
 314         (DYNAMIC_MASKING): ... this. Adjust comment.
 315         * i386-opc.tbl (MaskingMorZ): Define.
 316         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 317         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 318         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 319         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 320         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 321         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 322         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 323         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 324         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 325
 326 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-opc.tbl: Use element rather than vector size for AVX512*
 329         scatter/gather insns.
 330         * i386-tbl.h: Re-generate.
 331
 332 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 333
 334         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 335         (cpu_flags): Drop CpuVREX.
 336         * i386-opc.h (CpuVREX): Delete.
 337         (union i386_cpu_flags): Remove cpuvrex.
 338         * i386-init.h, i386-tbl.h: Re-generate.
 339
 340 2018-07-30  Jim Wilson  <jimw@sifive.com>
 341
 342         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 343         fields.
 344         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 345
 346 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 347
 348         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 349         * Makefile.in: Regenerated.
 350         * configure.ac: Add C-SKY.
 351         * configure: Regenerated.
 352         * csky-dis.c: New file.
 353         * csky-opc.h: New file.
 354         * disassemble.c (ARCH_csky): Define.
 355         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 356         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 357
 358 2018-07-27  Alan Modra  <amodra@gmail.com>
 359
 360         * ppc-opc.c (insert_sprbat): Correct function parameter and
 361         return type.
 362         (extract_sprbat): Likewise, variable too.
 363
 364 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 365             Alan Modra  <amodra@gmail.com>
 366
 367         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 368         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 369         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 370         support disjointed BAT.
 371         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 372         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 373         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 374
 375 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 376             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 377
 378         * i386-gen.c (adjust_broadcast_modifier): New function.
 379         (process_i386_opcode_modifier): Add an argument for operands.
 380         Adjust the Broadcast value based on operands.
 381         (output_i386_opcode): Pass operand_types to
 382         process_i386_opcode_modifier.
 383         (process_i386_opcodes): Pass NULL as operands to
 384         process_i386_opcode_modifier.
 385         * i386-opc.h (BYTE_BROADCAST): New.
 386         (WORD_BROADCAST): Likewise.
 387         (DWORD_BROADCAST): Likewise.
 388         (QWORD_BROADCAST): Likewise.
 389         (i386_opcode_modifier): Expand broadcast to 3 bits.
 390         * i386-tbl.h: Regenerated.
 391
 392 2018-07-24  Alan Modra  <amodra@gmail.com>
 393
 394         PR 23430
 395         * or1k-desc.h: Regenerate.
 396
 397 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 398
 399         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 400         vcvtusi2ss, and vcvtusi2sd.
 401         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 402         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 403         * i386-tbl.h: Re-generate.
 404
 405 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 406
 407         * arc-opc.c (extract_w6): Fix extending the sign.
 408
 409 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 410
 411         * arc-tbl.h (vewt): Allow it for ARC EM family.
 412
 413 2018-07-23  Alan Modra  <amodra@gmail.com>
 414
 415         PR 23419
 416         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 417         opcode variants for mtspr/mfspr encodings.
 418
 419 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 420             Maciej W. Rozycki  <macro@mips.com>
 421
 422         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 423         loongson3a descriptors.
 424         (parse_mips_ase_option): Handle -M loongson-mmi option.
 425         (print_mips_disassembler_options): Document -M loongson-mmi.
 426         * mips-opc.c (LMMI): New macro.
 427         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 428         instructions.
 429
 430 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 431
 432         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 433         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 434         IgnoreSize and [XYZ]MMword where applicable.
 435         * i386-tbl.h: Re-generate.
 436
 437 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 438
 439         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 440         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 441         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 442         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 443         * i386-tbl.h: Re-generate.
 444
 445 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 446
 447         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 448         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 449         VPCLMULQDQ templates into their respective AVX512VL counterparts
 450         where possible, using Disp8ShiftVL and CheckRegSize instead of
 451         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 452         * i386-tbl.h: Re-generate.
 453
 454 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 455
 456         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 457         AVX512VL counterparts where possible, using Disp8ShiftVL and
 458         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 459         IgnoreSize) as appropriate.
 460         * i386-tbl.h: Re-generate.
 461
 462 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 463
 464         * i386-opc.tbl: Fold AVX512BW templates into their respective
 465         AVX512VL counterparts where possible, using Disp8ShiftVL and
 466         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 467         IgnoreSize) as appropriate.
 468         * i386-tbl.h: Re-generate.
 469
 470 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-opc.tbl: Fold AVX512CD templates into their respective
 473         AVX512VL counterparts where possible, using Disp8ShiftVL and
 474         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 475         IgnoreSize) as appropriate.
 476         * i386-tbl.h: Re-generate.
 477
 478 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 479
 480         * i386-opc.h (DISP8_SHIFT_VL): New.
 481         * i386-opc.tbl (Disp8ShiftVL):  Define.
 482         (various): Fold AVX512VL templates into their respective
 483         AVX512F counterparts where possible, using Disp8ShiftVL and
 484         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 485         IgnoreSize) as appropriate.
 486         * i386-tbl.h: Re-generate.
 487
 488 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 489
 490         * Makefile.am: Change dependencies and rule for
 491         $(srcdir)/i386-init.h.
 492         * Makefile.in: Re-generate.
 493         * i386-gen.c (process_i386_opcodes): New local variable
 494         "marker". Drop opening of input file. Recognize marker and line
 495         number directives.
 496         * i386-opc.tbl (OPCODE_I386_H): Define.
 497         (i386-opc.h): Include it.
 498         (None): Undefine.
 499
 500 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 501
 502         PR gas/23418
 503         * i386-opc.h (Byte): Update comments.
 504         (Word): Likewise.
 505         (Dword): Likewise.
 506         (Fword): Likewise.
 507         (Qword): Likewise.
 508         (Tbyte): Likewise.
 509         (Xmmword): Likewise.
 510         (Ymmword): Likewise.
 511         (Zmmword): Likewise.
 512         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 513         vcvttps2uqq.
 514         * i386-tbl.h: Regenerated.
 515
 516 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 517
 518         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 519         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 520         * aarch64-asm-2.c: Regenerate.
 521         * aarch64-dis-2.c: Regenerate.
 522         * aarch64-opc-2.c: Regenerate.
 523
 524 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 525
 526         PR binutils/23192
 527         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 528         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 529         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 530         sqdmulh, sqrdmulh): Use Em16.
 531
 532 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 533
 534         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 535         csdb together with them.
 536         (thumb32_opcodes): Likewise.
 537
 538 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 541         requiring 32-bit registers as operands 2 and 3. Improve
 542         comments.
 543         (mwait, mwaitx): Fold templates. Improve comments.
 544         OPERAND_TYPE_INOUTPORTREG.
 545         * i386-tbl.h: Re-generate.
 546
 547 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 548
 549         * i386-gen.c (operand_type_init): Remove
 550         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 551         OPERAND_TYPE_INOUTPORTREG.
 552         * i386-init.h: Re-generate.
 553
 554 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 555
 556         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 557         (wrssq, wrussq): Add Qword.
 558         * i386-tbl.h: Re-generate.
 559
 560 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 561
 562         * i386-opc.h: Rename OTMax to OTNum.
 563         (OTNumOfUints): Adjust calculation.
 564         (OTUnused): Directly alias to OTNum.
 565
 566 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 567
 568         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 569         `reg_xys'.
 570         (lea_reg_xys): Likewise.
 571         (print_insn_loop_primitive): Rename `reg' local variable to
 572         `reg_dxy'.
 573
 574 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 575
 576         PR binutils/23242
 577         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 578
 579 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 580
 581         PR binutils/23369
 582         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 583         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 584
 585 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 586
 587         PR tdep/8282
 588         * mips-dis.c (mips_option_arg_t): New enumeration.
 589         (mips_options): New variable.
 590         (disassembler_options_mips): New function.
 591         (print_mips_disassembler_options): Reimplement in terms of
 592         `disassembler_options_mips'.
 593         * arm-dis.c (disassembler_options_arm): Adapt to using the
 594         `disasm_options_and_args_t' structure.
 595         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 596         * s390-dis.c (disassembler_options_s390): Likewise.
 597
 598 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 599
 600         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 601         expected result.
 602         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 603         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 604         * testsuite/ld-arm/tls-longplt.d: Likewise.
 605
 606 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 607
 608         PR binutils/23192
 609         * aarch64-asm-2.c: Regenerate.
 610         * aarch64-dis-2.c: Likewise.
 611         * aarch64-opc-2.c: Likewise.
 612         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 613         * aarch64-opc.c (operand_general_constraint_met_p,
 614         aarch64_print_operand): Likewise.
 615         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 616         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 617         fmlal2, fmlsl2.
 618         (AARCH64_OPERANDS): Add Em2.
 619
 620 2018-06-26  Nick Clifton  <nickc@redhat.com>
 621
 622         * po/uk.po: Updated Ukranian translation.
 623         * po/de.po: Updated German translation.
 624         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 625
 626 2018-06-26  Nick Clifton  <nickc@redhat.com>
 627
 628         * nfp-dis.c: Fix spelling mistake.
 629
 630 2018-06-24  Nick Clifton  <nickc@redhat.com>
 631
 632         * configure: Regenerate.
 633         * po/opcodes.pot: Regenerate.
 634
 635 2018-06-24  Nick Clifton  <nickc@redhat.com>
 636
 637         2.31 branch created.
 638
 639 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 640
 641         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 642         * aarch64-asm-2.c: Regenerate.
 643         * aarch64-dis-2.c: Likewise.
 644
 645 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 646
 647         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 648         `-M ginv' option description.
 649
 650 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 651
 652         PR gas/23305
 653         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 654         la and lla.
 655
 656 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 657
 658         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 659         * configure.ac: Remove AC_PREREQ.
 660         * Makefile.in: Re-generate.
 661         * aclocal.m4: Re-generate.
 662         * configure: Re-generate.
 663
 664 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 665
 666         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 667         mips64r6 descriptors.
 668         (parse_mips_ase_option): Handle -Mginv option.
 669         (print_mips_disassembler_options): Document -Mginv.
 670         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 671         (GINV): New macro.
 672         (mips_opcodes): Define ginvi and ginvt.
 673
 674 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 675             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 676
 677         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 678         * mips-opc.c (CRC, CRC64): New macros.
 679         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 680         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 681         crc32cd for CRC64.
 682
 683 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 684
 685         PR 20319
 686         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 687         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 688
 689 2018-06-06  Alan Modra  <amodra@gmail.com>
 690
 691         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 692         setjmp.  Move init for some other vars later too.
 693
 694 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 695
 696         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 697         (dis_private): Add new fields for property section tracking.
 698         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 699         (xtensa_instruction_fits): New functions.
 700         (fetch_data): Bump minimal fetch size to 4.
 701         (print_insn_xtensa): Make struct dis_private static.
 702         Load and prepare property table on section change.
 703         Don't disassemble literals. Don't disassemble instructions that
 704         cross property table boundaries.
 705
 706 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 707
 708         * configure: Regenerated.
 709
 710 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 711
 712         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 713         * i386-tbl.h: Re-generate.
 714
 715 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 716
 717         * i386-opc.tbl (sldt, str): Add NoRex64.
 718         * i386-tbl.h: Re-generate.
 719
 720 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 721
 722         * i386-opc.tbl (invpcid): Add Oword.
 723         * i386-tbl.h: Re-generate.
 724
 725 2018-06-01  Alan Modra  <amodra@gmail.com>
 726
 727         * sysdep.h (_bfd_error_handler): Don't declare.
 728         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 729         * rl78-decode.opc: Likewise.
 730         * msp430-decode.c: Regenerate.
 731         * rl78-decode.c: Regenerate.
 732
 733 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 734
 735         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 736         * i386-init.h : Regenerated.
 737
 738 2018-05-25  Alan Modra  <amodra@gmail.com>
 739
 740         * Makefile.in: Regenerate.
 741         * po/POTFILES.in: Regenerate.
 742
 743 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 744
 745         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 746         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 747         (insert_bab, extract_bab, insert_btab, extract_btab,
 748         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 749         (BAT, BBA VBA RBS XB6S): Delete macros.
 750         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 751         (BB, BD, RBX, XC6): Update for new macros.
 752         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 753         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 754         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 755         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 756
 757 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 758
 759         * Makefile.am: Add support for s12z architecture.
 760         * configure.ac: Likewise.
 761         * disassemble.c: Likewise.
 762         * disassemble.h: Likewise.
 763         * Makefile.in: Regenerate.
 764         * configure: Regenerate.
 765         * s12z-dis.c: New file.
 766         * s12z.h: New file.
 767
 768 2018-05-18  Alan Modra  <amodra@gmail.com>
 769
 770         * nfp-dis.c: Don't #include libbfd.h.
 771         (init_nfp3200_priv): Use bfd_get_section_contents.
 772         (nit_nfp6000_mecsr_sec): Likewise.
 773
 774 2018-05-17  Nick Clifton  <nickc@redhat.com>
 775
 776         * po/zh_CN.po: Updated simplified Chinese translation.
 777
 778 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 779
 780         PR binutils/23109
 781         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 782         * aarch64-dis-2.c: Regenerate.
 783
 784 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 785
 786         PR binutils/21446
 787         * aarch64-asm.c (opintl.h): Include.
 788         (aarch64_ins_sysreg): Enforce read/write constraints.
 789         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 790         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 791         (F_REG_READ, F_REG_WRITE): New.
 792         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 793         AARCH64_OPND_SYSREG.
 794         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 795         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 796         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 797         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 798         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 799         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 800         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 801         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 802         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 803         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 804         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 805         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 806         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 807         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 808         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 809         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 810         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 811
 812 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 813
 814         PR binutils/21446
 815         * aarch64-dis.c (no_notes: New.
 816         (parse_aarch64_dis_option): Support notes.
 817         (aarch64_decode_insn, print_operands): Likewise.
 818         (print_aarch64_disassembler_options): Document notes.
 819         * aarch64-opc.c (aarch64_print_operand): Support notes.
 820
 821 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 822
 823         PR binutils/21446
 824         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 825         and take error struct.
 826         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 827         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 828         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 829         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 830         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 831         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 832         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 833         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 834         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 835         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 836         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 837         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 838         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 839         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 840         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 841         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 842         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 843         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 844         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 845         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 846         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 847         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 848         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 849         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 850         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 851         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 852         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 853         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 854         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 855         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 856         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 857         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 858         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 859         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 860         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 861         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 862         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 863         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 864         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 865         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 866         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 867         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 868         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 869         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 870         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 871         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 872         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 873         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 874         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 875         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 876         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 877         (determine_disassembling_preference, aarch64_decode_insn,
 878         print_insn_aarch64_word, print_insn_data): Take errors struct.
 879         (print_insn_aarch64): Use errors.
 880         * aarch64-asm-2.c: Regenerate.
 881         * aarch64-dis-2.c: Regenerate.
 882         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 883         boolean in aarch64_insert_operan.
 884         (print_operand_extractor): Likewise.
 885         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 886
 887 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 888
 889         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 890
 891 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 892
 893         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 894
 895 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 896
 897         * cr16-opc.c (cr16_instruction): Comment typo fix.
 898         * hppa-dis.c (print_insn_hppa): Likewise.
 899
 900 2018-05-08  Jim Wilson  <jimw@sifive.com>
 901
 902         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 903         (match_c_slli64, match_srxi_as_c_srxi): New.
 904         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 905         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 906         <c.slli, c.srli, c.srai>: Use match_s_slli.
 907         <c.slli64, c.srli64, c.srai64>: New.
 908
 909 2018-05-08  Alan Modra  <amodra@gmail.com>
 910
 911         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 912         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 913         partition opcode space for index lookup.
 914
 915 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 916
 917         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 918         <insn_length>: ...with this.  Update usage.
 919         Remove duplicate call to *info->memory_error_func.
 920
 921 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 922             H.J. Lu  <hongjiu.lu@intel.com>
 923
 924         * i386-dis.c (Gva): New.
 925         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 926         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 927         (prefix_table): New instructions (see prefix above).
 928         (mod_table): New instructions (see prefix above).
 929         (OP_G): Handle va_mode.
 930         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 931         CPU_MOVDIR64B_FLAGS.
 932         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 933         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 934         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 935         * i386-opc.tbl: Add movidir{i,64b}.
 936         * i386-init.h: Regenerated.
 937         * i386-tbl.h: Likewise.
 938
 939 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 940
 941         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 942         AddrPrefixOpReg.
 943         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 944         (AddrPrefixOpReg): This.
 945         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 946         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 947
 948 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 949
 950         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 951         (vle_num_opcodes): Likewise.
 952         (spe2_num_opcodes): Likewise.
 953         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 954         initialization loop.
 955         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 956         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 957         only once.
 958
 959 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 960
 961         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 962
 963 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 964
 965         Makefile.am: Added nfp-dis.c.
 966         configure.ac: Added bfd_nfp_arch.
 967         disassemble.h: Added print_insn_nfp prototype.
 968         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 969         nfp-dis.c: New, for NFP support.
 970         po/POTFILES.in: Added nfp-dis.c to the list.
 971         Makefile.in: Regenerate.
 972         configure: Regenerate.
 973
 974 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 975
 976         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 977         templates into their base ones.
 978         * i386-tlb.h: Re-generate.
 979
 980 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 981
 982         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 983         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 984         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 985         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 986         * i386-init.h: Re-generate.
 987
 988 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 989
 990         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 991         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 992         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 993         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 994         comment.
 995         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 996         and CpuRegMask.
 997         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 998         CpuRegMask: Delete.
 999         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1000         cpuregzmm, and cpuregmask.
1001         * i386-init.h: Re-generate.
1002         * i386-tbl.h: Re-generate.
1003
1004 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1005
1006         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1007         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1008         * i386-init.h: Re-generate.
1009
1010 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1011
1012         * i386-gen.c (VexImmExt): Delete.
1013         * i386-opc.h (VexImmExt, veximmext): Delete.
1014         * i386-opc.tbl: Drop all VexImmExt uses.
1015         * i386-tlb.h: Re-generate.
1016
1017 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1018
1019         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1020         register-only forms.
1021         * i386-tlb.h: Re-generate.
1022
1023 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1024
1025         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1026
1027 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1028
1029         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1030         PREFIX_0F1C.
1031         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1032         (cpu_flags): Add CpuCLDEMOTE.
1033         * i386-init.h: Regenerate.
1034         * i386-opc.h (enum): Add CpuCLDEMOTE,
1035         (i386_cpu_flags): Add cpucldemote.
1036         * i386-opc.tbl: Add cldemote.
1037         * i386-tbl.h: Regenerate.
1038
1039 2018-04-16  Alan Modra  <amodra@gmail.com>
1040
1041         * Makefile.am: Remove sh5 and sh64 support.
1042         * configure.ac: Likewise.
1043         * disassemble.c: Likewise.
1044         * disassemble.h: Likewise.
1045         * sh-dis.c: Likewise.
1046         * sh64-dis.c: Delete.
1047         * sh64-opc.c: Delete.
1048         * sh64-opc.h: Delete.
1049         * Makefile.in: Regenerate.
1050         * configure: Regenerate.
1051         * po/POTFILES.in: Regenerate.
1052
1053 2018-04-16  Alan Modra  <amodra@gmail.com>
1054
1055         * Makefile.am: Remove w65 support.
1056         * configure.ac: Likewise.
1057         * disassemble.c: Likewise.
1058         * disassemble.h: Likewise.
1059         * w65-dis.c: Delete.
1060         * w65-opc.h: Delete.
1061         * Makefile.in: Regenerate.
1062         * configure: Regenerate.
1063         * po/POTFILES.in: Regenerate.
1064
1065 2018-04-16  Alan Modra  <amodra@gmail.com>
1066
1067         * configure.ac: Remove we32k support.
1068         * configure: Regenerate.
1069
1070 2018-04-16  Alan Modra  <amodra@gmail.com>
1071
1072         * Makefile.am: Remove m88k support.
1073         * configure.ac: Likewise.
1074         * disassemble.c: Likewise.
1075         * disassemble.h: Likewise.
1076         * m88k-dis.c: Delete.
1077         * Makefile.in: Regenerate.
1078         * configure: Regenerate.
1079         * po/POTFILES.in: Regenerate.
1080
1081 2018-04-16  Alan Modra  <amodra@gmail.com>
1082
1083         * Makefile.am: Remove i370 support.
1084         * configure.ac: Likewise.
1085         * disassemble.c: Likewise.
1086         * disassemble.h: Likewise.
1087         * i370-dis.c: Delete.
1088         * i370-opc.c: Delete.
1089         * Makefile.in: Regenerate.
1090         * configure: Regenerate.
1091         * po/POTFILES.in: Regenerate.
1092
1093 2018-04-16  Alan Modra  <amodra@gmail.com>
1094
1095         * Makefile.am: Remove h8500 support.
1096         * configure.ac: Likewise.
1097         * disassemble.c: Likewise.
1098         * disassemble.h: Likewise.
1099         * h8500-dis.c: Delete.
1100         * h8500-opc.h: Delete.
1101         * Makefile.in: Regenerate.
1102         * configure: Regenerate.
1103         * po/POTFILES.in: Regenerate.
1104
1105 2018-04-16  Alan Modra  <amodra@gmail.com>
1106
1107         * configure.ac: Remove tahoe support.
1108         * configure: Regenerate.
1109
1110 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1111
1112         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1113         umwait.
1114         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1115         64-bit mode.
1116         * i386-tbl.h: Regenerated.
1117
1118 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1119
1120         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1121         PREFIX_MOD_1_0FAE_REG_6.
1122         (va_mode): New.
1123         (OP_E_register): Use va_mode.
1124         * i386-dis-evex.h (prefix_table):
1125         New instructions (see prefixes above).
1126         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1127         (cpu_flags): Likewise.
1128         * i386-opc.h (enum): Likewise.
1129         (i386_cpu_flags): Likewise.
1130         * i386-opc.tbl: Add umonitor, umwait, tpause.
1131         * i386-init.h: Regenerate.
1132         * i386-tbl.h: Likewise.
1133
1134 2018-04-11  Alan Modra  <amodra@gmail.com>
1135
1136         * opcodes/i860-dis.c: Delete.
1137         * opcodes/i960-dis.c: Delete.
1138         * Makefile.am: Remove i860 and i960 support.
1139         * configure.ac: Likewise.
1140         * disassemble.c: Likewise.
1141         * disassemble.h: Likewise.
1142         * Makefile.in: Regenerate.
1143         * configure: Regenerate.
1144         * po/POTFILES.in: Regenerate.
1145
1146 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1147
1148         PR binutils/23025
1149         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1150         to 0.
1151         (print_insn): Clear vex instead of vex.evex.
1152
1153 2018-04-04  Nick Clifton  <nickc@redhat.com>
1154
1155         * po/es.po: Updated Spanish translation.
1156
1157 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1158
1159         * i386-gen.c (opcode_modifiers): Delete VecESize.
1160         * i386-opc.h (VecESize): Delete.
1161         (struct i386_opcode_modifier): Delete vecesize.
1162         * i386-opc.tbl: Drop VecESize.
1163         * i386-tlb.h: Re-generate.
1164
1165 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1166
1167         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1168         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1169         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1170         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1171         * i386-tlb.h: Re-generate.
1172
1173 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1174
1175         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1176         Fold AVX512 forms
1177         * i386-tlb.h: Re-generate.
1178
1179 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1180
1181         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1182         (vex_len_table): Drop Y for vcvt*2si.
1183         (putop): Replace plain 'Y' handling by abort().
1184
1185 2018-03-28  Nick Clifton  <nickc@redhat.com>
1186
1187         PR 22988
1188         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1189         instructions with only a base address register.
1190         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1191         handle AARHC64_OPND_SVE_ADDR_R.
1192         (aarch64_print_operand): Likewise.
1193         * aarch64-asm-2.c: Regenerate.
1194         * aarch64_dis-2.c: Regenerate.
1195         * aarch64-opc-2.c: Regenerate.
1196
1197 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1198
1199         * i386-opc.tbl: Drop VecESize from register only insn forms and
1200         memory forms not allowing broadcast.
1201         * i386-tlb.h: Re-generate.
1202
1203 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1204
1205         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1206         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1207         sha256*): Drop Disp<N>.
1208
1209 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1210
1211         * i386-dis.c (EbndS, bnd_swap_mode): New.
1212         (prefix_table): Use EbndS.
1213         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1214         * i386-opc.tbl (bndmov): Move misplaced Load.
1215         * i386-tlb.h: Re-generate.
1216
1217 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1218
1219         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1220         templates allowing memory operands and folded ones for register
1221         only flavors.
1222         * i386-tlb.h: Re-generate.
1223
1224 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1225
1226         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1227         256-bit templates. Drop redundant leftover Disp<N>.
1228         * i386-tlb.h: Re-generate.
1229
1230 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1231
1232         * riscv-opc.c (riscv_insn_types): New.
1233
1234 2018-03-13  Nick Clifton  <nickc@redhat.com>
1235
1236         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1237
1238 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1239
1240         * i386-opc.tbl: Add Optimize to clr.
1241         * i386-tbl.h: Regenerated.
1242
1243 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1244
1245         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1246         * i386-opc.h (OldGcc): Removed.
1247         (i386_opcode_modifier): Remove oldgcc.
1248         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1249         instructions for old (<= 2.8.1) versions of gcc.
1250         * i386-tbl.h: Regenerated.
1251
1252 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1253
1254         * i386-opc.h (EVEXDYN): New.
1255         * i386-opc.tbl: Fold various AVX512VL templates.
1256         * i386-tlb.h: Re-generate.
1257
1258 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1259
1260         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1261         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1262         vpexpandd, vpexpandq): Fold AFX512VF templates.
1263         * i386-tlb.h: Re-generate.
1264
1265 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1266
1267         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1268         Fold 128- and 256-bit VEX-encoded templates.
1269         * i386-tlb.h: Re-generate.
1270
1271 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1272
1273         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1274         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1275         vpexpandd, vpexpandq): Fold AVX512F templates.
1276         * i386-tlb.h: Re-generate.
1277
1278 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1279
1280         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1281         64-bit templates. Drop Disp<N>.
1282         * i386-tlb.h: Re-generate.
1283
1284 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1285
1286         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1287         and 256-bit templates.
1288         * i386-tlb.h: Re-generate.
1289
1290 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1291
1292         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1293         * i386-tlb.h: Re-generate.
1294
1295 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1296
1297         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1298         Drop NoAVX.
1299         * i386-tlb.h: Re-generate.
1300
1301 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1302
1303         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1304         * i386-tlb.h: Re-generate.
1305
1306 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1307
1308         * i386-gen.c (opcode_modifiers): Delete FloatD.
1309         * i386-opc.h (FloatD): Delete.
1310         (struct i386_opcode_modifier): Delete floatd.
1311         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1312         FloatD by D.
1313         * i386-tlb.h: Re-generate.
1314
1315 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1316
1317         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1318
1319 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1320
1321         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1322         * i386-tlb.h: Re-generate.
1323
1324 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1325
1326         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1327         forms.
1328         * i386-tlb.h: Re-generate.
1329
1330 2018-03-07  Alan Modra  <amodra@gmail.com>
1331
1332         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1333         bfd_arch_rs6000.
1334         * disassemble.h (print_insn_rs6000): Delete.
1335         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1336         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1337         (print_insn_rs6000): Delete.
1338
1339 2018-03-03  Alan Modra  <amodra@gmail.com>
1340
1341         * sysdep.h (opcodes_error_handler): Define.
1342         (_bfd_error_handler): Declare.
1343         * Makefile.am: Remove stray #.
1344         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1345         EDIT" comment.
1346         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1347         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1348         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1349         opcodes_error_handler to print errors.  Standardize error messages.
1350         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1351         and include opintl.h.
1352         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1353         * i386-gen.c: Standardize error messages.
1354         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1355         * Makefile.in: Regenerate.
1356         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1357         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1358         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1359         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1360         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1361         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1362         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1363         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1364         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1365         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1366         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1367         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1368         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1369
1370 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1371
1372         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1373         vpsub[bwdq] instructions.
1374         * i386-tbl.h: Regenerated.
1375
1376 2018-03-01  Alan Modra  <amodra@gmail.com>
1377
1378         * configure.ac (ALL_LINGUAS): Sort.
1379         * configure: Regenerate.
1380
1381 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1382
1383         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1384         macro by assignements.
1385
1386 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1387
1388         PR gas/22871
1389         * i386-gen.c (opcode_modifiers): Add Optimize.
1390         * i386-opc.h (Optimize): New enum.
1391         (i386_opcode_modifier): Add optimize.
1392         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1393         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1394         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1395         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1396         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1397         vpxord and vpxorq.
1398         * i386-tbl.h: Regenerated.
1399
1400 2018-02-26  Alan Modra  <amodra@gmail.com>
1401
1402         * crx-dis.c (getregliststring): Allocate a large enough buffer
1403         to silence false positive gcc8 warning.
1404
1405 2018-02-22  Shea Levy <shea@shealevy.com>
1406
1407         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1408
1409 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1410
1411         * i386-opc.tbl: Add {rex},
1412         * i386-tbl.h: Regenerated.
1413
1414 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1415
1416         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1417         (mips16_opcodes): Replace `M' with `m' for "restore".
1418
1419 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1420
1421         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1422
1423 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1424
1425         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1426         variable to `function_index'.
1427
1428 2018-02-13  Nick Clifton  <nickc@redhat.com>
1429
1430         PR 22823
1431         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1432         about truncation of printing.
1433
1434 2018-02-12  Henry Wong <henry@stuffedcow.net>
1435
1436         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1437
1438 2018-02-05  Nick Clifton  <nickc@redhat.com>
1439
1440         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1441
1442 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1443
1444         * i386-dis.c (enum): Add pconfig.
1445         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1446         (cpu_flags): Add CpuPCONFIG.
1447         * i386-opc.h (enum): Add CpuPCONFIG.
1448         (i386_cpu_flags): Add cpupconfig.
1449         * i386-opc.tbl: Add PCONFIG instruction.
1450         * i386-init.h: Regenerate.
1451         * i386-tbl.h: Likewise.
1452
1453 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1454
1455         * i386-dis.c (enum): Add PREFIX_0F09.
1456         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1457         (cpu_flags): Add CpuWBNOINVD.
1458         * i386-opc.h (enum): Add CpuWBNOINVD.
1459         (i386_cpu_flags): Add cpuwbnoinvd.
1460         * i386-opc.tbl: Add WBNOINVD instruction.
1461         * i386-init.h: Regenerate.
1462         * i386-tbl.h: Likewise.
1463
1464 2018-01-17  Jim Wilson  <jimw@sifive.com>
1465
1466         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1467
1468 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1469
1470         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1471         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1472         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1473         (cpu_flags): Add CpuIBT, CpuSHSTK.
1474         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1475         (i386_cpu_flags): Add cpuibt, cpushstk.
1476         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1477         * i386-init.h: Regenerate.
1478         * i386-tbl.h: Likewise.
1479
1480 2018-01-16  Nick Clifton  <nickc@redhat.com>
1481
1482         * po/pt_BR.po: Updated Brazilian Portugese translation.
1483         * po/de.po: Updated German translation.
1484
1485 2018-01-15  Jim Wilson  <jimw@sifive.com>
1486
1487         * riscv-opc.c (match_c_nop): New.
1488         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1489
1490 2018-01-15  Nick Clifton  <nickc@redhat.com>
1491
1492         * po/uk.po: Updated Ukranian translation.
1493
1494 2018-01-13  Nick Clifton  <nickc@redhat.com>
1495
1496         * po/opcodes.pot: Regenerated.
1497
1498 2018-01-13  Nick Clifton  <nickc@redhat.com>
1499
1500         * configure: Regenerate.
1501
1502 2018-01-13  Nick Clifton  <nickc@redhat.com>
1503
1504         2.30 branch created.
1505
1506 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1507
1508         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1509         * i386-tbl.h: Regenerate.
1510
1511 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1512
1513         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1514         * i386-tbl.h: Re-generate.
1515
1516 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1517
1518         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1519         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1520         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1521         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1522         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1523         Disp8MemShift of AVX512VL forms.
1524         * i386-tbl.h: Re-generate.
1525
1526 2018-01-09  Jim Wilson  <jimw@sifive.com>
1527
1528         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1529         then the hi_addr value is zero.
1530
1531 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1532
1533         * arm-dis.c (arm_opcodes): Add csdb.
1534         (thumb32_opcodes): Add csdb.
1535
1536 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1537
1538         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1539         * aarch64-asm-2.c: Regenerate.
1540         * aarch64-dis-2.c: Regenerate.
1541         * aarch64-opc-2.c: Regenerate.
1542
1543 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1544
1545         PR gas/22681
1546         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1547         Remove AVX512 vmovd with 64-bit operands.
1548         * i386-tbl.h: Regenerated.
1549
1550 2018-01-05  Jim Wilson  <jimw@sifive.com>
1551
1552         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1553         jalr.
1554
1555 2018-01-03  Alan Modra  <amodra@gmail.com>
1556
1557         Update year range in copyright notice of all files.
1558
1559 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1560
1561         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1562         and OPERAND_TYPE_REGZMM entries.
1563
1564 For older changes see ChangeLog-2017
1565 \f
1566 Copyright (C) 2018 Free Software Foundation, Inc.
1567
1568 Copying and distribution of this file, with or without modification,
1569 are permitted in any medium without royalty provided the copyright
1570 notice and this notice are preserved.
1571
1572 Local Variables:
1573 mode: change-log
1574 left-margin: 8
1575 fill-column: 74
1576 version-control: never
1577 End: