1 2018-11-06 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
4 (vpmaxub): Re-order attributes on AVX512BW flavor.
5 * i386-tbl.h: Re-generate.
7 2018-11-06 Jan Beulich <jbeulich@suse.com>
9 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
10 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
11 Vex=1 on AVX / AVX2 flavors.
12 (vpmaxub): Re-order attributes on AVX512BW flavor.
13 * i386-tbl.h: Re-generate.
15 2018-11-06 Jan Beulich <jbeulich@suse.com>
17 * i386-opc.tbl (VexW0, VexW1): New.
18 (vphadd*, vphsub*): Use VexW0 on XOP variants.
19 * i386-tbl.h: Re-generate.
21 2018-10-22 John Darrington <john@darrington.wattle.id.au>
23 * s12z-dis.c (decode_possible_symbol): Add fallback case.
26 2018-10-19 Tamar Christina <tamar.christina@arm.com>
28 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
29 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
30 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
32 2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
34 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
35 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
37 2018-10-10 Jan Beulich <jbeulich@suse.com>
39 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
41 * i386-opc.h (Size16, Size32, Size64): Delete.
43 (SIZE16, SIZE32, SIZE64): Define.
44 (struct i386_opcode_modifier): Drop size16, size32, and size64.
46 * i386-opc.tbl (Size16, Size32, Size64): Define.
47 * i386-tbl.h: Re-generate.
49 2018-10-09 Sudakshina Das <sudi.das@arm.com>
51 * aarch64-opc.c (operand_general_constraint_met_p): Add
52 SSBS in the check for one-bit immediate.
53 (aarch64_sys_regs): New entry for SSBS.
54 (aarch64_sys_reg_supported_p): New check for above.
55 (aarch64_pstatefields): New entry for SSBS.
56 (aarch64_pstatefield_supported_p): New check for above.
58 2018-10-09 Sudakshina Das <sudi.das@arm.com>
60 * aarch64-opc.c (aarch64_sys_regs): New entries for
61 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
62 (aarch64_sys_reg_supported_p): New checks for above.
64 2018-10-09 Sudakshina Das <sudi.das@arm.com>
66 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
67 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
68 with the hint immediate.
69 * aarch64-opc.c (aarch64_hint_options): New entries for
70 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
71 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
72 while checking for HINT_OPD_F_NOPRINT flag.
73 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
75 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
76 (aarch64_opcode_table): Add entry for BTI.
77 (AARCH64_OPERANDS): Add new description for BTI targets.
78 * aarch64-asm-2.c: Regenerate.
79 * aarch64-dis-2.c: Regenerate.
80 * aarch64-opc-2.c: Regenerate.
82 2018-10-09 Sudakshina Das <sudi.das@arm.com>
84 * aarch64-opc.c (aarch64_sys_regs): New entries for
86 (aarch64_sys_reg_supported_p): New check for above.
88 2018-10-09 Sudakshina Das <sudi.das@arm.com>
90 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
91 (aarch64_sys_ins_reg_supported_p): New check for above.
93 2018-10-09 Sudakshina Das <sudi.das@arm.com>
95 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
96 AARCH64_OPND_SYSREG_SR.
97 * aarch64-opc.c (aarch64_print_operand): Likewise.
98 (aarch64_sys_regs_sr): Define table.
99 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
100 AARCH64_FEATURE_PREDRES.
101 * aarch64-tbl.h (aarch64_feature_predres): New.
102 (PREDRES, PREDRES_INSN): New.
103 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
104 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
105 * aarch64-asm-2.c: Regenerate.
106 * aarch64-dis-2.c: Regenerate.
107 * aarch64-opc-2.c: Regenerate.
109 2018-10-09 Sudakshina Das <sudi.das@arm.com>
111 * aarch64-tbl.h (aarch64_feature_sb): New.
113 (aarch64_opcode_table): Add entry for sb.
114 * aarch64-asm-2.c: Regenerate.
115 * aarch64-dis-2.c: Regenerate.
116 * aarch64-opc-2.c: Regenerate.
118 2018-10-09 Sudakshina Das <sudi.das@arm.com>
120 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
121 (aarch64_feature_frintts): New.
122 (FLAGMANIP, FRINTTS): New.
123 (aarch64_opcode_table): Add entries for xaflag, axflag
124 and frint[32,64][x,z] instructions.
125 * aarch64-asm-2.c: Regenerate.
126 * aarch64-dis-2.c: Regenerate.
127 * aarch64-opc-2.c: Regenerate.
129 2018-10-09 Sudakshina Das <sudi.das@arm.com>
131 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
132 (ARMV8_5, V8_5_INSN): New.
134 2018-10-08 Tamar Christina <tamar.christina@arm.com>
136 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
138 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
140 * i386-dis.c (rm_table): Add enclv.
141 * i386-opc.tbl: Add enclv.
142 * i386-tbl.h: Regenerated.
144 2018-10-05 Sudakshina Das <sudi.das@arm.com>
146 * arm-dis.c (arm_opcodes): Add sb.
147 (thumb32_opcodes): Likewise.
149 2018-10-05 Richard Henderson <rth@twiddle.net>
150 Stafford Horne <shorne@gmail.com>
152 * or1k-desc.c: Regenerate.
153 * or1k-desc.h: Regenerate.
154 * or1k-opc.c: Regenerate.
155 * or1k-opc.h: Regenerate.
156 * or1k-opinst.c: Regenerate.
158 2018-10-05 Richard Henderson <rth@twiddle.net>
160 * or1k-asm.c: Regenerated.
161 * or1k-desc.c: Regenerated.
162 * or1k-desc.h: Regenerated.
163 * or1k-dis.c: Regenerated.
164 * or1k-ibld.c: Regenerated.
165 * or1k-opc.c: Regenerated.
166 * or1k-opc.h: Regenerated.
167 * or1k-opinst.c: Regenerated.
169 2018-10-05 Richard Henderson <rth@twiddle.net>
171 * or1k-asm.c: Regenerate.
173 2018-10-03 Tamar Christina <tamar.christina@arm.com>
175 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
176 * aarch64-dis.c (print_operands): Refactor to take notes.
177 (print_verifier_notes): New.
178 (print_aarch64_insn): Apply constraint verifier.
179 (print_insn_aarch64_word): Update call to print_aarch64_insn.
180 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
182 2018-10-03 Tamar Christina <tamar.christina@arm.com>
184 * aarch64-opc.c (init_insn_block): New.
185 (verify_constraints, aarch64_is_destructive_by_operands): New.
186 * aarch64-opc.h (verify_constraints): New.
188 2018-10-03 Tamar Christina <tamar.christina@arm.com>
190 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
191 * aarch64-opc.c (verify_ldpsw): Update arguments.
193 2018-10-03 Tamar Christina <tamar.christina@arm.com>
195 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
196 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
198 2018-10-03 Tamar Christina <tamar.christina@arm.com>
200 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
201 * aarch64-dis.c (insn_sequence): New.
203 2018-10-03 Tamar Christina <tamar.christina@arm.com>
205 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
206 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
207 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
208 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
211 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
213 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
215 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
216 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
217 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
218 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
219 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
220 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
221 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
223 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
225 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
227 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
229 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
230 are used when extracting signed fields and converting them to
231 potentially 64-bit types.
233 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
235 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
236 * Makefile.in: Re-generate.
237 * aclocal.m4: Re-generate.
238 * configure: Re-generate.
239 * configure.ac: Remove check for -Wno-missing-field-initializers.
240 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
241 (csky_v2_opcodes): Likewise.
243 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
245 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
247 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
249 * nds32-asm.c (operand_fields): Remove the unused fields.
250 (nds32_opcodes): Remove the unused instructions.
251 * nds32-dis.c (nds32_ex9_info): Removed.
252 (nds32_parse_opcode): Updated.
253 (print_insn_nds32): Likewise.
254 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
255 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
256 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
257 build_opcode_hash_table): New functions.
258 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
259 nds32_opcode_table): New.
260 (hw_ktabs): Declare it to a pointer rather than an array.
261 (build_hash_table): Removed.
262 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
263 SYN_ROPT and upadte HW_GPR and HW_INT.
264 * nds32-dis.c (keywords): Remove const.
265 (match_field): New function.
266 (nds32_parse_opcode): Updated.
267 * disassemble.c (disassemble_init_for_target):
268 Add disassemble_init_nds32.
269 * nds32-dis.c (eum map_type): New.
270 (nds32_private_data): Likewise.
271 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
272 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
273 (print_insn_nds32): Updated.
274 * nds32-asm.c (parse_aext_reg): Add new parameter.
275 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
278 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
279 (operand_fields): Add new fields.
280 (nds32_opcodes): Add new instructions.
281 (keyword_aridxi_mx): New keyword.
282 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
284 (ALU2_1, ALU2_2, ALU2_3): New macros.
285 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
287 2018-09-17 Kito Cheng <kito@andestech.com>
289 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
291 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
294 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
295 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
296 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
297 (EVEX_LEN_0F7E_P_1): Likewise.
298 (EVEX_LEN_0F7E_P_2): Likewise.
299 (EVEX_LEN_0FD6_P_2): Likewise.
300 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
301 (EVEX_LEN_TABLE): Likewise.
302 (EVEX_LEN_0F6E_P_2): New enum.
303 (EVEX_LEN_0F7E_P_1): Likewise.
304 (EVEX_LEN_0F7E_P_2): Likewise.
305 (EVEX_LEN_0FD6_P_2): Likewise.
306 (evex_len_table): New.
307 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
308 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
309 * i386-tbl.h: Regenerated.
311 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
314 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
315 VEX_LEN_0F7E_P_2 entries.
316 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
317 * i386-tbl.h: Regenerated.
319 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
321 * i386-dis.c (VZERO_Fixup): Removed.
323 (VEX_LEN_0F10_P_1): Likewise.
324 (VEX_LEN_0F10_P_3): Likewise.
325 (VEX_LEN_0F11_P_1): Likewise.
326 (VEX_LEN_0F11_P_3): Likewise.
327 (VEX_LEN_0F2E_P_0): Likewise.
328 (VEX_LEN_0F2E_P_2): Likewise.
329 (VEX_LEN_0F2F_P_0): Likewise.
330 (VEX_LEN_0F2F_P_2): Likewise.
331 (VEX_LEN_0F51_P_1): Likewise.
332 (VEX_LEN_0F51_P_3): Likewise.
333 (VEX_LEN_0F52_P_1): Likewise.
334 (VEX_LEN_0F53_P_1): Likewise.
335 (VEX_LEN_0F58_P_1): Likewise.
336 (VEX_LEN_0F58_P_3): Likewise.
337 (VEX_LEN_0F59_P_1): Likewise.
338 (VEX_LEN_0F59_P_3): Likewise.
339 (VEX_LEN_0F5A_P_1): Likewise.
340 (VEX_LEN_0F5A_P_3): Likewise.
341 (VEX_LEN_0F5C_P_1): Likewise.
342 (VEX_LEN_0F5C_P_3): Likewise.
343 (VEX_LEN_0F5D_P_1): Likewise.
344 (VEX_LEN_0F5D_P_3): Likewise.
345 (VEX_LEN_0F5E_P_1): Likewise.
346 (VEX_LEN_0F5E_P_3): Likewise.
347 (VEX_LEN_0F5F_P_1): Likewise.
348 (VEX_LEN_0F5F_P_3): Likewise.
349 (VEX_LEN_0FC2_P_1): Likewise.
350 (VEX_LEN_0FC2_P_3): Likewise.
351 (VEX_LEN_0F3A0A_P_2): Likewise.
352 (VEX_LEN_0F3A0B_P_2): Likewise.
353 (VEX_W_0F10_P_0): Likewise.
354 (VEX_W_0F10_P_1): Likewise.
355 (VEX_W_0F10_P_2): Likewise.
356 (VEX_W_0F10_P_3): Likewise.
357 (VEX_W_0F11_P_0): Likewise.
358 (VEX_W_0F11_P_1): Likewise.
359 (VEX_W_0F11_P_2): Likewise.
360 (VEX_W_0F11_P_3): Likewise.
361 (VEX_W_0F12_P_0_M_0): Likewise.
362 (VEX_W_0F12_P_0_M_1): Likewise.
363 (VEX_W_0F12_P_1): Likewise.
364 (VEX_W_0F12_P_2): Likewise.
365 (VEX_W_0F12_P_3): Likewise.
366 (VEX_W_0F13_M_0): Likewise.
367 (VEX_W_0F14): Likewise.
368 (VEX_W_0F15): Likewise.
369 (VEX_W_0F16_P_0_M_0): Likewise.
370 (VEX_W_0F16_P_0_M_1): Likewise.
371 (VEX_W_0F16_P_1): Likewise.
372 (VEX_W_0F16_P_2): Likewise.
373 (VEX_W_0F17_M_0): Likewise.
374 (VEX_W_0F28): Likewise.
375 (VEX_W_0F29): Likewise.
376 (VEX_W_0F2B_M_0): Likewise.
377 (VEX_W_0F2E_P_0): Likewise.
378 (VEX_W_0F2E_P_2): Likewise.
379 (VEX_W_0F2F_P_0): Likewise.
380 (VEX_W_0F2F_P_2): Likewise.
381 (VEX_W_0F50_M_0): Likewise.
382 (VEX_W_0F51_P_0): Likewise.
383 (VEX_W_0F51_P_1): Likewise.
384 (VEX_W_0F51_P_2): Likewise.
385 (VEX_W_0F51_P_3): Likewise.
386 (VEX_W_0F52_P_0): Likewise.
387 (VEX_W_0F52_P_1): Likewise.
388 (VEX_W_0F53_P_0): Likewise.
389 (VEX_W_0F53_P_1): Likewise.
390 (VEX_W_0F58_P_0): Likewise.
391 (VEX_W_0F58_P_1): Likewise.
392 (VEX_W_0F58_P_2): Likewise.
393 (VEX_W_0F58_P_3): Likewise.
394 (VEX_W_0F59_P_0): Likewise.
395 (VEX_W_0F59_P_1): Likewise.
396 (VEX_W_0F59_P_2): Likewise.
397 (VEX_W_0F59_P_3): Likewise.
398 (VEX_W_0F5A_P_0): Likewise.
399 (VEX_W_0F5A_P_1): Likewise.
400 (VEX_W_0F5A_P_3): Likewise.
401 (VEX_W_0F5B_P_0): Likewise.
402 (VEX_W_0F5B_P_1): Likewise.
403 (VEX_W_0F5B_P_2): Likewise.
404 (VEX_W_0F5C_P_0): Likewise.
405 (VEX_W_0F5C_P_1): Likewise.
406 (VEX_W_0F5C_P_2): Likewise.
407 (VEX_W_0F5C_P_3): Likewise.
408 (VEX_W_0F5D_P_0): Likewise.
409 (VEX_W_0F5D_P_1): Likewise.
410 (VEX_W_0F5D_P_2): Likewise.
411 (VEX_W_0F5D_P_3): Likewise.
412 (VEX_W_0F5E_P_0): Likewise.
413 (VEX_W_0F5E_P_1): Likewise.
414 (VEX_W_0F5E_P_2): Likewise.
415 (VEX_W_0F5E_P_3): Likewise.
416 (VEX_W_0F5F_P_0): Likewise.
417 (VEX_W_0F5F_P_1): Likewise.
418 (VEX_W_0F5F_P_2): Likewise.
419 (VEX_W_0F5F_P_3): Likewise.
420 (VEX_W_0F60_P_2): Likewise.
421 (VEX_W_0F61_P_2): Likewise.
422 (VEX_W_0F62_P_2): Likewise.
423 (VEX_W_0F63_P_2): Likewise.
424 (VEX_W_0F64_P_2): Likewise.
425 (VEX_W_0F65_P_2): Likewise.
426 (VEX_W_0F66_P_2): Likewise.
427 (VEX_W_0F67_P_2): Likewise.
428 (VEX_W_0F68_P_2): Likewise.
429 (VEX_W_0F69_P_2): Likewise.
430 (VEX_W_0F6A_P_2): Likewise.
431 (VEX_W_0F6B_P_2): Likewise.
432 (VEX_W_0F6C_P_2): Likewise.
433 (VEX_W_0F6D_P_2): Likewise.
434 (VEX_W_0F6F_P_1): Likewise.
435 (VEX_W_0F6F_P_2): Likewise.
436 (VEX_W_0F70_P_1): Likewise.
437 (VEX_W_0F70_P_2): Likewise.
438 (VEX_W_0F70_P_3): Likewise.
439 (VEX_W_0F71_R_2_P_2): Likewise.
440 (VEX_W_0F71_R_4_P_2): Likewise.
441 (VEX_W_0F71_R_6_P_2): Likewise.
442 (VEX_W_0F72_R_2_P_2): Likewise.
443 (VEX_W_0F72_R_4_P_2): Likewise.
444 (VEX_W_0F72_R_6_P_2): Likewise.
445 (VEX_W_0F73_R_2_P_2): Likewise.
446 (VEX_W_0F73_R_3_P_2): Likewise.
447 (VEX_W_0F73_R_6_P_2): Likewise.
448 (VEX_W_0F73_R_7_P_2): Likewise.
449 (VEX_W_0F74_P_2): Likewise.
450 (VEX_W_0F75_P_2): Likewise.
451 (VEX_W_0F76_P_2): Likewise.
452 (VEX_W_0F77_P_0): Likewise.
453 (VEX_W_0F7C_P_2): Likewise.
454 (VEX_W_0F7C_P_3): Likewise.
455 (VEX_W_0F7D_P_2): Likewise.
456 (VEX_W_0F7D_P_3): Likewise.
457 (VEX_W_0F7E_P_1): Likewise.
458 (VEX_W_0F7F_P_1): Likewise.
459 (VEX_W_0F7F_P_2): Likewise.
460 (VEX_W_0FAE_R_2_M_0): Likewise.
461 (VEX_W_0FAE_R_3_M_0): Likewise.
462 (VEX_W_0FC2_P_0): Likewise.
463 (VEX_W_0FC2_P_1): Likewise.
464 (VEX_W_0FC2_P_2): Likewise.
465 (VEX_W_0FC2_P_3): Likewise.
466 (VEX_W_0FD0_P_2): Likewise.
467 (VEX_W_0FD0_P_3): Likewise.
468 (VEX_W_0FD1_P_2): Likewise.
469 (VEX_W_0FD2_P_2): Likewise.
470 (VEX_W_0FD3_P_2): Likewise.
471 (VEX_W_0FD4_P_2): Likewise.
472 (VEX_W_0FD5_P_2): Likewise.
473 (VEX_W_0FD6_P_2): Likewise.
474 (VEX_W_0FD7_P_2_M_1): Likewise.
475 (VEX_W_0FD8_P_2): Likewise.
476 (VEX_W_0FD9_P_2): Likewise.
477 (VEX_W_0FDA_P_2): Likewise.
478 (VEX_W_0FDB_P_2): Likewise.
479 (VEX_W_0FDC_P_2): Likewise.
480 (VEX_W_0FDD_P_2): Likewise.
481 (VEX_W_0FDE_P_2): Likewise.
482 (VEX_W_0FDF_P_2): Likewise.
483 (VEX_W_0FE0_P_2): Likewise.
484 (VEX_W_0FE1_P_2): Likewise.
485 (VEX_W_0FE2_P_2): Likewise.
486 (VEX_W_0FE3_P_2): Likewise.
487 (VEX_W_0FE4_P_2): Likewise.
488 (VEX_W_0FE5_P_2): Likewise.
489 (VEX_W_0FE6_P_1): Likewise.
490 (VEX_W_0FE6_P_2): Likewise.
491 (VEX_W_0FE6_P_3): Likewise.
492 (VEX_W_0FE7_P_2_M_0): Likewise.
493 (VEX_W_0FE8_P_2): Likewise.
494 (VEX_W_0FE9_P_2): Likewise.
495 (VEX_W_0FEA_P_2): Likewise.
496 (VEX_W_0FEB_P_2): Likewise.
497 (VEX_W_0FEC_P_2): Likewise.
498 (VEX_W_0FED_P_2): Likewise.
499 (VEX_W_0FEE_P_2): Likewise.
500 (VEX_W_0FEF_P_2): Likewise.
501 (VEX_W_0FF0_P_3_M_0): Likewise.
502 (VEX_W_0FF1_P_2): Likewise.
503 (VEX_W_0FF2_P_2): Likewise.
504 (VEX_W_0FF3_P_2): Likewise.
505 (VEX_W_0FF4_P_2): Likewise.
506 (VEX_W_0FF5_P_2): Likewise.
507 (VEX_W_0FF6_P_2): Likewise.
508 (VEX_W_0FF7_P_2): Likewise.
509 (VEX_W_0FF8_P_2): Likewise.
510 (VEX_W_0FF9_P_2): Likewise.
511 (VEX_W_0FFA_P_2): Likewise.
512 (VEX_W_0FFB_P_2): Likewise.
513 (VEX_W_0FFC_P_2): Likewise.
514 (VEX_W_0FFD_P_2): Likewise.
515 (VEX_W_0FFE_P_2): Likewise.
516 (VEX_W_0F3800_P_2): Likewise.
517 (VEX_W_0F3801_P_2): Likewise.
518 (VEX_W_0F3802_P_2): Likewise.
519 (VEX_W_0F3803_P_2): Likewise.
520 (VEX_W_0F3804_P_2): Likewise.
521 (VEX_W_0F3805_P_2): Likewise.
522 (VEX_W_0F3806_P_2): Likewise.
523 (VEX_W_0F3807_P_2): Likewise.
524 (VEX_W_0F3808_P_2): Likewise.
525 (VEX_W_0F3809_P_2): Likewise.
526 (VEX_W_0F380A_P_2): Likewise.
527 (VEX_W_0F380B_P_2): Likewise.
528 (VEX_W_0F3817_P_2): Likewise.
529 (VEX_W_0F381C_P_2): Likewise.
530 (VEX_W_0F381D_P_2): Likewise.
531 (VEX_W_0F381E_P_2): Likewise.
532 (VEX_W_0F3820_P_2): Likewise.
533 (VEX_W_0F3821_P_2): Likewise.
534 (VEX_W_0F3822_P_2): Likewise.
535 (VEX_W_0F3823_P_2): Likewise.
536 (VEX_W_0F3824_P_2): Likewise.
537 (VEX_W_0F3825_P_2): Likewise.
538 (VEX_W_0F3828_P_2): Likewise.
539 (VEX_W_0F3829_P_2): Likewise.
540 (VEX_W_0F382A_P_2_M_0): Likewise.
541 (VEX_W_0F382B_P_2): Likewise.
542 (VEX_W_0F3830_P_2): Likewise.
543 (VEX_W_0F3831_P_2): Likewise.
544 (VEX_W_0F3832_P_2): Likewise.
545 (VEX_W_0F3833_P_2): Likewise.
546 (VEX_W_0F3834_P_2): Likewise.
547 (VEX_W_0F3835_P_2): Likewise.
548 (VEX_W_0F3837_P_2): Likewise.
549 (VEX_W_0F3838_P_2): Likewise.
550 (VEX_W_0F3839_P_2): Likewise.
551 (VEX_W_0F383A_P_2): Likewise.
552 (VEX_W_0F383B_P_2): Likewise.
553 (VEX_W_0F383C_P_2): Likewise.
554 (VEX_W_0F383D_P_2): Likewise.
555 (VEX_W_0F383E_P_2): Likewise.
556 (VEX_W_0F383F_P_2): Likewise.
557 (VEX_W_0F3840_P_2): Likewise.
558 (VEX_W_0F3841_P_2): Likewise.
559 (VEX_W_0F38DB_P_2): Likewise.
560 (VEX_W_0F3A08_P_2): Likewise.
561 (VEX_W_0F3A09_P_2): Likewise.
562 (VEX_W_0F3A0A_P_2): Likewise.
563 (VEX_W_0F3A0B_P_2): Likewise.
564 (VEX_W_0F3A0C_P_2): Likewise.
565 (VEX_W_0F3A0D_P_2): Likewise.
566 (VEX_W_0F3A0E_P_2): Likewise.
567 (VEX_W_0F3A0F_P_2): Likewise.
568 (VEX_W_0F3A21_P_2): Likewise.
569 (VEX_W_0F3A40_P_2): Likewise.
570 (VEX_W_0F3A41_P_2): Likewise.
571 (VEX_W_0F3A42_P_2): Likewise.
572 (VEX_W_0F3A62_P_2): Likewise.
573 (VEX_W_0F3A63_P_2): Likewise.
574 (VEX_W_0F3ADF_P_2): Likewise.
575 (VEX_LEN_0F77_P_0): New.
576 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
577 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
578 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
579 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
580 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
581 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
582 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
583 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
584 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
585 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
586 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
587 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
588 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
589 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
590 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
591 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
592 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
593 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
594 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
595 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
596 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
597 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
598 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
599 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
600 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
601 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
602 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
603 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
604 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
605 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
606 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
607 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
608 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
609 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
610 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
611 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
612 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
613 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
614 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
615 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
616 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
617 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
618 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
619 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
620 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
621 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
622 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
623 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
624 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
625 (vex_table): Update VEX 0F28 and 0F29 entries.
626 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
627 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
628 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
629 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
630 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
631 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
632 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
633 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
634 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
635 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
636 VEX_LEN_0F3A0B_P_2 entries.
637 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
638 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
639 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
640 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
641 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
642 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
643 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
644 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
645 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
646 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
647 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
648 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
649 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
650 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
651 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
652 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
653 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
654 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
655 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
656 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
657 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
658 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
659 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
660 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
661 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
662 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
663 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
664 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
665 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
666 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
667 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
668 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
669 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
670 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
671 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
672 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
673 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
674 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
675 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
676 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
677 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
678 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
679 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
680 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
681 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
682 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
683 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
684 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
685 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
686 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
687 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
688 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
689 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
690 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
691 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
692 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
693 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
694 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
695 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
696 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
697 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
698 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
699 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
700 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
701 VEX_W_0F3ADF_P_2 entries.
702 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
703 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
704 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
706 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
708 * i386-opc.tbl (VexWIG): New.
709 Replace VexW=3 with VexWIG.
711 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
713 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
714 * i386-tbl.h: Regenerated.
716 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
719 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
720 VEX_LEN_0FD6_P_2 entries.
721 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
722 * i386-tbl.h: Regenerated.
724 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
727 * i386-opc.h (VEXWIG): New.
728 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
729 * i386-tbl.h: Regenerated.
731 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
734 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
735 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
736 * i386-dis.c (EXxEVexR64): New.
737 (evex_rounding_64_mode): Likewise.
738 (OP_Rounding): Handle evex_rounding_64_mode.
740 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
743 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
744 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
745 * i386-dis.c (Edqa): New.
746 (dqa_mode): Likewise.
747 (intel_operand_size): Handle dqa_mode as m_mode.
748 (OP_E_register): Handle dqa_mode as dq_mode.
749 (OP_E_memory): Set shift for dqa_mode based on address_mode.
751 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
753 * i386-dis.c (OP_E_memory): Reformat.
755 2018-09-14 Jan Beulich <jbeulich@suse.com>
757 * i386-opc.tbl (crc32): Fold byte and word forms.
758 * i386-tbl.h: Re-generate.
760 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
762 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
763 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
764 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
765 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
766 * i386-tbl.h: Regenerated.
768 2018-09-13 Jan Beulich <jbeulich@suse.com>
770 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
772 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
773 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
774 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
775 * i386-tbl.h: Re-generate.
777 2018-09-13 Jan Beulich <jbeulich@suse.com>
779 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
781 * i386-tbl.h: Re-generate.
783 2018-09-13 Jan Beulich <jbeulich@suse.com>
785 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
787 * i386-tbl.h: Re-generate.
789 2018-09-13 Jan Beulich <jbeulich@suse.com>
791 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
793 * i386-tbl.h: Re-generate.
795 2018-09-13 Jan Beulich <jbeulich@suse.com>
797 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
799 * i386-tbl.h: Re-generate.
801 2018-09-13 Jan Beulich <jbeulich@suse.com>
803 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
805 * i386-tbl.h: Re-generate.
807 2018-09-13 Jan Beulich <jbeulich@suse.com>
809 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
811 * i386-tbl.h: Re-generate.
813 2018-09-13 Jan Beulich <jbeulich@suse.com>
815 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
816 * i386-tbl.h: Re-generate.
818 2018-09-13 Jan Beulich <jbeulich@suse.com>
820 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
821 * i386-tbl.h: Re-generate.
823 2018-09-13 Jan Beulich <jbeulich@suse.com>
825 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
827 * i386-tbl.h: Re-generate.
829 2018-09-13 Jan Beulich <jbeulich@suse.com>
831 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
833 * i386-tbl.h: Re-generate.
835 2018-09-13 Jan Beulich <jbeulich@suse.com>
837 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
838 * i386-tbl.h: Re-generate.
840 2018-09-13 Jan Beulich <jbeulich@suse.com>
842 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
843 * i386-tbl.h: Re-generate.
845 2018-09-13 Jan Beulich <jbeulich@suse.com>
847 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
848 * i386-tbl.h: Re-generate.
850 2018-09-13 Jan Beulich <jbeulich@suse.com>
852 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
854 * i386-tbl.h: Re-generate.
856 2018-09-13 Jan Beulich <jbeulich@suse.com>
858 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
860 * i386-tbl.h: Re-generate.
862 2018-09-13 Jan Beulich <jbeulich@suse.com>
864 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
866 * i386-tbl.h: Re-generate.
868 2018-09-13 Jan Beulich <jbeulich@suse.com>
870 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
871 * i386-tbl.h: Re-generate.
873 2018-09-13 Jan Beulich <jbeulich@suse.com>
875 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
876 * i386-tbl.h: Re-generate.
878 2018-09-13 Jan Beulich <jbeulich@suse.com>
880 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
881 * i386-tbl.h: Re-generate.
883 2018-09-13 Jan Beulich <jbeulich@suse.com>
885 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
886 (vpbroadcastw, rdpid): Drop NoRex64.
887 * i386-tbl.h: Re-generate.
889 2018-09-13 Jan Beulich <jbeulich@suse.com>
891 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
892 store templates, adding D.
893 * i386-tbl.h: Re-generate.
895 2018-09-13 Jan Beulich <jbeulich@suse.com>
897 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
898 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
899 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
900 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
901 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
902 Fold load and store templates where possible, adding D. Drop
903 IgnoreSize where it was pointlessly present. Drop redundant
905 * i386-tbl.h: Re-generate.
907 2018-09-13 Jan Beulich <jbeulich@suse.com>
909 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
910 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
911 (intel_operand_size): Handle v_bndmk_mode.
912 (OP_E_memory): Likewise. Produce (bad) when also riprel.
914 2018-09-08 John Darrington <john@darrington.wattle.id.au>
916 * disassemble.c (ARCH_s12z): Define if ARCH_all.
918 2018-08-31 Kito Cheng <kito@andestech.com>
920 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
921 compressed floating point instructions.
923 2018-08-30 Kito Cheng <kito@andestech.com>
925 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
926 riscv_opcode.xlen_requirement.
927 * riscv-opc.c (riscv_opcodes): Update for struct change.
929 2018-08-29 Martin Aberg <maberg@gaisler.com>
931 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
932 psr (PWRPSR) instruction.
934 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
936 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
938 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
940 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
942 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
944 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
945 loongson3a as an alias of gs464 for compatibility.
946 * mips-opc.c (mips_opcodes): Change Comments.
948 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
950 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
952 (print_mips_disassembler_options): Document -M loongson-ext.
953 * mips-opc.c (LEXT2): New macro.
954 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
956 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
958 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
960 (parse_mips_ase_option): Handle -M loongson-ext option.
961 (print_mips_disassembler_options): Document -M loongson-ext.
962 * mips-opc.c (IL3A): Delete.
963 * mips-opc.c (LEXT): New macro.
964 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
967 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
969 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
971 (parse_mips_ase_option): Handle -M loongson-cam option.
972 (print_mips_disassembler_options): Document -M loongson-cam.
973 * mips-opc.c (LCAM): New macro.
974 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
977 2018-08-21 Alan Modra <amodra@gmail.com>
979 * ppc-dis.c (operand_value_powerpc): Init "invalid".
980 (skip_optional_operands): Count optional operands, and update
981 ppc_optional_operand_value call.
982 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
983 (extract_vlensi): Likewise.
984 (extract_fxm): Return default value for missing optional operand.
985 (extract_ls, extract_raq, extract_tbr): Likewise.
986 (insert_sxl, extract_sxl): New functions.
987 (insert_esync, extract_esync): Remove Power9 handling and simplify.
988 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
989 flag and extra entry.
990 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
993 2018-08-20 Alan Modra <amodra@gmail.com>
995 * sh-opc.h (MASK): Simplify.
997 2018-08-18 John Darrington <john@darrington.wattle.id.au>
999 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1000 BM_RESERVED0 or BM_RESERVED1
1001 (bm_rel_decode, bm_n_bytes): Ditto.
1003 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1007 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1009 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1010 address with the addr32 prefix and without base nor index
1013 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1015 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1016 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1017 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1018 (cpu_flags): Add CpuCMOV and CpuFXSR.
1019 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1020 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1021 * i386-init.h: Regenerated.
1022 * i386-tbl.h: Likewise.
1024 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1026 * arc-regs.h: Update auxiliary registers.
1028 2018-08-06 Jan Beulich <jbeulich@suse.com>
1030 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1031 (RegIP, RegIZ): Define.
1032 * i386-reg.tbl: Adjust comments.
1033 (rip): Use Qword instead of BaseIndex. Use RegIP.
1034 (eip): Use Dword instead of BaseIndex. Use RegIP.
1035 (riz): Add Qword. Use RegIZ.
1036 (eiz): Add Dword. Use RegIZ.
1037 * i386-tbl.h: Re-generate.
1039 2018-08-03 Jan Beulich <jbeulich@suse.com>
1041 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1042 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1043 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1044 * i386-tbl.h: Re-generate.
1046 2018-08-03 Jan Beulich <jbeulich@suse.com>
1048 * i386-gen.c (operand_types): Remove Mem field.
1049 * i386-opc.h (union i386_operand_type): Remove mem field.
1050 * i386-init.h, i386-tbl.h: Re-generate.
1052 2018-08-01 Alan Modra <amodra@gmail.com>
1054 * po/POTFILES.in: Regenerate.
1056 2018-07-31 Nick Clifton <nickc@redhat.com>
1058 * po/sv.po: Updated Swedish translation.
1060 2018-07-31 Jan Beulich <jbeulich@suse.com>
1062 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1063 * i386-init.h, i386-tbl.h: Re-generate.
1065 2018-07-31 Jan Beulich <jbeulich@suse.com>
1067 * i386-opc.h (ZEROING_MASKING) Rename to ...
1068 (DYNAMIC_MASKING): ... this. Adjust comment.
1069 * i386-opc.tbl (MaskingMorZ): Define.
1070 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1071 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1072 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1073 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1074 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1075 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1076 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1077 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1078 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1080 2018-07-31 Jan Beulich <jbeulich@suse.com>
1082 * i386-opc.tbl: Use element rather than vector size for AVX512*
1083 scatter/gather insns.
1084 * i386-tbl.h: Re-generate.
1086 2018-07-31 Jan Beulich <jbeulich@suse.com>
1088 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1089 (cpu_flags): Drop CpuVREX.
1090 * i386-opc.h (CpuVREX): Delete.
1091 (union i386_cpu_flags): Remove cpuvrex.
1092 * i386-init.h, i386-tbl.h: Re-generate.
1094 2018-07-30 Jim Wilson <jimw@sifive.com>
1096 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1098 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1100 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1102 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1103 * Makefile.in: Regenerated.
1104 * configure.ac: Add C-SKY.
1105 * configure: Regenerated.
1106 * csky-dis.c: New file.
1107 * csky-opc.h: New file.
1108 * disassemble.c (ARCH_csky): Define.
1109 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1110 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1112 2018-07-27 Alan Modra <amodra@gmail.com>
1114 * ppc-opc.c (insert_sprbat): Correct function parameter and
1116 (extract_sprbat): Likewise, variable too.
1118 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1119 Alan Modra <amodra@gmail.com>
1121 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1122 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1123 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1124 support disjointed BAT.
1125 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1126 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1127 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1129 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1130 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1132 * i386-gen.c (adjust_broadcast_modifier): New function.
1133 (process_i386_opcode_modifier): Add an argument for operands.
1134 Adjust the Broadcast value based on operands.
1135 (output_i386_opcode): Pass operand_types to
1136 process_i386_opcode_modifier.
1137 (process_i386_opcodes): Pass NULL as operands to
1138 process_i386_opcode_modifier.
1139 * i386-opc.h (BYTE_BROADCAST): New.
1140 (WORD_BROADCAST): Likewise.
1141 (DWORD_BROADCAST): Likewise.
1142 (QWORD_BROADCAST): Likewise.
1143 (i386_opcode_modifier): Expand broadcast to 3 bits.
1144 * i386-tbl.h: Regenerated.
1146 2018-07-24 Alan Modra <amodra@gmail.com>
1149 * or1k-desc.h: Regenerate.
1151 2018-07-24 Jan Beulich <jbeulich@suse.com>
1153 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1154 vcvtusi2ss, and vcvtusi2sd.
1155 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1156 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1157 * i386-tbl.h: Re-generate.
1159 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1161 * arc-opc.c (extract_w6): Fix extending the sign.
1163 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1165 * arc-tbl.h (vewt): Allow it for ARC EM family.
1167 2018-07-23 Alan Modra <amodra@gmail.com>
1170 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1171 opcode variants for mtspr/mfspr encodings.
1173 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1174 Maciej W. Rozycki <macro@mips.com>
1176 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1177 loongson3a descriptors.
1178 (parse_mips_ase_option): Handle -M loongson-mmi option.
1179 (print_mips_disassembler_options): Document -M loongson-mmi.
1180 * mips-opc.c (LMMI): New macro.
1181 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1184 2018-07-19 Jan Beulich <jbeulich@suse.com>
1186 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1187 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1188 IgnoreSize and [XYZ]MMword where applicable.
1189 * i386-tbl.h: Re-generate.
1191 2018-07-19 Jan Beulich <jbeulich@suse.com>
1193 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1194 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1195 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1196 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1197 * i386-tbl.h: Re-generate.
1199 2018-07-19 Jan Beulich <jbeulich@suse.com>
1201 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1202 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1203 VPCLMULQDQ templates into their respective AVX512VL counterparts
1204 where possible, using Disp8ShiftVL and CheckRegSize instead of
1205 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1206 * i386-tbl.h: Re-generate.
1208 2018-07-19 Jan Beulich <jbeulich@suse.com>
1210 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1211 AVX512VL counterparts where possible, using Disp8ShiftVL and
1212 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1213 IgnoreSize) as appropriate.
1214 * i386-tbl.h: Re-generate.
1216 2018-07-19 Jan Beulich <jbeulich@suse.com>
1218 * i386-opc.tbl: Fold AVX512BW templates into their respective
1219 AVX512VL counterparts where possible, using Disp8ShiftVL and
1220 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1221 IgnoreSize) as appropriate.
1222 * i386-tbl.h: Re-generate.
1224 2018-07-19 Jan Beulich <jbeulich@suse.com>
1226 * i386-opc.tbl: Fold AVX512CD templates into their respective
1227 AVX512VL counterparts where possible, using Disp8ShiftVL and
1228 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1229 IgnoreSize) as appropriate.
1230 * i386-tbl.h: Re-generate.
1232 2018-07-19 Jan Beulich <jbeulich@suse.com>
1234 * i386-opc.h (DISP8_SHIFT_VL): New.
1235 * i386-opc.tbl (Disp8ShiftVL): Define.
1236 (various): Fold AVX512VL templates into their respective
1237 AVX512F counterparts where possible, using Disp8ShiftVL and
1238 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1239 IgnoreSize) as appropriate.
1240 * i386-tbl.h: Re-generate.
1242 2018-07-19 Jan Beulich <jbeulich@suse.com>
1244 * Makefile.am: Change dependencies and rule for
1245 $(srcdir)/i386-init.h.
1246 * Makefile.in: Re-generate.
1247 * i386-gen.c (process_i386_opcodes): New local variable
1248 "marker". Drop opening of input file. Recognize marker and line
1250 * i386-opc.tbl (OPCODE_I386_H): Define.
1251 (i386-opc.h): Include it.
1254 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1257 * i386-opc.h (Byte): Update comments.
1263 (Xmmword): Likewise.
1264 (Ymmword): Likewise.
1265 (Zmmword): Likewise.
1266 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1268 * i386-tbl.h: Regenerated.
1270 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1272 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1273 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1274 * aarch64-asm-2.c: Regenerate.
1275 * aarch64-dis-2.c: Regenerate.
1276 * aarch64-opc-2.c: Regenerate.
1278 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1281 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1282 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1283 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1284 sqdmulh, sqrdmulh): Use Em16.
1286 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1288 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1289 csdb together with them.
1290 (thumb32_opcodes): Likewise.
1292 2018-07-11 Jan Beulich <jbeulich@suse.com>
1294 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1295 requiring 32-bit registers as operands 2 and 3. Improve
1297 (mwait, mwaitx): Fold templates. Improve comments.
1298 OPERAND_TYPE_INOUTPORTREG.
1299 * i386-tbl.h: Re-generate.
1301 2018-07-11 Jan Beulich <jbeulich@suse.com>
1303 * i386-gen.c (operand_type_init): Remove
1304 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1305 OPERAND_TYPE_INOUTPORTREG.
1306 * i386-init.h: Re-generate.
1308 2018-07-11 Jan Beulich <jbeulich@suse.com>
1310 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1311 (wrssq, wrussq): Add Qword.
1312 * i386-tbl.h: Re-generate.
1314 2018-07-11 Jan Beulich <jbeulich@suse.com>
1316 * i386-opc.h: Rename OTMax to OTNum.
1317 (OTNumOfUints): Adjust calculation.
1318 (OTUnused): Directly alias to OTNum.
1320 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1322 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1324 (lea_reg_xys): Likewise.
1325 (print_insn_loop_primitive): Rename `reg' local variable to
1328 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1331 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1333 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1336 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1337 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1339 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1342 * mips-dis.c (mips_option_arg_t): New enumeration.
1343 (mips_options): New variable.
1344 (disassembler_options_mips): New function.
1345 (print_mips_disassembler_options): Reimplement in terms of
1346 `disassembler_options_mips'.
1347 * arm-dis.c (disassembler_options_arm): Adapt to using the
1348 `disasm_options_and_args_t' structure.
1349 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1350 * s390-dis.c (disassembler_options_s390): Likewise.
1352 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1354 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1356 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1357 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1358 * testsuite/ld-arm/tls-longplt.d: Likewise.
1360 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1363 * aarch64-asm-2.c: Regenerate.
1364 * aarch64-dis-2.c: Likewise.
1365 * aarch64-opc-2.c: Likewise.
1366 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1367 * aarch64-opc.c (operand_general_constraint_met_p,
1368 aarch64_print_operand): Likewise.
1369 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1370 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1372 (AARCH64_OPERANDS): Add Em2.
1374 2018-06-26 Nick Clifton <nickc@redhat.com>
1376 * po/uk.po: Updated Ukranian translation.
1377 * po/de.po: Updated German translation.
1378 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1380 2018-06-26 Nick Clifton <nickc@redhat.com>
1382 * nfp-dis.c: Fix spelling mistake.
1384 2018-06-24 Nick Clifton <nickc@redhat.com>
1386 * configure: Regenerate.
1387 * po/opcodes.pot: Regenerate.
1389 2018-06-24 Nick Clifton <nickc@redhat.com>
1391 2.31 branch created.
1393 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1395 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1396 * aarch64-asm-2.c: Regenerate.
1397 * aarch64-dis-2.c: Likewise.
1399 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1401 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1402 `-M ginv' option description.
1404 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1407 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1410 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1412 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1413 * configure.ac: Remove AC_PREREQ.
1414 * Makefile.in: Re-generate.
1415 * aclocal.m4: Re-generate.
1416 * configure: Re-generate.
1418 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1420 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1421 mips64r6 descriptors.
1422 (parse_mips_ase_option): Handle -Mginv option.
1423 (print_mips_disassembler_options): Document -Mginv.
1424 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1426 (mips_opcodes): Define ginvi and ginvt.
1428 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1429 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1431 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1432 * mips-opc.c (CRC, CRC64): New macros.
1433 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1434 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1437 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1440 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1441 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1443 2018-06-06 Alan Modra <amodra@gmail.com>
1445 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1446 setjmp. Move init for some other vars later too.
1448 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1450 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1451 (dis_private): Add new fields for property section tracking.
1452 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1453 (xtensa_instruction_fits): New functions.
1454 (fetch_data): Bump minimal fetch size to 4.
1455 (print_insn_xtensa): Make struct dis_private static.
1456 Load and prepare property table on section change.
1457 Don't disassemble literals. Don't disassemble instructions that
1458 cross property table boundaries.
1460 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1462 * configure: Regenerated.
1464 2018-06-01 Jan Beulich <jbeulich@suse.com>
1466 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1467 * i386-tbl.h: Re-generate.
1469 2018-06-01 Jan Beulich <jbeulich@suse.com>
1471 * i386-opc.tbl (sldt, str): Add NoRex64.
1472 * i386-tbl.h: Re-generate.
1474 2018-06-01 Jan Beulich <jbeulich@suse.com>
1476 * i386-opc.tbl (invpcid): Add Oword.
1477 * i386-tbl.h: Re-generate.
1479 2018-06-01 Alan Modra <amodra@gmail.com>
1481 * sysdep.h (_bfd_error_handler): Don't declare.
1482 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1483 * rl78-decode.opc: Likewise.
1484 * msp430-decode.c: Regenerate.
1485 * rl78-decode.c: Regenerate.
1487 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1489 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1490 * i386-init.h : Regenerated.
1492 2018-05-25 Alan Modra <amodra@gmail.com>
1494 * Makefile.in: Regenerate.
1495 * po/POTFILES.in: Regenerate.
1497 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1499 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1500 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1501 (insert_bab, extract_bab, insert_btab, extract_btab,
1502 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1503 (BAT, BBA VBA RBS XB6S): Delete macros.
1504 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1505 (BB, BD, RBX, XC6): Update for new macros.
1506 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1507 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1508 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1509 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1511 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1513 * Makefile.am: Add support for s12z architecture.
1514 * configure.ac: Likewise.
1515 * disassemble.c: Likewise.
1516 * disassemble.h: Likewise.
1517 * Makefile.in: Regenerate.
1518 * configure: Regenerate.
1519 * s12z-dis.c: New file.
1522 2018-05-18 Alan Modra <amodra@gmail.com>
1524 * nfp-dis.c: Don't #include libbfd.h.
1525 (init_nfp3200_priv): Use bfd_get_section_contents.
1526 (nit_nfp6000_mecsr_sec): Likewise.
1528 2018-05-17 Nick Clifton <nickc@redhat.com>
1530 * po/zh_CN.po: Updated simplified Chinese translation.
1532 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1535 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1536 * aarch64-dis-2.c: Regenerate.
1538 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1541 * aarch64-asm.c (opintl.h): Include.
1542 (aarch64_ins_sysreg): Enforce read/write constraints.
1543 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1544 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1545 (F_REG_READ, F_REG_WRITE): New.
1546 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1547 AARCH64_OPND_SYSREG.
1548 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1549 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1550 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1551 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1552 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1553 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1554 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1555 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1556 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1557 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1558 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1559 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1560 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1561 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1562 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1563 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1564 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1566 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1569 * aarch64-dis.c (no_notes: New.
1570 (parse_aarch64_dis_option): Support notes.
1571 (aarch64_decode_insn, print_operands): Likewise.
1572 (print_aarch64_disassembler_options): Document notes.
1573 * aarch64-opc.c (aarch64_print_operand): Support notes.
1575 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1578 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1579 and take error struct.
1580 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1581 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1582 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1583 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1584 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1585 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1586 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1587 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1588 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1589 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1590 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1591 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1592 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1593 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1594 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1595 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1596 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1597 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1598 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1599 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1600 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1601 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1602 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1603 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1604 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1605 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1606 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1607 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1608 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1609 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1610 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1611 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1612 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1613 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1614 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1615 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1616 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1617 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1618 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1619 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1620 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1621 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1622 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1623 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1624 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1625 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1626 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1627 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1628 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1629 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1630 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1631 (determine_disassembling_preference, aarch64_decode_insn,
1632 print_insn_aarch64_word, print_insn_data): Take errors struct.
1633 (print_insn_aarch64): Use errors.
1634 * aarch64-asm-2.c: Regenerate.
1635 * aarch64-dis-2.c: Regenerate.
1636 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1637 boolean in aarch64_insert_operan.
1638 (print_operand_extractor): Likewise.
1639 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1641 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1643 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1645 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1647 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1649 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1651 * cr16-opc.c (cr16_instruction): Comment typo fix.
1652 * hppa-dis.c (print_insn_hppa): Likewise.
1654 2018-05-08 Jim Wilson <jimw@sifive.com>
1656 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1657 (match_c_slli64, match_srxi_as_c_srxi): New.
1658 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1659 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1660 <c.slli, c.srli, c.srai>: Use match_s_slli.
1661 <c.slli64, c.srli64, c.srai64>: New.
1663 2018-05-08 Alan Modra <amodra@gmail.com>
1665 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1666 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1667 partition opcode space for index lookup.
1669 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1671 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1672 <insn_length>: ...with this. Update usage.
1673 Remove duplicate call to *info->memory_error_func.
1675 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1676 H.J. Lu <hongjiu.lu@intel.com>
1678 * i386-dis.c (Gva): New.
1679 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1680 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1681 (prefix_table): New instructions (see prefix above).
1682 (mod_table): New instructions (see prefix above).
1683 (OP_G): Handle va_mode.
1684 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1685 CPU_MOVDIR64B_FLAGS.
1686 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1687 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1688 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1689 * i386-opc.tbl: Add movidir{i,64b}.
1690 * i386-init.h: Regenerated.
1691 * i386-tbl.h: Likewise.
1693 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1695 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1697 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1698 (AddrPrefixOpReg): This.
1699 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1700 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1702 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1704 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1705 (vle_num_opcodes): Likewise.
1706 (spe2_num_opcodes): Likewise.
1707 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1708 initialization loop.
1709 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1710 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1713 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1715 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1717 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1719 Makefile.am: Added nfp-dis.c.
1720 configure.ac: Added bfd_nfp_arch.
1721 disassemble.h: Added print_insn_nfp prototype.
1722 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1723 nfp-dis.c: New, for NFP support.
1724 po/POTFILES.in: Added nfp-dis.c to the list.
1725 Makefile.in: Regenerate.
1726 configure: Regenerate.
1728 2018-04-26 Jan Beulich <jbeulich@suse.com>
1730 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1731 templates into their base ones.
1732 * i386-tlb.h: Re-generate.
1734 2018-04-26 Jan Beulich <jbeulich@suse.com>
1736 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1737 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1738 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1739 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1740 * i386-init.h: Re-generate.
1742 2018-04-26 Jan Beulich <jbeulich@suse.com>
1744 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1745 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1746 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1747 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1749 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1751 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1753 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1754 cpuregzmm, and cpuregmask.
1755 * i386-init.h: Re-generate.
1756 * i386-tbl.h: Re-generate.
1758 2018-04-26 Jan Beulich <jbeulich@suse.com>
1760 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1761 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1762 * i386-init.h: Re-generate.
1764 2018-04-26 Jan Beulich <jbeulich@suse.com>
1766 * i386-gen.c (VexImmExt): Delete.
1767 * i386-opc.h (VexImmExt, veximmext): Delete.
1768 * i386-opc.tbl: Drop all VexImmExt uses.
1769 * i386-tlb.h: Re-generate.
1771 2018-04-25 Jan Beulich <jbeulich@suse.com>
1773 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1774 register-only forms.
1775 * i386-tlb.h: Re-generate.
1777 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1779 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1781 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1783 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1785 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1786 (cpu_flags): Add CpuCLDEMOTE.
1787 * i386-init.h: Regenerate.
1788 * i386-opc.h (enum): Add CpuCLDEMOTE,
1789 (i386_cpu_flags): Add cpucldemote.
1790 * i386-opc.tbl: Add cldemote.
1791 * i386-tbl.h: Regenerate.
1793 2018-04-16 Alan Modra <amodra@gmail.com>
1795 * Makefile.am: Remove sh5 and sh64 support.
1796 * configure.ac: Likewise.
1797 * disassemble.c: Likewise.
1798 * disassemble.h: Likewise.
1799 * sh-dis.c: Likewise.
1800 * sh64-dis.c: Delete.
1801 * sh64-opc.c: Delete.
1802 * sh64-opc.h: Delete.
1803 * Makefile.in: Regenerate.
1804 * configure: Regenerate.
1805 * po/POTFILES.in: Regenerate.
1807 2018-04-16 Alan Modra <amodra@gmail.com>
1809 * Makefile.am: Remove w65 support.
1810 * configure.ac: Likewise.
1811 * disassemble.c: Likewise.
1812 * disassemble.h: Likewise.
1813 * w65-dis.c: Delete.
1814 * w65-opc.h: Delete.
1815 * Makefile.in: Regenerate.
1816 * configure: Regenerate.
1817 * po/POTFILES.in: Regenerate.
1819 2018-04-16 Alan Modra <amodra@gmail.com>
1821 * configure.ac: Remove we32k support.
1822 * configure: Regenerate.
1824 2018-04-16 Alan Modra <amodra@gmail.com>
1826 * Makefile.am: Remove m88k support.
1827 * configure.ac: Likewise.
1828 * disassemble.c: Likewise.
1829 * disassemble.h: Likewise.
1830 * m88k-dis.c: Delete.
1831 * Makefile.in: Regenerate.
1832 * configure: Regenerate.
1833 * po/POTFILES.in: Regenerate.
1835 2018-04-16 Alan Modra <amodra@gmail.com>
1837 * Makefile.am: Remove i370 support.
1838 * configure.ac: Likewise.
1839 * disassemble.c: Likewise.
1840 * disassemble.h: Likewise.
1841 * i370-dis.c: Delete.
1842 * i370-opc.c: Delete.
1843 * Makefile.in: Regenerate.
1844 * configure: Regenerate.
1845 * po/POTFILES.in: Regenerate.
1847 2018-04-16 Alan Modra <amodra@gmail.com>
1849 * Makefile.am: Remove h8500 support.
1850 * configure.ac: Likewise.
1851 * disassemble.c: Likewise.
1852 * disassemble.h: Likewise.
1853 * h8500-dis.c: Delete.
1854 * h8500-opc.h: Delete.
1855 * Makefile.in: Regenerate.
1856 * configure: Regenerate.
1857 * po/POTFILES.in: Regenerate.
1859 2018-04-16 Alan Modra <amodra@gmail.com>
1861 * configure.ac: Remove tahoe support.
1862 * configure: Regenerate.
1864 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1866 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1868 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1870 * i386-tbl.h: Regenerated.
1872 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1874 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1875 PREFIX_MOD_1_0FAE_REG_6.
1877 (OP_E_register): Use va_mode.
1878 * i386-dis-evex.h (prefix_table):
1879 New instructions (see prefixes above).
1880 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1881 (cpu_flags): Likewise.
1882 * i386-opc.h (enum): Likewise.
1883 (i386_cpu_flags): Likewise.
1884 * i386-opc.tbl: Add umonitor, umwait, tpause.
1885 * i386-init.h: Regenerate.
1886 * i386-tbl.h: Likewise.
1888 2018-04-11 Alan Modra <amodra@gmail.com>
1890 * opcodes/i860-dis.c: Delete.
1891 * opcodes/i960-dis.c: Delete.
1892 * Makefile.am: Remove i860 and i960 support.
1893 * configure.ac: Likewise.
1894 * disassemble.c: Likewise.
1895 * disassemble.h: Likewise.
1896 * Makefile.in: Regenerate.
1897 * configure: Regenerate.
1898 * po/POTFILES.in: Regenerate.
1900 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1903 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1905 (print_insn): Clear vex instead of vex.evex.
1907 2018-04-04 Nick Clifton <nickc@redhat.com>
1909 * po/es.po: Updated Spanish translation.
1911 2018-03-28 Jan Beulich <jbeulich@suse.com>
1913 * i386-gen.c (opcode_modifiers): Delete VecESize.
1914 * i386-opc.h (VecESize): Delete.
1915 (struct i386_opcode_modifier): Delete vecesize.
1916 * i386-opc.tbl: Drop VecESize.
1917 * i386-tlb.h: Re-generate.
1919 2018-03-28 Jan Beulich <jbeulich@suse.com>
1921 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1922 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1923 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1924 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1925 * i386-tlb.h: Re-generate.
1927 2018-03-28 Jan Beulich <jbeulich@suse.com>
1929 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1931 * i386-tlb.h: Re-generate.
1933 2018-03-28 Jan Beulich <jbeulich@suse.com>
1935 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1936 (vex_len_table): Drop Y for vcvt*2si.
1937 (putop): Replace plain 'Y' handling by abort().
1939 2018-03-28 Nick Clifton <nickc@redhat.com>
1942 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1943 instructions with only a base address register.
1944 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1945 handle AARHC64_OPND_SVE_ADDR_R.
1946 (aarch64_print_operand): Likewise.
1947 * aarch64-asm-2.c: Regenerate.
1948 * aarch64_dis-2.c: Regenerate.
1949 * aarch64-opc-2.c: Regenerate.
1951 2018-03-22 Jan Beulich <jbeulich@suse.com>
1953 * i386-opc.tbl: Drop VecESize from register only insn forms and
1954 memory forms not allowing broadcast.
1955 * i386-tlb.h: Re-generate.
1957 2018-03-22 Jan Beulich <jbeulich@suse.com>
1959 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1960 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1961 sha256*): Drop Disp<N>.
1963 2018-03-22 Jan Beulich <jbeulich@suse.com>
1965 * i386-dis.c (EbndS, bnd_swap_mode): New.
1966 (prefix_table): Use EbndS.
1967 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1968 * i386-opc.tbl (bndmov): Move misplaced Load.
1969 * i386-tlb.h: Re-generate.
1971 2018-03-22 Jan Beulich <jbeulich@suse.com>
1973 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1974 templates allowing memory operands and folded ones for register
1976 * i386-tlb.h: Re-generate.
1978 2018-03-22 Jan Beulich <jbeulich@suse.com>
1980 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1981 256-bit templates. Drop redundant leftover Disp<N>.
1982 * i386-tlb.h: Re-generate.
1984 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1986 * riscv-opc.c (riscv_insn_types): New.
1988 2018-03-13 Nick Clifton <nickc@redhat.com>
1990 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1992 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1994 * i386-opc.tbl: Add Optimize to clr.
1995 * i386-tbl.h: Regenerated.
1997 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1999 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2000 * i386-opc.h (OldGcc): Removed.
2001 (i386_opcode_modifier): Remove oldgcc.
2002 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2003 instructions for old (<= 2.8.1) versions of gcc.
2004 * i386-tbl.h: Regenerated.
2006 2018-03-08 Jan Beulich <jbeulich@suse.com>
2008 * i386-opc.h (EVEXDYN): New.
2009 * i386-opc.tbl: Fold various AVX512VL templates.
2010 * i386-tlb.h: Re-generate.
2012 2018-03-08 Jan Beulich <jbeulich@suse.com>
2014 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2015 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2016 vpexpandd, vpexpandq): Fold AFX512VF templates.
2017 * i386-tlb.h: Re-generate.
2019 2018-03-08 Jan Beulich <jbeulich@suse.com>
2021 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2022 Fold 128- and 256-bit VEX-encoded templates.
2023 * i386-tlb.h: Re-generate.
2025 2018-03-08 Jan Beulich <jbeulich@suse.com>
2027 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2028 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2029 vpexpandd, vpexpandq): Fold AVX512F templates.
2030 * i386-tlb.h: Re-generate.
2032 2018-03-08 Jan Beulich <jbeulich@suse.com>
2034 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2035 64-bit templates. Drop Disp<N>.
2036 * i386-tlb.h: Re-generate.
2038 2018-03-08 Jan Beulich <jbeulich@suse.com>
2040 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2041 and 256-bit templates.
2042 * i386-tlb.h: Re-generate.
2044 2018-03-08 Jan Beulich <jbeulich@suse.com>
2046 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2047 * i386-tlb.h: Re-generate.
2049 2018-03-08 Jan Beulich <jbeulich@suse.com>
2051 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2053 * i386-tlb.h: Re-generate.
2055 2018-03-08 Jan Beulich <jbeulich@suse.com>
2057 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2058 * i386-tlb.h: Re-generate.
2060 2018-03-08 Jan Beulich <jbeulich@suse.com>
2062 * i386-gen.c (opcode_modifiers): Delete FloatD.
2063 * i386-opc.h (FloatD): Delete.
2064 (struct i386_opcode_modifier): Delete floatd.
2065 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2067 * i386-tlb.h: Re-generate.
2069 2018-03-08 Jan Beulich <jbeulich@suse.com>
2071 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2073 2018-03-08 Jan Beulich <jbeulich@suse.com>
2075 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2076 * i386-tlb.h: Re-generate.
2078 2018-03-08 Jan Beulich <jbeulich@suse.com>
2080 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2082 * i386-tlb.h: Re-generate.
2084 2018-03-07 Alan Modra <amodra@gmail.com>
2086 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2088 * disassemble.h (print_insn_rs6000): Delete.
2089 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2090 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2091 (print_insn_rs6000): Delete.
2093 2018-03-03 Alan Modra <amodra@gmail.com>
2095 * sysdep.h (opcodes_error_handler): Define.
2096 (_bfd_error_handler): Declare.
2097 * Makefile.am: Remove stray #.
2098 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2100 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2101 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2102 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2103 opcodes_error_handler to print errors. Standardize error messages.
2104 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2105 and include opintl.h.
2106 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2107 * i386-gen.c: Standardize error messages.
2108 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2109 * Makefile.in: Regenerate.
2110 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2111 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2112 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2113 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2114 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2115 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2116 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2117 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2118 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2119 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2120 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2121 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2122 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2124 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2126 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2127 vpsub[bwdq] instructions.
2128 * i386-tbl.h: Regenerated.
2130 2018-03-01 Alan Modra <amodra@gmail.com>
2132 * configure.ac (ALL_LINGUAS): Sort.
2133 * configure: Regenerate.
2135 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2137 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2138 macro by assignements.
2140 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2143 * i386-gen.c (opcode_modifiers): Add Optimize.
2144 * i386-opc.h (Optimize): New enum.
2145 (i386_opcode_modifier): Add optimize.
2146 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2147 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2148 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2149 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2150 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2152 * i386-tbl.h: Regenerated.
2154 2018-02-26 Alan Modra <amodra@gmail.com>
2156 * crx-dis.c (getregliststring): Allocate a large enough buffer
2157 to silence false positive gcc8 warning.
2159 2018-02-22 Shea Levy <shea@shealevy.com>
2161 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2163 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2165 * i386-opc.tbl: Add {rex},
2166 * i386-tbl.h: Regenerated.
2168 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2170 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2171 (mips16_opcodes): Replace `M' with `m' for "restore".
2173 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2175 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2177 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2179 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2180 variable to `function_index'.
2182 2018-02-13 Nick Clifton <nickc@redhat.com>
2185 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2186 about truncation of printing.
2188 2018-02-12 Henry Wong <henry@stuffedcow.net>
2190 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2192 2018-02-05 Nick Clifton <nickc@redhat.com>
2194 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2196 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2198 * i386-dis.c (enum): Add pconfig.
2199 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2200 (cpu_flags): Add CpuPCONFIG.
2201 * i386-opc.h (enum): Add CpuPCONFIG.
2202 (i386_cpu_flags): Add cpupconfig.
2203 * i386-opc.tbl: Add PCONFIG instruction.
2204 * i386-init.h: Regenerate.
2205 * i386-tbl.h: Likewise.
2207 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2209 * i386-dis.c (enum): Add PREFIX_0F09.
2210 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2211 (cpu_flags): Add CpuWBNOINVD.
2212 * i386-opc.h (enum): Add CpuWBNOINVD.
2213 (i386_cpu_flags): Add cpuwbnoinvd.
2214 * i386-opc.tbl: Add WBNOINVD instruction.
2215 * i386-init.h: Regenerate.
2216 * i386-tbl.h: Likewise.
2218 2018-01-17 Jim Wilson <jimw@sifive.com>
2220 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2222 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2224 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2225 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2226 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2227 (cpu_flags): Add CpuIBT, CpuSHSTK.
2228 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2229 (i386_cpu_flags): Add cpuibt, cpushstk.
2230 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2231 * i386-init.h: Regenerate.
2232 * i386-tbl.h: Likewise.
2234 2018-01-16 Nick Clifton <nickc@redhat.com>
2236 * po/pt_BR.po: Updated Brazilian Portugese translation.
2237 * po/de.po: Updated German translation.
2239 2018-01-15 Jim Wilson <jimw@sifive.com>
2241 * riscv-opc.c (match_c_nop): New.
2242 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2244 2018-01-15 Nick Clifton <nickc@redhat.com>
2246 * po/uk.po: Updated Ukranian translation.
2248 2018-01-13 Nick Clifton <nickc@redhat.com>
2250 * po/opcodes.pot: Regenerated.
2252 2018-01-13 Nick Clifton <nickc@redhat.com>
2254 * configure: Regenerate.
2256 2018-01-13 Nick Clifton <nickc@redhat.com>
2258 2.30 branch created.
2260 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2262 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2263 * i386-tbl.h: Regenerate.
2265 2018-01-10 Jan Beulich <jbeulich@suse.com>
2267 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2268 * i386-tbl.h: Re-generate.
2270 2018-01-10 Jan Beulich <jbeulich@suse.com>
2272 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2273 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2274 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2275 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2276 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2277 Disp8MemShift of AVX512VL forms.
2278 * i386-tbl.h: Re-generate.
2280 2018-01-09 Jim Wilson <jimw@sifive.com>
2282 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2283 then the hi_addr value is zero.
2285 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2287 * arm-dis.c (arm_opcodes): Add csdb.
2288 (thumb32_opcodes): Add csdb.
2290 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2292 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2293 * aarch64-asm-2.c: Regenerate.
2294 * aarch64-dis-2.c: Regenerate.
2295 * aarch64-opc-2.c: Regenerate.
2297 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2300 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2301 Remove AVX512 vmovd with 64-bit operands.
2302 * i386-tbl.h: Regenerated.
2304 2018-01-05 Jim Wilson <jimw@sifive.com>
2306 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2309 2018-01-03 Alan Modra <amodra@gmail.com>
2311 Update year range in copyright notice of all files.
2313 2018-01-02 Jan Beulich <jbeulich@suse.com>
2315 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2316 and OPERAND_TYPE_REGZMM entries.
2318 For older changes see ChangeLog-2017
2320 Copyright (C) 2018 Free Software Foundation, Inc.
2322 Copying and distribution of this file, with or without modification,
2323 are permitted in any medium without royalty provided the copyright
2324 notice and this notice are preserved.
2330 version-control: never