1 2017-08-31 James Bowman <james.bowman@ftdichip.com>
3 * ft32-dis.c (print_insn_ft32): Correct display of non-address
6 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
7 Edmar Wienskoski <edmar.wienskoski@nxp.com>
9 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
10 PPC_OPCODE_EFS2 flag to "e200z4" entry.
11 New entries efs2 and spe2.
12 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
13 (SPE2_OPCD_SEGS): New macro.
14 (spe2_opcd_indices): New.
15 (disassemble_init_powerpc): Handle SPE2 opcodes.
16 (lookup_spe2): New function.
17 (print_insn_powerpc): call lookup_spe2.
18 * ppc-opc.c (insert_evuimm1_ex0): New function.
19 (extract_evuimm1_ex0): Likewise.
20 (insert_evuimm_lt8): Likewise.
21 (extract_evuimm_lt8): Likewise.
22 (insert_off_spe2): Likewise.
23 (extract_off_spe2): Likewise.
24 (insert_Ddd): Likewise.
25 (extract_Ddd): Likewise.
27 (EVUIMM_LT8): Likewise.
28 (EVUIMM_LT16): Adjust.
31 (EVUIMM_1_EX0): Likewise.
34 (VX_OFF_SPE2): Likewise.
37 (VX_MASK_DDD): New mask.
39 (VX_RA_CONST): New macro.
40 (VX_RA_CONST_MASK): Likewise.
41 (VX_RB_CONST): Likewise.
42 (VX_RB_CONST_MASK): Likewise.
43 (VX_OFF_SPE2_MASK): Likewise.
44 (VX_SPE_CRFD): Likewise.
45 (VX_SPE_CRFD_MASK VX): Likewise.
46 (VX_SPE2_CLR): Likewise.
47 (VX_SPE2_CLR_MASK): Likewise.
48 (VX_SPE2_SPLATB): Likewise.
49 (VX_SPE2_SPLATB_MASK): Likewise.
50 (VX_SPE2_OCTET): Likewise.
51 (VX_SPE2_OCTET_MASK): Likewise.
52 (VX_SPE2_DDHH): Likewise.
53 (VX_SPE2_DDHH_MASK): Likewise.
54 (VX_SPE2_HH): Likewise.
55 (VX_SPE2_HH_MASK): Likewise.
56 (VX_SPE2_EVMAR): Likewise.
57 (VX_SPE2_EVMAR_MASK): Likewise.
60 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
61 (powerpc_macros): Map old SPE instructions have new names
62 with the same opcodes. Add SPE2 instructions which just are
64 (spe2_opcodes): Add SPE2 opcodes.
66 2017-08-23 Alan Modra <amodra@gmail.com>
68 * ppc-opc.c: Formatting and comment fixes. Move insert and
69 extract functions earlier, deleting forward declarations.
70 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
73 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
75 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
77 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
78 Edmar Wienskoski <edmar.wienskoski@nxp.com>
80 * ppc-opc.c (insert_evuimm2_ex0): New function.
81 (extract_evuimm2_ex0): Likewise.
82 (insert_evuimm4_ex0): Likewise.
83 (extract_evuimm4_ex0): Likewise.
84 (insert_evuimm8_ex0): Likewise.
85 (extract_evuimm8_ex0): Likewise.
86 (insert_evuimm_lt16): Likewise.
87 (extract_evuimm_lt16): Likewise.
88 (insert_rD_rS_even): Likewise.
89 (extract_rD_rS_even): Likewise.
90 (insert_off_lsp): Likewise.
91 (extract_off_lsp): Likewise.
92 (RD_EVEN): New operand.
95 (EVUIMM_LT16): New operand.
97 (EVUIMM_2_EX0): New operand.
99 (EVUIMM_4_EX0): New operand.
101 (EVUIMM_8_EX0): New operand.
103 (VX_OFF): New operand.
105 (VX_LSP_MASK): Likewise.
106 (VX_LSP_OFF_MASK): Likewise.
107 (PPC_OPCODE_LSP): Likewise.
108 (vle_opcodes): Add LSP opcodes.
109 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
111 2017-08-09 Jiong Wang <jiong.wang@arm.com>
113 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
114 register operands in CRC instructions.
115 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
118 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
120 * disassemble.c (disassembler): Mark big and mach with
123 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
125 * disassemble.c (disassembler): Remove arch/mach/endian
128 2017-07-25 Nick Clifton <nickc@redhat.com>
131 * arc-opc.c (insert_rhv2): Use lower case first letter in error
133 (insert_r0): Likewise.
134 (insert_r1): Likewise.
135 (insert_r2): Likewise.
136 (insert_r3): Likewise.
137 (insert_sp): Likewise.
138 (insert_gp): Likewise.
139 (insert_pcl): Likewise.
140 (insert_blink): Likewise.
141 (insert_ilink1): Likewise.
142 (insert_ilink2): Likewise.
143 (insert_ras): Likewise.
144 (insert_rbs): Likewise.
145 (insert_rcs): Likewise.
146 (insert_simm3s): Likewise.
147 (insert_rrange): Likewise.
148 (insert_r13el): Likewise.
149 (insert_fpel): Likewise.
150 (insert_blinkel): Likewise.
151 (insert_pclel): Likewise.
152 (insert_nps_bitop_size_2b): Likewise.
153 (insert_nps_imm_offset): Likewise.
154 (insert_nps_imm_entry): Likewise.
155 (insert_nps_size_16bit): Likewise.
156 (insert_nps_##NAME##_pos): Likewise.
157 (insert_nps_##NAME): Likewise.
158 (insert_nps_bitop_ins_ext): Likewise.
159 (insert_nps_##NAME): Likewise.
160 (insert_nps_min_hofs): Likewise.
161 (insert_nps_##NAME): Likewise.
162 (insert_nps_rbdouble_64): Likewise.
163 (insert_nps_misc_imm_offset): Likewise.
164 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
167 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
168 Jiong Wang <jiong.wang@arm.com>
170 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
172 * aarch64-dis-2.c: Regenerated.
174 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
176 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
179 2017-07-20 Nick Clifton <nickc@redhat.com>
181 * po/de.po: Updated German translation.
183 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
185 * arc-regs.h (sec_stat): New aux register.
186 (aux_kernel_sp): Likewise.
187 (aux_sec_u_sp): Likewise.
188 (aux_sec_k_sp): Likewise.
189 (sec_vecbase_build): Likewise.
190 (nsc_table_top): Likewise.
191 (nsc_table_base): Likewise.
192 (ersec_stat): Likewise.
193 (aux_sec_except): Likewise.
195 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
197 * arc-opc.c (extract_uimm12_20): New function.
198 (UIMM12_20): New operand.
200 * arc-tbl.h (sjli): Add new instruction.
202 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
203 John Eric Martin <John.Martin@emmicro-us.com>
205 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
206 (UIMM3_23): Adjust accordingly.
207 * arc-regs.h: Add/correct jli_base register.
208 * arc-tbl.h (jli_s): Likewise.
210 2017-07-18 Nick Clifton <nickc@redhat.com>
213 * aarch64-opc.c: Fix spelling typos.
214 * i386-dis.c: Likewise.
216 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
218 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
219 max_addr_offset and octets variables to size_t.
221 2017-07-12 Alan Modra <amodra@gmail.com>
223 * po/da.po: Update from translationproject.org/latest/opcodes/.
224 * po/de.po: Likewise.
225 * po/es.po: Likewise.
226 * po/fi.po: Likewise.
227 * po/fr.po: Likewise.
228 * po/id.po: Likewise.
229 * po/it.po: Likewise.
230 * po/nl.po: Likewise.
231 * po/pt_BR.po: Likewise.
232 * po/ro.po: Likewise.
233 * po/sv.po: Likewise.
234 * po/tr.po: Likewise.
235 * po/uk.po: Likewise.
236 * po/vi.po: Likewise.
237 * po/zh_CN.po: Likewise.
239 2017-07-11 Yao Qi <yao.qi@linaro.org>
240 Alan Modra <amodra@gmail.com>
242 * cgen.sh: Mark generated files read-only.
243 * epiphany-asm.c: Regenerate.
244 * epiphany-desc.c: Regenerate.
245 * epiphany-desc.h: Regenerate.
246 * epiphany-dis.c: Regenerate.
247 * epiphany-ibld.c: Regenerate.
248 * epiphany-opc.c: Regenerate.
249 * epiphany-opc.h: Regenerate.
250 * fr30-asm.c: Regenerate.
251 * fr30-desc.c: Regenerate.
252 * fr30-desc.h: Regenerate.
253 * fr30-dis.c: Regenerate.
254 * fr30-ibld.c: Regenerate.
255 * fr30-opc.c: Regenerate.
256 * fr30-opc.h: Regenerate.
257 * frv-asm.c: Regenerate.
258 * frv-desc.c: Regenerate.
259 * frv-desc.h: Regenerate.
260 * frv-dis.c: Regenerate.
261 * frv-ibld.c: Regenerate.
262 * frv-opc.c: Regenerate.
263 * frv-opc.h: Regenerate.
264 * ip2k-asm.c: Regenerate.
265 * ip2k-desc.c: Regenerate.
266 * ip2k-desc.h: Regenerate.
267 * ip2k-dis.c: Regenerate.
268 * ip2k-ibld.c: Regenerate.
269 * ip2k-opc.c: Regenerate.
270 * ip2k-opc.h: Regenerate.
271 * iq2000-asm.c: Regenerate.
272 * iq2000-desc.c: Regenerate.
273 * iq2000-desc.h: Regenerate.
274 * iq2000-dis.c: Regenerate.
275 * iq2000-ibld.c: Regenerate.
276 * iq2000-opc.c: Regenerate.
277 * iq2000-opc.h: Regenerate.
278 * lm32-asm.c: Regenerate.
279 * lm32-desc.c: Regenerate.
280 * lm32-desc.h: Regenerate.
281 * lm32-dis.c: Regenerate.
282 * lm32-ibld.c: Regenerate.
283 * lm32-opc.c: Regenerate.
284 * lm32-opc.h: Regenerate.
285 * lm32-opinst.c: Regenerate.
286 * m32c-asm.c: Regenerate.
287 * m32c-desc.c: Regenerate.
288 * m32c-desc.h: Regenerate.
289 * m32c-dis.c: Regenerate.
290 * m32c-ibld.c: Regenerate.
291 * m32c-opc.c: Regenerate.
292 * m32c-opc.h: Regenerate.
293 * m32r-asm.c: Regenerate.
294 * m32r-desc.c: Regenerate.
295 * m32r-desc.h: Regenerate.
296 * m32r-dis.c: Regenerate.
297 * m32r-ibld.c: Regenerate.
298 * m32r-opc.c: Regenerate.
299 * m32r-opc.h: Regenerate.
300 * m32r-opinst.c: Regenerate.
301 * mep-asm.c: Regenerate.
302 * mep-desc.c: Regenerate.
303 * mep-desc.h: Regenerate.
304 * mep-dis.c: Regenerate.
305 * mep-ibld.c: Regenerate.
306 * mep-opc.c: Regenerate.
307 * mep-opc.h: Regenerate.
308 * mt-asm.c: Regenerate.
309 * mt-desc.c: Regenerate.
310 * mt-desc.h: Regenerate.
311 * mt-dis.c: Regenerate.
312 * mt-ibld.c: Regenerate.
313 * mt-opc.c: Regenerate.
314 * mt-opc.h: Regenerate.
315 * or1k-asm.c: Regenerate.
316 * or1k-desc.c: Regenerate.
317 * or1k-desc.h: Regenerate.
318 * or1k-dis.c: Regenerate.
319 * or1k-ibld.c: Regenerate.
320 * or1k-opc.c: Regenerate.
321 * or1k-opc.h: Regenerate.
322 * or1k-opinst.c: Regenerate.
323 * xc16x-asm.c: Regenerate.
324 * xc16x-desc.c: Regenerate.
325 * xc16x-desc.h: Regenerate.
326 * xc16x-dis.c: Regenerate.
327 * xc16x-ibld.c: Regenerate.
328 * xc16x-opc.c: Regenerate.
329 * xc16x-opc.h: Regenerate.
330 * xstormy16-asm.c: Regenerate.
331 * xstormy16-desc.c: Regenerate.
332 * xstormy16-desc.h: Regenerate.
333 * xstormy16-dis.c: Regenerate.
334 * xstormy16-ibld.c: Regenerate.
335 * xstormy16-opc.c: Regenerate.
336 * xstormy16-opc.h: Regenerate.
338 2017-07-07 Alan Modra <amodra@gmail.com>
340 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
341 * m32c-dis.c: Regenerate.
342 * mep-dis.c: Regenerate.
344 2017-07-05 Borislav Petkov <bp@suse.de>
346 * i386-dis.c: Enable ModRM.reg /6 aliases.
348 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
350 * opcodes/arm-dis.c: Support MVFR2 in disassembly
353 2017-07-04 Tristan Gingold <gingold@adacore.com>
355 * configure: Regenerate.
357 2017-07-03 Tristan Gingold <gingold@adacore.com>
359 * po/opcodes.pot: Regenerate.
361 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
363 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
364 entries to the MSA ASE instruction block.
366 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
367 Maciej W. Rozycki <macro@imgtec.com>
369 * micromips-opc.c (XPA, XPAVZ): New macros.
370 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
373 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
374 Maciej W. Rozycki <macro@imgtec.com>
376 * micromips-opc.c (I36): New macro.
377 (micromips_opcodes): Add "eretnc".
379 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
380 Andrew Bennett <andrew.bennett@imgtec.com>
382 * mips-dis.c (mips_calculate_combination_ases): Handle the
384 (parse_mips_ase_option): New function.
385 (parse_mips_dis_option): Factor out ASE option handling to the
386 new function. Call `mips_calculate_combination_ases'.
387 * mips-opc.c (XPAVZ): New macro.
388 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
389 "mfhgc0", "mthc0" and "mthgc0".
391 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
393 * mips-dis.c (mips_calculate_combination_ases): New function.
394 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
395 calculation to the new function.
396 (set_default_mips_dis_options): Call the new function.
398 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
400 * arc-dis.c (parse_disassembler_options): Use
401 FOR_EACH_DISASSEMBLER_OPTION.
403 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
405 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
406 disassembler option strings.
407 (parse_cpu_option): Likewise.
409 2017-06-28 Tamar Christina <tamar.christina@arm.com>
411 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
412 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
413 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
414 (aarch64_feature_dotprod, DOT_INSN): New.
416 * aarch64-dis-2.c: Regenerated.
418 2017-06-28 Jiong Wang <jiong.wang@arm.com>
420 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
422 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
423 Matthew Fortune <matthew.fortune@imgtec.com>
424 Andrew Bennett <andrew.bennett@imgtec.com>
426 * mips-formats.h (INT_BIAS): New macro.
427 (INT_ADJ): Redefine in INT_BIAS terms.
428 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
429 (mips_print_save_restore): New function.
430 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
431 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
433 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
434 (print_mips16_insn_arg): Call `mips_print_save_restore' for
435 OP_SAVE_RESTORE_LIST handling, factored out from here.
436 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
437 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
438 (mips_builtin_opcodes): Add "restore" and "save" entries.
439 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
441 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
443 2017-06-23 Andrew Waterman <andrew@sifive.com>
445 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
446 alias; do not mark SLTI instruction as an alias.
448 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
450 * i386-dis.c (RM_0FAE_REG_5): Removed.
451 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
452 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
453 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
454 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
455 PREFIX_MOD_3_0F01_REG_5_RM_0.
456 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
457 PREFIX_MOD_3_0FAE_REG_5.
458 (mod_table): Update MOD_0FAE_REG_5.
459 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
460 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
461 * i386-tbl.h: Regenerated.
463 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
465 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
466 * i386-opc.tbl: Likewise.
467 * i386-tbl.h: Regenerated.
469 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
471 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
473 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
476 2017-06-19 Nick Clifton <nickc@redhat.com>
479 * score-dis.c (score_opcodes): Add sentinel.
481 2017-06-16 Alan Modra <amodra@gmail.com>
483 * rx-decode.c: Regenerate.
485 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
488 * i386-dis.c (OP_E_register): Check valid bnd register.
491 2017-06-15 Nick Clifton <nickc@redhat.com>
494 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
497 2017-06-15 Nick Clifton <nickc@redhat.com>
500 * rl78-decode.opc (OP_BUF_LEN): Define.
501 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
502 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
504 * rl78-decode.c: Regenerate.
506 2017-06-15 Nick Clifton <nickc@redhat.com>
509 * bfin-dis.c (gregs): Clip index to prevent overflow.
514 2017-06-14 Nick Clifton <nickc@redhat.com>
517 * score7-dis.c (score_opcodes): Add sentinel.
519 2017-06-14 Yao Qi <yao.qi@linaro.org>
521 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
522 * arm-dis.c: Likewise.
523 * ia64-dis.c: Likewise.
524 * mips-dis.c: Likewise.
525 * spu-dis.c: Likewise.
526 * disassemble.h (print_insn_aarch64): New declaration, moved from
528 (print_insn_big_arm, print_insn_big_mips): Likewise.
529 (print_insn_i386, print_insn_ia64): Likewise.
530 (print_insn_little_arm, print_insn_little_mips): Likewise.
532 2017-06-14 Nick Clifton <nickc@redhat.com>
535 * rx-decode.opc: Include libiberty.h
536 (GET_SCALE): New macro - validates access to SCALE array.
537 (GET_PSCALE): New macro - validates access to PSCALE array.
538 (DIs, SIs, S2Is, rx_disp): Use new macros.
539 * rx-decode.c: Regenerate.
541 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
543 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
545 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
547 * arc-dis.c (enforced_isa_mask): Declare.
548 (cpu_types): Likewise.
549 (parse_cpu_option): New function.
550 (parse_disassembler_options): Use it.
551 (print_insn_arc): Use enforced_isa_mask.
552 (print_arc_disassembler_options): Document new options.
554 2017-05-24 Yao Qi <yao.qi@linaro.org>
556 * alpha-dis.c: Include disassemble.h, don't include
558 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
559 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
560 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
561 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
562 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
563 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
564 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
565 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
566 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
567 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
568 * moxie-dis.c, msp430-dis.c, mt-dis.c:
569 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
570 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
571 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
572 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
573 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
574 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
575 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
576 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
577 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
578 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
579 * z80-dis.c, z8k-dis.c: Likewise.
580 * disassemble.h: New file.
582 2017-05-24 Yao Qi <yao.qi@linaro.org>
584 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
585 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
587 2017-05-24 Yao Qi <yao.qi@linaro.org>
589 * disassemble.c (disassembler): Add arguments a, big and mach.
592 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
594 * i386-dis.c (NOTRACK_Fixup): New.
596 (NOTRACK_PREFIX): Likewise.
597 (last_active_prefix): Likewise.
598 (reg_table): Use NOTRACK on indirect call and jmp.
599 (ckprefix): Set last_active_prefix.
600 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
601 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
602 * i386-opc.h (NoTrackPrefixOk): New.
603 (i386_opcode_modifier): Add notrackprefixok.
604 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
606 * i386-tbl.h: Regenerated.
608 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
610 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
612 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
614 (print_insn_sparc): Handle new operand types.
615 * sparc-opc.c (MASK_M8): Define.
617 (v6notlet): Likewise.
628 (v9andleon): Likewise.
631 (HWS2_VM8): Likewise.
632 (sparc_opcode_archs): Add entry for "m8".
633 (sparc_opcodes): Add OSA2017 and M8 instructions
634 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
636 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
637 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
638 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
639 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
640 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
641 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
642 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
643 ASI_CORE_SELECT_COMMIT_NHT.
645 2017-05-18 Alan Modra <amodra@gmail.com>
647 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
648 * aarch64-dis.c: Likewise.
649 * aarch64-gen.c: Likewise.
650 * aarch64-opc.c: Likewise.
652 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
653 Matthew Fortune <matthew.fortune@imgtec.com>
655 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
656 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
657 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
658 (print_insn_arg) <OP_REG28>: Add handler.
659 (validate_insn_args) <OP_REG28>: Handle.
660 (print_mips16_insn_arg): Handle MIPS16 instructions that require
661 32-bit encoding and 9-bit immediates.
662 (print_insn_mips16): Handle MIPS16 instructions that require
663 32-bit encoding and MFC0/MTC0 operand decoding.
664 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
665 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
666 (RD_C0, WR_C0, E2, E2MT): New macros.
667 (mips16_opcodes): Add entries for MIPS16e2 instructions:
668 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
669 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
670 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
671 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
672 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
673 instructions, "swl", "swr", "sync" and its "sync_acquire",
674 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
675 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
676 regular/extended entries for original MIPS16 ISA revision
677 instructions whose extended forms are subdecoded in the MIPS16e2
678 ISA revision: "li", "sll" and "srl".
680 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
682 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
683 reference in CP0 move operand decoding.
685 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
687 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
689 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
691 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
693 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
694 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
695 "sync_rmb" and "sync_wmb" as aliases.
696 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
697 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
699 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
701 * arc-dis.c (parse_option): Update quarkse_em option..
702 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
704 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
706 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
708 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
710 2017-05-01 Michael Clark <michaeljclark@mac.com>
712 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
715 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
717 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
718 and branches and not synthetic data instructions.
720 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
722 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
724 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
726 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
727 * arc-opc.c (insert_r13el): New function.
729 * arc-tbl.h: Add new enter/leave variants.
731 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
733 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
735 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
737 * mips-dis.c (print_mips_disassembler_options): Add
740 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
742 * mips16-opc.c (AL): New macro.
743 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
744 of "ld" and "lw" as aliases.
746 2017-04-24 Tamar Christina <tamar.christina@arm.com>
748 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
751 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
752 Alan Modra <amodra@gmail.com>
754 * ppc-opc.c (ELEV): Define.
755 (vle_opcodes): Add se_rfgi and e_sc.
756 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
759 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
761 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
763 2017-04-21 Nick Clifton <nickc@redhat.com>
766 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
769 2017-04-13 Alan Modra <amodra@gmail.com>
771 * epiphany-desc.c: Regenerate.
772 * fr30-desc.c: Regenerate.
773 * frv-desc.c: Regenerate.
774 * ip2k-desc.c: Regenerate.
775 * iq2000-desc.c: Regenerate.
776 * lm32-desc.c: Regenerate.
777 * m32c-desc.c: Regenerate.
778 * m32r-desc.c: Regenerate.
779 * mep-desc.c: Regenerate.
780 * mt-desc.c: Regenerate.
781 * or1k-desc.c: Regenerate.
782 * xc16x-desc.c: Regenerate.
783 * xstormy16-desc.c: Regenerate.
785 2017-04-11 Alan Modra <amodra@gmail.com>
787 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
788 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
789 PPC_OPCODE_TMR for e6500.
790 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
791 (PPCVEC3): Define as PPC_OPCODE_POWER9.
792 (PPCVSX2): Define as PPC_OPCODE_POWER8.
793 (PPCVSX3): Define as PPC_OPCODE_POWER9.
794 (PPCHTM): Define as PPC_OPCODE_POWER8.
795 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
797 2017-04-10 Alan Modra <amodra@gmail.com>
799 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
800 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
801 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
802 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
804 2017-04-09 Pip Cet <pipcet@gmail.com>
806 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
807 appropriate floating-point precision directly.
809 2017-04-07 Alan Modra <amodra@gmail.com>
811 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
812 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
813 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
814 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
815 vector instructions with E6500 not PPCVEC2.
817 2017-04-06 Pip Cet <pipcet@gmail.com>
819 * Makefile.am: Add wasm32-dis.c.
820 * configure.ac: Add wasm32-dis.c to wasm32 target.
821 * disassemble.c: Add wasm32 disassembler code.
822 * wasm32-dis.c: New file.
823 * Makefile.in: Regenerate.
824 * configure: Regenerate.
825 * po/POTFILES.in: Regenerate.
826 * po/opcodes.pot: Regenerate.
828 2017-04-05 Pedro Alves <palves@redhat.com>
830 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
831 * arm-dis.c (parse_arm_disassembler_options): Constify.
832 * ppc-dis.c (powerpc_init_dialect): Constify local.
833 * vax-dis.c (parse_disassembler_options): Constify.
835 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
837 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
840 2017-03-30 Pip Cet <pipcet@gmail.com>
842 * configure.ac: Add (empty) bfd_wasm32_arch target.
843 * configure: Regenerate
844 * po/opcodes.pot: Regenerate.
846 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
848 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
850 * opcodes/sparc-opc.c (asi_table): New ASIs.
852 2017-03-29 Alan Modra <amodra@gmail.com>
854 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
856 (lookup_powerpc): Don't special case -1 dialect. Handle
858 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
859 lookup_powerpc call, pass it on second.
861 2017-03-27 Alan Modra <amodra@gmail.com>
864 * ppc-dis.c (struct ppc_mopt): Comment.
865 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
867 2017-03-27 Rinat Zelig <rinat@mellanox.com>
869 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
870 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
871 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
872 (insert_nps_misc_imm_offset): New function.
873 (extract_nps_misc imm_offset): New function.
874 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
875 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
877 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
879 * s390-mkopc.c (main): Remove vx2 check.
880 * s390-opc.txt: Remove vx2 instruction flags.
882 2017-03-21 Rinat Zelig <rinat@mellanox.com>
884 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
885 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
886 (insert_nps_imm_offset): New function.
887 (extract_nps_imm_offset): New function.
888 (insert_nps_imm_entry): New function.
889 (extract_nps_imm_entry): New function.
891 2017-03-17 Alan Modra <amodra@gmail.com>
894 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
895 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
896 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
898 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
900 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
904 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
906 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
908 2017-03-13 Andrew Waterman <andrew@sifive.com>
910 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
915 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
917 * i386-gen.c (opcode_modifiers): Replace S with Load.
918 * i386-opc.h (S): Removed.
920 (i386_opcode_modifier): Replace s with load.
921 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
922 and {evex}. Replace S with Load.
923 * i386-tbl.h: Regenerated.
925 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
927 * i386-opc.tbl: Use CpuCET on rdsspq.
928 * i386-tbl.h: Regenerated.
930 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
932 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
933 <vsx>: Do not use PPC_OPCODE_VSX3;
935 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
937 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
939 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
941 * i386-dis.c (REG_0F1E_MOD_3): New enum.
942 (MOD_0F1E_PREFIX_1): Likewise.
943 (MOD_0F38F5_PREFIX_2): Likewise.
944 (MOD_0F38F6_PREFIX_0): Likewise.
945 (RM_0F1E_MOD_3_REG_7): Likewise.
946 (PREFIX_MOD_0_0F01_REG_5): Likewise.
947 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
948 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
949 (PREFIX_0F1E): Likewise.
950 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
951 (PREFIX_0F38F5): Likewise.
952 (dis386_twobyte): Use PREFIX_0F1E.
953 (reg_table): Add REG_0F1E_MOD_3.
954 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
955 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
956 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
957 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
958 (three_byte_table): Use PREFIX_0F38F5.
959 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
960 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
961 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
962 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
963 PREFIX_MOD_3_0F01_REG_5_RM_2.
964 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
965 (cpu_flags): Add CpuCET.
966 * i386-opc.h (CpuCET): New enum.
967 (CpuUnused): Commented out.
968 (i386_cpu_flags): Add cpucet.
969 * i386-opc.tbl: Add Intel CET instructions.
970 * i386-init.h: Regenerated.
971 * i386-tbl.h: Likewise.
973 2017-03-06 Alan Modra <amodra@gmail.com>
976 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
977 (extract_raq, extract_ras, extract_rbx): New functions.
978 (powerpc_operands): Use opposite corresponding insert function.
980 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
981 register restriction.
983 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
985 * disassemble.c Include "safe-ctype.h".
986 (disassemble_init_for_target): Handle s390 init.
987 (remove_whitespace_and_extra_commas): New function.
988 (disassembler_options_cmp): Likewise.
989 * arm-dis.c: Include "libiberty.h".
991 (regnames): Use long disassembler style names.
992 Add force-thumb and no-force-thumb options.
993 (NUM_ARM_REGNAMES): Rename from this...
994 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
995 (get_arm_regname_num_options): Delete.
996 (set_arm_regname_option): Likewise.
997 (get_arm_regnames): Likewise.
998 (parse_disassembler_options): Likewise.
999 (parse_arm_disassembler_option): Rename from this...
1000 (parse_arm_disassembler_options): ...to this. Make static.
1001 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1002 (print_insn): Use parse_arm_disassembler_options.
1003 (disassembler_options_arm): New function.
1004 (print_arm_disassembler_options): Handle updated regnames.
1005 * ppc-dis.c: Include "libiberty.h".
1006 (ppc_opts): Add "32" and "64" entries.
1007 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1008 (powerpc_init_dialect): Add break to switch statement.
1009 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1010 (disassembler_options_powerpc): New function.
1011 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1012 Remove printing of "32" and "64".
1013 * s390-dis.c: Include "libiberty.h".
1014 (init_flag): Remove unneeded variable.
1015 (struct s390_options_t): New structure type.
1016 (options): New structure.
1017 (init_disasm): Rename from this...
1018 (disassemble_init_s390): ...to this. Add initializations for
1019 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1020 (print_insn_s390): Delete call to init_disasm.
1021 (disassembler_options_s390): New function.
1022 (print_s390_disassembler_options): Print using information from
1024 * po/opcodes.pot: Regenerate.
1026 2017-02-28 Jan Beulich <jbeulich@suse.com>
1028 * i386-dis.c (PCMPESTR_Fixup): New.
1029 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1030 (prefix_table): Use PCMPESTR_Fixup.
1031 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1033 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1034 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1035 Split 64-bit and non-64-bit variants.
1036 * opcodes/i386-tbl.h: Re-generate.
1038 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1040 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1041 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1042 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1043 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1044 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1045 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1046 (OP_SVE_V_HSD): New macros.
1047 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1048 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1049 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1050 (aarch64_opcode_table): Add new SVE instructions.
1051 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1052 for rotation operands. Add new SVE operands.
1053 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1054 (ins_sve_quad_index): Likewise.
1055 (ins_imm_rotate): Split into...
1056 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1057 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1058 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1060 (aarch64_ins_sve_addr_ri_s4): New function.
1061 (aarch64_ins_sve_quad_index): Likewise.
1062 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1063 * aarch64-asm-2.c: Regenerate.
1064 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1065 (ext_sve_quad_index): Likewise.
1066 (ext_imm_rotate): Split into...
1067 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1068 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1069 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1071 (aarch64_ext_sve_addr_ri_s4): New function.
1072 (aarch64_ext_sve_quad_index): Likewise.
1073 (aarch64_ext_sve_index): Allow quad indices.
1074 (do_misc_decoding): Likewise.
1075 * aarch64-dis-2.c: Regenerate.
1076 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1077 aarch64_field_kinds.
1078 (OPD_F_OD_MASK): Widen by one bit.
1079 (OPD_F_NO_ZR): Bump accordingly.
1080 (get_operand_field_width): New function.
1081 * aarch64-opc.c (fields): Add new SVE fields.
1082 (operand_general_constraint_met_p): Handle new SVE operands.
1083 (aarch64_print_operand): Likewise.
1084 * aarch64-opc-2.c: Regenerate.
1086 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1088 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1089 (aarch64_feature_compnum): ...this.
1090 (SIMD_V8_3): Replace with...
1092 (CNUM_INSN): New macro.
1093 (aarch64_opcode_table): Use it for the complex number instructions.
1095 2017-02-24 Jan Beulich <jbeulich@suse.com>
1097 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1099 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1101 Add support for associating SPARC ASIs with an architecture level.
1102 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1103 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1104 decoding of SPARC ASIs.
1106 2017-02-23 Jan Beulich <jbeulich@suse.com>
1108 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1109 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1111 2017-02-21 Jan Beulich <jbeulich@suse.com>
1113 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1114 1 (instead of to itself). Correct typo.
1116 2017-02-14 Andrew Waterman <andrew@sifive.com>
1118 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1121 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1123 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1124 (aarch64_sys_reg_supported_p): Handle them.
1126 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1128 * arc-opc.c (UIMM6_20R): Define.
1129 (SIMM12_20): Use above.
1130 (SIMM12_20R): Define.
1131 (SIMM3_5_S): Use above.
1132 (UIMM7_A32_11R_S): Define.
1133 (UIMM7_9_S): Use above.
1134 (UIMM3_13R_S): Define.
1135 (SIMM11_A32_7_S): Use above.
1137 (UIMM10_A32_8_S): Use above.
1138 (UIMM8_8R_S): Define.
1140 (arc_relax_opcodes): Use all above defines.
1142 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1144 * arc-regs.h: Distinguish some of the registers different on
1145 ARC700 and HS38 cpus.
1147 2017-02-14 Alan Modra <amodra@gmail.com>
1150 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1151 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1153 2017-02-11 Stafford Horne <shorne@gmail.com>
1154 Alan Modra <amodra@gmail.com>
1156 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1157 Use insn_bytes_value and insn_int_value directly instead. Don't
1158 free allocated memory until function exit.
1160 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1162 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1164 2017-02-03 Nick Clifton <nickc@redhat.com>
1167 * aarch64-opc.c (print_register_list): Ensure that the register
1168 list index will fir into the tb buffer.
1169 (print_register_offset_address): Likewise.
1170 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1172 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1175 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1176 instructions when the previous fetch packet ends with a 32-bit
1179 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1181 * pru-opc.c: Remove vague reference to a future GDB port.
1183 2017-01-20 Nick Clifton <nickc@redhat.com>
1185 * po/ga.po: Updated Irish translation.
1187 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1189 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1191 2017-01-13 Yao Qi <yao.qi@linaro.org>
1193 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1194 if FETCH_DATA returns 0.
1195 (m68k_scan_mask): Likewise.
1196 (print_insn_m68k): Update code to handle -1 return value.
1198 2017-01-13 Yao Qi <yao.qi@linaro.org>
1200 * m68k-dis.c (enum print_insn_arg_error): New.
1201 (NEXTBYTE): Replace -3 with
1202 PRINT_INSN_ARG_MEMORY_ERROR.
1203 (NEXTULONG): Likewise.
1204 (NEXTSINGLE): Likewise.
1205 (NEXTDOUBLE): Likewise.
1206 (NEXTDOUBLE): Likewise.
1207 (NEXTPACKED): Likewise.
1208 (FETCH_ARG): Likewise.
1209 (FETCH_DATA): Update comments.
1210 (print_insn_arg): Update comments. Replace magic numbers with
1212 (match_insn_m68k): Likewise.
1214 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1216 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1217 * i386-dis-evex.h (evex_table): Updated.
1218 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1219 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1220 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1221 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1222 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1223 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1224 * i386-init.h: Regenerate.
1225 * i386-tbl.h: Ditto.
1227 2017-01-12 Yao Qi <yao.qi@linaro.org>
1229 * msp430-dis.c (msp430_singleoperand): Return -1 if
1230 msp430dis_opcode_signed returns false.
1231 (msp430_doubleoperand): Likewise.
1232 (msp430_branchinstr): Return -1 if
1233 msp430dis_opcode_unsigned returns false.
1234 (msp430x_calla_instr): Likewise.
1235 (print_insn_msp430): Likewise.
1237 2017-01-05 Nick Clifton <nickc@redhat.com>
1240 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1241 could not be matched.
1242 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1245 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1247 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1248 (aarch64_opcode_table): Use RCPC_INSN.
1250 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1252 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1254 * riscv-opcodes/all-opcodes: Likewise.
1256 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1258 * riscv-dis.c (print_insn_args): Add fall through comment.
1260 2017-01-03 Nick Clifton <nickc@redhat.com>
1262 * po/sr.po: New Serbian translation.
1263 * configure.ac (ALL_LINGUAS): Add sr.
1264 * configure: Regenerate.
1266 2017-01-02 Alan Modra <amodra@gmail.com>
1268 * epiphany-desc.h: Regenerate.
1269 * epiphany-opc.h: Regenerate.
1270 * fr30-desc.h: Regenerate.
1271 * fr30-opc.h: Regenerate.
1272 * frv-desc.h: Regenerate.
1273 * frv-opc.h: Regenerate.
1274 * ip2k-desc.h: Regenerate.
1275 * ip2k-opc.h: Regenerate.
1276 * iq2000-desc.h: Regenerate.
1277 * iq2000-opc.h: Regenerate.
1278 * lm32-desc.h: Regenerate.
1279 * lm32-opc.h: Regenerate.
1280 * m32c-desc.h: Regenerate.
1281 * m32c-opc.h: Regenerate.
1282 * m32r-desc.h: Regenerate.
1283 * m32r-opc.h: Regenerate.
1284 * mep-desc.h: Regenerate.
1285 * mep-opc.h: Regenerate.
1286 * mt-desc.h: Regenerate.
1287 * mt-opc.h: Regenerate.
1288 * or1k-desc.h: Regenerate.
1289 * or1k-opc.h: Regenerate.
1290 * xc16x-desc.h: Regenerate.
1291 * xc16x-opc.h: Regenerate.
1292 * xstormy16-desc.h: Regenerate.
1293 * xstormy16-opc.h: Regenerate.
1295 2017-01-02 Alan Modra <amodra@gmail.com>
1297 Update year range in copyright notice of all files.
1299 For older changes see ChangeLog-2016
1301 Copyright (C) 2017 Free Software Foundation, Inc.
1303 Copying and distribution of this file, with or without modification,
1304 are permitted in any medium without royalty provided the copyright
1305 notice and this notice are preserved.
1311 version-control: never