opcodes/ChangeLog

   1 2019-12-11  Alan Modra  <amodra@gmail.com>
   2
   3         * ns32k-dis.c (sign_extend): Correct last patch.
   4
   5 2019-12-11  Alan Modra  <amodra@gmail.com>
   6
   7         * vax-dis.c (NEXTLONG): Avoid signed overflow.
   8
   9 2019-12-11  Alan Modra  <amodra@gmail.com>
  10
  11         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
  12         sign extend using shifts.
  13
  14 2019-12-11  Alan Modra  <amodra@gmail.com>
  15
  16         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
  17
  18 2019-12-11  Alan Modra  <amodra@gmail.com>
  19
  20         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
  21         on NULL registertable entry.
  22         (tic4x_hash_opcode): Use unsigned arithmetic.
  23
  24 2019-12-11  Alan Modra  <amodra@gmail.com>
  25
  26         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
  27
  28 2019-12-11  Alan Modra  <amodra@gmail.com>
  29
  30         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
  31         (bit_extract_simple, sign_extend): Likewise.
  32
  33 2019-12-11  Alan Modra  <amodra@gmail.com>
  34
  35         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
  36
  37 2019-12-11  Alan Modra  <amodra@gmail.com>
  38
  39         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
  40
  41 2019-12-11  Alan Modra  <amodra@gmail.com>
  42
  43         * m68k-dis.c (COERCE32): Cast value first.
  44         (NEXTLONG, NEXTULONG): Avoid signed overflow.
  45
  46 2019-12-11  Alan Modra  <amodra@gmail.com>
  47
  48         * h8300-dis.c (extract_immediate): Avoid signed overflow.
  49         (bfd_h8_disassemble): Likewise.
  50
  51 2019-12-11  Alan Modra  <amodra@gmail.com>
  52
  53         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
  54         past end of operands array.
  55
  56 2019-12-11  Alan Modra  <amodra@gmail.com>
  57
  58         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
  59         overflow when collecting bytes of a number.
  60
  61 2019-12-11  Alan Modra  <amodra@gmail.com>
  62
  63         * cris-dis.c (print_with_operands): Avoid signed integer
  64         overflow when collecting bytes of a 32-bit integer.
  65
  66 2019-12-11  Alan Modra  <amodra@gmail.com>
  67
  68         * cr16-dis.c (EXTRACT, SBM): Rewrite.
  69         (cr16_match_opcode): Delete duplicate bcond test.
  70
  71 2019-12-11  Alan Modra  <amodra@gmail.com>
  72
  73         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
  74         (SIGNBIT): New.
  75         (MASKBITS, SIGNEXTEND): Rewrite.
  76         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
  77         unsigned arithmetic, instead assign result of SIGNEXTEND back
  78         to x.
  79         (fmtconst_val): Use 1u in shift expression.
  80
  81 2019-12-11  Alan Modra  <amodra@gmail.com>
  82
  83         * arc-dis.c (find_format_from_table): Use ull constant when
  84         shifting by up to 32.
  85
  86 2019-12-11  Alan Modra  <amodra@gmail.com>
  87
  88         PR 25270
  89         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
  90         false when field is zero for sve_size_tsz_bhs.
  91
  92 2019-12-11  Alan Modra  <amodra@gmail.com>
  93
  94         * epiphany-ibld.c: Regenerate.
  95
  96 2019-12-10  Alan Modra  <amodra@gmail.com>
  97
  98         PR 24960
  99         * disassemble.c (disassemble_free_target): New function.
 100
 101 2019-12-10  Alan Modra  <amodra@gmail.com>
 102
 103         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 104         * disassemble.c (disassemble_init_for_target): Likewise.
 105         * bpf-dis.c: Regenerate.
 106         * epiphany-dis.c: Regenerate.
 107         * fr30-dis.c: Regenerate.
 108         * frv-dis.c: Regenerate.
 109         * ip2k-dis.c: Regenerate.
 110         * iq2000-dis.c: Regenerate.
 111         * lm32-dis.c: Regenerate.
 112         * m32c-dis.c: Regenerate.
 113         * m32r-dis.c: Regenerate.
 114         * mep-dis.c: Regenerate.
 115         * mt-dis.c: Regenerate.
 116         * or1k-dis.c: Regenerate.
 117         * xc16x-dis.c: Regenerate.
 118         * xstormy16-dis.c: Regenerate.
 119
 120 2019-12-10  Alan Modra  <amodra@gmail.com>
 121
 122         * ppc-dis.c (private): Delete variable.
 123         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 124         (powerpc_init_dialect): Don't use global private.
 125
 126 2019-12-10  Alan Modra  <amodra@gmail.com>
 127
 128         * s12z-opc.c: Formatting.
 129
 130 2019-12-08  Alan Modra  <amodra@gmail.com>
 131
 132         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 133         registers.
 134
 135 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 136
 137         * aarch64-tbl.h (aarch64_feature_crypto,
 138         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 139         CRYPTO_V8_2_INSN): Delete.
 140
 141 2019-12-05  Alan Modra  <amodra@gmail.com>
 142
 143         PR 25249
 144         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 145         (struct string_buf): New.
 146         (strbuf): New function.
 147         (get_field): Use strbuf rather than strdup of local temp.
 148         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 149         (get_field_rfsl, get_field_imm15): Likewise.
 150         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 151         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 152         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 153         get_field functions.
 154
 155 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 156
 157         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 158         * i386-tbl.h: Re-generate.
 159
 160 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 161
 162         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 163
 164 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 167         forms.
 168         (xbegin): Drop DefaultSize.
 169         * i386-tbl.h: Re-generate.
 170
 171 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 172
 173         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 174         Change the coproc CRC conditions to use the extension
 175         feature set, second word, base on ARM_EXT2_CRC.
 176
 177 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 178
 179         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 180         * i386-tbl.h: Re-generate.
 181
 182 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 183
 184         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 185         JumpInterSegment, and JumpAbsolute entries.
 186         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 187         JUMP_ABSOLUTE): Define.
 188         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 189         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 190         fields.
 191         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 192         JumpInterSegment): Define.
 193         * i386-tbl.h: Re-generate.
 194
 195 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-gen.c (operand_type_init): Remove
 198         OPERAND_TYPE_JUMPABSOLUTE entry.
 199         (opcode_modifiers): Add JumpAbsolute entry.
 200         (operand_types): Remove JumpAbsolute entry.
 201         * i386-opc.h (JumpAbsolute): Move between enums.
 202         (struct i386_opcode_modifier): Add jumpabsolute field.
 203         (union i386_operand_type): Remove jumpabsolute field.
 204         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 205         * i386-init.h, i386-tbl.h: Re-generate.
 206
 207 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 210         (operand_types): Remove AnySize entry.
 211         * i386-opc.h (AnySize): Move between enums.
 212         (struct i386_opcode_modifier): Add anysize field.
 213         (OTUnused): Un-comment.
 214         (union i386_operand_type): Remove anysize field.
 215         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 216         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 217         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 218         AnySize.
 219         * i386-tbl.h: Re-generate.
 220
 221 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 222
 223         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 224         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 225         use the floating point register (FPR).
 226
 227 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 228
 229         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 230         cmode 1101.
 231         (is_mve_encoding_conflict): Update cmode conflict checks for
 232         MVE_VMVN_IMM.
 233
 234 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 235
 236         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 237         entry.
 238         (operand_types): Remove EsSeg entry.
 239         (main): Replace stale use of OTMax.
 240         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 241         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 242         (EsSeg): Delete.
 243         (OTUnused): Comment out.
 244         (union i386_operand_type): Remove esseg field.
 245         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 246         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 247         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 248         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 249         * i386-init.h, i386-tbl.h: Re-generate.
 250
 251 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-gen.c (operand_instances): Add RegB entry.
 254         * i386-opc.h (enum operand_instance): Add RegB.
 255         * i386-opc.tbl (RegC, RegD, RegB): Define.
 256         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 257         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 258         monitorx, mwaitx): Drop ImmExt and convert encodings
 259         accordingly.
 260         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 261         (edx, rdx): Add Instance=RegD.
 262         (ebx, rbx): Add Instance=RegB.
 263         * i386-tbl.h: Re-generate.
 264
 265 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 266
 267         * i386-gen.c (operand_type_init): Adjust
 268         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 269         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 270         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 271         (operand_instances): New.
 272         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 273         (output_operand_type): New parameter "instance". Process it.
 274         (process_i386_operand_type): New local variable "instance".
 275         (main): Adjust static assertions.
 276         * i386-opc.h (INSTANCE_WIDTH): Define.
 277         (enum operand_instance): New.
 278         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 279         (union i386_operand_type): Replace acc, inoutportreg, and
 280         shiftcount by instance.
 281         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 282         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 283         Add Instance=.
 284         * i386-init.h, i386-tbl.h: Re-generate.
 285
 286 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 287
 288         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 289         smaxp/sminp entries' "tied_operand" field to 2.
 290
 291 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 292
 293         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 294         "index" local variable by that of the already existing "num".
 295
 296 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 297
 298         PR gas/25167
 299         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 300         * i386-tbl.h: Regenerated.
 301
 302 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 303
 304         * i386-gen.c (operand_type_init): Add Class= to
 305         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 306         OPERAND_TYPE_REGBND entry.
 307         (operand_classes): Add RegMask and RegBND entries.
 308         (operand_types): Drop RegMask and RegBND entry.
 309         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 310         (RegMask, RegBND): Delete.
 311         (union i386_operand_type): Remove regmask and regbnd fields.
 312         * i386-opc.tbl (RegMask, RegBND): Define.
 313         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 314         Class=RegBND.
 315         * i386-init.h, i386-tbl.h: Re-generate.
 316
 317 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 318
 319         * i386-gen.c (operand_type_init): Add Class= to
 320         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 321         OPERAND_TYPE_REGZMM entries.
 322         (operand_classes): Add RegMMX and RegSIMD entries.
 323         (operand_types): Drop RegMMX and RegSIMD entries.
 324         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 325         (RegMMX, RegSIMD): Delete.
 326         (union i386_operand_type): Remove regmmx and regsimd fields.
 327         * i386-opc.tbl (RegMMX): Define.
 328         (RegXMM, RegYMM, RegZMM): Add Class=.
 329         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 330         Class=RegSIMD.
 331         * i386-init.h, i386-tbl.h: Re-generate.
 332
 333 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 334
 335         * i386-gen.c (operand_type_init): Add Class= to
 336         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 337         entries.
 338         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 339         (operand_types): Drop Control, Debug, and Test entries.
 340         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 341         (Control, Debug, Test): Delete.
 342         (union i386_operand_type): Remove control, debug, and test
 343         fields.
 344         * i386-opc.tbl (Control, Debug, Test): Define.
 345         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 346         Class=RegDR, and Test by Class=RegTR.
 347         * i386-init.h, i386-tbl.h: Re-generate.
 348
 349 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 350
 351         * i386-gen.c (operand_type_init): Add Class= to
 352         OPERAND_TYPE_SREG entry.
 353         (operand_classes): Add SReg entry.
 354         (operand_types): Drop SReg entry.
 355         * i386-opc.h (enum operand_class): Add SReg.
 356         (SReg): Delete.
 357         (union i386_operand_type): Remove sreg field.
 358         * i386-opc.tbl (SReg): Define.
 359         * i386-reg.tbl: Replace SReg by Class=SReg.
 360         * i386-init.h, i386-tbl.h: Re-generate.
 361
 362 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 363
 364         * i386-gen.c (operand_type_init): Add Class=. New
 365         OPERAND_TYPE_ANYIMM entry.
 366         (operand_classes): New.
 367         (operand_types): Drop Reg entry.
 368         (output_operand_type): New parameter "class". Process it.
 369         (process_i386_operand_type): New local variable "class".
 370         (main): Adjust static assertions.
 371         * i386-opc.h (CLASS_WIDTH): Define.
 372         (enum operand_class): New.
 373         (Reg): Replace by Class. Adjust comment.
 374         (union i386_operand_type): Replace reg by class.
 375         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 376         Class=.
 377         * i386-reg.tbl: Replace Reg by Class=Reg.
 378         * i386-init.h: Re-generate.
 379
 380 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 381
 382         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 383         (aarch64_opcode_table): Add data gathering hint mnemonic.
 384         * opcodes/aarch64-dis-2.c: Account for new instruction.
 385
 386 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 387
 388         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 389
 390
 391 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 392
 393         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 394         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 395         aarch64_feature_f64mm): New feature sets.
 396         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 397         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 398         instructions.
 399         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 400         macros.
 401         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 402         (OP_SVE_QQQ): New qualifier.
 403         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 404         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 405         the movprfx constraint.
 406         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 407         (aarch64_opcode_table): Define new instructions smmla,
 408         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 409         uzip{1/2}, trn{1/2}.
 410         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 411         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 412         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 413         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 414         Account for new instructions.
 415         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 416         S4x32 operand.
 417         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 418
 419 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 420 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 421
 422         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 423         Armv8.6-A.
 424         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 425         (neon_opcodes): Add bfloat SIMD instructions.
 426         (print_insn_coprocessor): Add new control character %b to print
 427         condition code without checking cp_num.
 428         (print_insn_neon): Account for BFloat16 instructions that have no
 429         special top-byte handling.
 430
 431 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 432 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 433
 434         * arm-dis.c (print_insn_coprocessor,
 435         print_insn_generic_coprocessor): Create wrapper functions around
 436         the implementation of the print_insn_coprocessor control codes.
 437         (print_insn_coprocessor_1): Original print_insn_coprocessor
 438         function that now takes which array to look at as an argument.
 439         (print_insn_arm): Use both print_insn_coprocessor and
 440         print_insn_generic_coprocessor.
 441         (print_insn_thumb32): As above.
 442
 443 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 444 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 445
 446         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 447         in reglane special case.
 448         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 449         aarch64_find_next_opcode): Account for new instructions.
 450         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 451         in reglane special case.
 452         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 453         new AARCH64_OPND_QLF_S_2H qualifier.
 454         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 455         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 456         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 457         sets.
 458         (BFLOAT_SVE, BFLOAT): New feature set macros.
 459         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 460         instructions.
 461         (aarch64_opcode_table): Define new instructions bfdot,
 462         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 463         bfcvtn2, bfcvt.
 464
 465 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 466 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 467
 468         * aarch64-tbl.h (ARMV8_6): New macro.
 469
 470 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-dis.c (prefix_table): Add mcommit.
 473         (rm_table): Add rdpru.
 474         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 475         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 476         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 477         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 478         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 479         * i386-opc.tbl (mcommit, rdpru): New.
 480         * i386-init.h, i386-tbl.h: Re-generate.
 481
 482 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 483
 484         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 485         "names32" instead.
 486         (OP_Monitor): Drop local variable "op1_names", re-purpose
 487         "names" for it instead, and replace former "names" uses by
 488         "names32" ones.
 489
 490 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 491
 492         PR/gas 25167
 493         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 494         operand-less forms.
 495         * opcodes/i386-tbl.h: Re-generate.
 496
 497 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 498
 499         * i386-dis.c (OP_Mwaitx): Delete.
 500         (prefix_table): Use OP_Mwait for mwaitx entry.
 501         (OP_Mwait): Also handle mwaitx.
 502
 503 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 504
 505         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 506         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 507         (prefix_table): Add respective entries.
 508         (rm_table): Link to those entries.
 509
 510 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 511
 512         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 513         (REG_0F1C_P_0_MOD_0): ... this.
 514         (REG_0F1E_MOD_3): Rename to ...
 515         (REG_0F1E_P_1_MOD_3): ... this.
 516         (RM_0F01_REG_5): Rename to ...
 517         (RM_0F01_REG_5_MOD_3): ... this.
 518         (RM_0F01_REG_7): Rename to ...
 519         (RM_0F01_REG_7_MOD_3): ... this.
 520         (RM_0F1E_MOD_3_REG_7): Rename to ...
 521         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 522         (RM_0FAE_REG_6): Rename to ...
 523         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 524         (RM_0FAE_REG_7): Rename to ...
 525         (RM_0FAE_REG_7_MOD_3): ... this.
 526         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 527         (PREFIX_0F01_REG_5_MOD_0): ... this.
 528         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 529         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 530         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 531         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 532         (PREFIX_0FAE_REG_0): Rename to ...
 533         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 534         (PREFIX_0FAE_REG_1): Rename to ...
 535         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 536         (PREFIX_0FAE_REG_2): Rename to ...
 537         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 538         (PREFIX_0FAE_REG_3): Rename to ...
 539         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 540         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 541         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 542         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 543         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 544         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 545         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 546         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 547         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 548         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 549         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 550         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 551         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 552         (PREFIX_0FAE_REG_7): Rename to ...
 553         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 554         (PREFIX_MOD_0_0FC3): Rename to ...
 555         (PREFIX_0FC3_MOD_0): ... this.
 556         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 557         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 558         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 559         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 560         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 561         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 562         (reg_table, prefix_table, mod_table, rm_table): Adjust
 563         accordingly.
 564
 565 2019-11-04  Nick Clifton  <nickc@redhat.com>
 566
 567         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 568         of a v850 system register.  Move the v850_sreg_names array into
 569         this function.
 570         (get_v850_reg_name): Likewise for ordinary register names.
 571         (get_v850_vreg_name): Likewise for vector register names.
 572         (get_v850_cc_name): Likewise for condition codes.
 573         * get_v850_float_cc_name): Likewise for floating point condition
 574         codes.
 575         (get_v850_cacheop_name): Likewise for cache-ops.
 576         (get_v850_prefop_name): Likewise for pref-ops.
 577         (disassemble): Use the new accessor functions.
 578
 579 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 580
 581         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 582         immediate for the writeback form of ldraa/ldrab if it is 0.
 583         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 584         * aarch64-opc-2.c: Regenerated.
 585
 586 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 587
 588         * i386-gen.c (operand_type_shorthands): Delete.
 589         (operand_type_init): Expand previous shorthands.
 590         (set_bitfield_from_shorthand): Rename back to ...
 591         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 592         of operand_type_init[].
 593         (set_bitfield): Adjust call to the above function.
 594         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 595         RegXMM, RegYMM, RegZMM): Define.
 596         * i386-reg.tbl: Expand prior shorthands.
 597
 598 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-gen.c (output_i386_opcode): Change order of fields
 601         emitted to output.
 602         * i386-opc.h (struct insn_template): Move operands field.
 603         Convert extension_opcode field to unsigned short.
 604         * i386-tbl.h: Re-generate.
 605
 606 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 607
 608         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 609         of W.
 610         * i386-opc.h (W): Extend comment.
 611         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 612         general purpose variants not allowing for byte operands.
 613         * i386-tbl.h: Re-generate.
 614
 615 2019-10-29  Nick Clifton  <nickc@redhat.com>
 616
 617         * tic30-dis.c (print_branch): Correct size of operand array.
 618
 619 2019-10-29  Nick Clifton  <nickc@redhat.com>
 620
 621         * d30v-dis.c (print_insn): Check that operand index is valid
 622         before attempting to access the operands array.
 623
 624 2019-10-29  Nick Clifton  <nickc@redhat.com>
 625
 626         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 627         locating the bit to be tested.
 628
 629 2019-10-29  Nick Clifton  <nickc@redhat.com>
 630
 631         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 632         values.
 633         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 634         (print_insn_s12z):  Check for illegal size values.
 635
 636 2019-10-28  Nick Clifton  <nickc@redhat.com>
 637
 638         * csky-dis.c (csky_chars_to_number): Check for a negative
 639         count. Use an unsigned integer to construct the return value.
 640
 641 2019-10-28  Nick Clifton  <nickc@redhat.com>
 642
 643         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 644         operand buffer.  Set value to 15 not 13.
 645         (get_register_operand): Use OPERAND_BUFFER_LEN.
 646         (get_indirect_operand): Likewise.
 647         (print_two_operand): Likewise.
 648         (print_three_operand): Likewise.
 649         (print_oar_insn): Likewise.
 650
 651 2019-10-28  Nick Clifton  <nickc@redhat.com>
 652
 653         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 654         (bit_extract_simple): Likewise.
 655         (bit_copy): Likewise.
 656         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 657         index_offset array are not accessed.
 658
 659 2019-10-28  Nick Clifton  <nickc@redhat.com>
 660
 661         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 662         operand.
 663
 664 2019-10-25  Nick Clifton  <nickc@redhat.com>
 665
 666         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 667         access to opcodes.op array element.
 668
 669 2019-10-23  Nick Clifton  <nickc@redhat.com>
 670
 671         * rx-dis.c (get_register_name): Fix spelling typo in error
 672         message.
 673         (get_condition_name, get_flag_name, get_double_register_name)
 674         (get_double_register_high_name, get_double_register_low_name)
 675         (get_double_control_register_name, get_double_condition_name)
 676         (get_opsize_name, get_size_name): Likewise.
 677
 678 2019-10-22  Nick Clifton  <nickc@redhat.com>
 679
 680         * rx-dis.c (get_size_name): New function.  Provides safe
 681         access to name array.
 682         (get_opsize_name): Likewise.
 683         (print_insn_rx): Use the accessor functions.
 684
 685 2019-10-16  Nick Clifton  <nickc@redhat.com>
 686
 687         * rx-dis.c (get_register_name): New function.  Provides safe
 688         access to name array.
 689         (get_condition_name, get_flag_name, get_double_register_name)
 690         (get_double_register_high_name, get_double_register_low_name)
 691         (get_double_control_register_name, get_double_condition_name):
 692         Likewise.
 693         (print_insn_rx): Use the accessor functions.
 694
 695 2019-10-09  Nick Clifton  <nickc@redhat.com>
 696
 697         PR 25041
 698         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 699         instructions.
 700
 701 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 702
 703         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 704         (cmpsd): Likewise. Move EsSeg to other operand.
 705         * opcodes/i386-tbl.h: Re-generate.
 706
 707 2019-09-23  Alan Modra  <amodra@gmail.com>
 708
 709         * m68k-dis.c: Include cpu-m68k.h
 710
 711 2019-09-23  Alan Modra  <amodra@gmail.com>
 712
 713         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 714         "elf/mips.h" earlier.
 715
 716 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 717
 718         PR gas/25012
 719         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 720         with SReg operand.
 721         * i386-tbl.h: Re-generate.
 722
 723 2019-09-18  Alan Modra  <amodra@gmail.com>
 724
 725         * arc-ext.c: Update throughout for bfd section macro changes.
 726
 727 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 728
 729         * Makefile.in: Re-generate.
 730         * configure: Re-generate.
 731
 732 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 733
 734         * riscv-opc.c (riscv_opcodes): Change subset field
 735         to insn_class field for all instructions.
 736         (riscv_insn_types): Likewise.
 737
 738 2019-09-16  Phil Blundell  <pb@pbcl.net>
 739
 740         * configure: Regenerated.
 741
 742 2019-09-10  Miod Vallat  <miod@online.fr>
 743
 744         PR 24982
 745         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 746
 747 2019-09-09  Phil Blundell  <pb@pbcl.net>
 748
 749         binutils 2.33 branch created.
 750
 751 2019-09-03  Nick Clifton  <nickc@redhat.com>
 752
 753         PR 24961
 754         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 755         greater than zero before indexing via (bufcnt -1).
 756
 757 2019-09-03  Nick Clifton  <nickc@redhat.com>
 758
 759         PR 24958
 760         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 761         (MAX_SPEC_REG_NAME_LEN): Define.
 762         (struct mmix_dis_info): Use defined constants for array lengths.
 763         (get_reg_name): New function.
 764         (get_sprec_reg_name): New function.
 765         (print_insn_mmix): Use new functions.
 766
 767 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 768
 769         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 770         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 771         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 772
 773 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 774
 775         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 776         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 777         (aarch64_sys_reg_supported_p): Update checks for the above.
 778
 779 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 780
 781         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 782         cases MVE_SQRSHRL and MVE_UQRSHLL.
 783         (print_insn_mve): Add case for specifier 'k' to check
 784         specific bit of the instruction.
 785
 786 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 787
 788         PR 24854
 789         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 790         encountering an unknown machine type.
 791         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 792         cases return -1 rather than calling abort.
 793
 794 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 795
 796         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 797         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 798         IgnoreSize.
 799         * i386-tbl.h: Re-generate.
 800
 801 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 802
 803         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 804         instructions.
 805
 806 2019-07-30  Mel Chen <mel.chen@sifive.com>
 807
 808         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 809         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 810
 811         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 812         fscsr.
 813
 814 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 815
 816         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 817         and MPY class instructions.
 818         (parse_option): Add nps400 option.
 819         (print_arc_disassembler_options): Add nps400 info.
 820
 821 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 822
 823         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 824         (bspop): Likewise.
 825         (modapp): Likewise.
 826         * arc-opc.c (RAD_CHK): Add.
 827         * arc-tbl.h: Regenerate.
 828
 829 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 830
 831         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 832         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 833
 834 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 835
 836         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 837         instructions as UNPREDICTABLE.
 838
 839 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 840
 841         * bpf-desc.c: Regenerated.
 842
 843 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 844
 845         * i386-gen.c (static_assert): Define.
 846         (main): Use it.
 847         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 848         (Opcode_Modifier_Num): ... this.
 849         (Mem): Delete.
 850
 851 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 852
 853         * i386-gen.c (operand_types): Move RegMem ...
 854         (opcode_modifiers): ... here.
 855         * i386-opc.h (RegMem): Move to opcode modifer enum.
 856         (union i386_operand_type): Move regmem field ...
 857         (struct i386_opcode_modifier): ... here.
 858         * i386-opc.tbl (RegMem): Define.
 859         (mov, movq): Move RegMem on segment, control, debug, and test
 860         register flavors.
 861         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 862         to non-SSE2AVX flavor.
 863         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 864         Move RegMem on register only flavors. Drop IgnoreSize from
 865         legacy encoding flavors.
 866         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 867         flavors.
 868         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 869         register only flavors.
 870         (vmovd): Move RegMem and drop IgnoreSize on register only
 871         flavor. Change opcode and operand order to store form.
 872         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 873
 874 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 875
 876         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 877         entries.
 878         * i386-opc.h (SReg2, SReg3): Replace by ...
 879         (SReg): ... this.
 880         (union i386_operand_type): Replace sreg fields.
 881         * i386-opc.tbl (mov, ): Use SReg.
 882         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 883         register flavors.
 884         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 885         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 886
 887 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 888
 889         * bpf-desc.c: Regenerate.
 890         * bpf-opc.c: Likewise.
 891         * bpf-opc.h: Likewise.
 892
 893 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 894
 895         * bpf-desc.c: Regenerate.
 896         * bpf-opc.c: Likewise.
 897
 898 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 899
 900         * arm-dis.c (print_insn_coprocessor): Rename index to
 901         index_operand.
 902
 903 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 904
 905         * riscv-opc.c (riscv_insn_types): Add r4 type.
 906
 907         * riscv-opc.c (riscv_insn_types): Add b and j type.
 908
 909         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 910         format for sb type and correct s type.
 911
 912 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 913
 914         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 915         SVE FMOV alias of FCPY.
 916
 917 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 918
 919         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 920         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 921
 922 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 923
 924         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 925         registers in an instruction prefixed by MOVPRFX.
 926
 927 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 928
 929         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 930         sve_size_13 icode to account for variant behaviour of
 931         pmull{t,b}.
 932         * aarch64-dis-2.c: Regenerate.
 933         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 934         sve_size_13 icode to account for variant behaviour of
 935         pmull{t,b}.
 936         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 937         (OP_SVE_VVV_Q_D): Add new qualifier.
 938         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 939         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 940         AES and those not.
 941
 942 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 943
 944         * opcodes/i386-gen.c (operand_type_init): Remove
 945         OPERAND_TYPE_VEC_IMM4 entry.
 946         (operand_types): Remove Vec_Imm4.
 947         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 948         (union i386_operand_type): Remove vec_imm4.
 949         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 950         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 951
 952 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 955         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 956         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 957         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 958         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 959         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 960         * i386-tbl.h: Re-generate.
 961
 962 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 963
 964         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 965         register operands.
 966         * i386-tbl.h: Re-generate.
 967
 968 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 969
 970         * i386-opc.tbl (C): New.
 971         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 972         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 973         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 974         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 975         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 976         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 977         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 978         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 979         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 980         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 981         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 982         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 983         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 984         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 985         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 986         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 987         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 988         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 989         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 990         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 991         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 992         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 993         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 994         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 995         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 996         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 997         flavors.
 998         * i386-tbl.h: Re-generate.
 999
1000 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1001
1002         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1003         register operands.
1004         * i386-tbl.h: Re-generate.
1005
1006 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1007
1008         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1009         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1010         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1011         * i386-tbl.h: Re-generate.
1012
1013 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1014
1015         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1016         Disp8MemShift from register only templates.
1017         * i386-tbl.h: Re-generate.
1018
1019 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1022         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1023         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1024         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1025         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1026         EVEX_W_0F11_P_3_M_1): Delete.
1027         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1028         EVEX_W_0F11_P_3): New.
1029         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1030         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1031         MOD_EVEX_0F11_PREFIX_3 table entries.
1032         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1033         PREFIX_EVEX_0F11 table entries.
1034         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1035         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1036         EVEX_W_0F11_P_3_M_{0,1} table entries.
1037
1038 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1039
1040         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1041         Delete.
1042
1043 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1044
1045         PR binutils/24719
1046         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1047         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1048         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1049         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1050         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1051         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1052         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1053         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1054         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1055         PREFIX_EVEX_0F38C6_REG_6 entries.
1056         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1057         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1058         EVEX_W_0F38C7_R_6_P_2 entries.
1059         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1060         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1061         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1062         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1063         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1064         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1065         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1066
1067 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1068
1069         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1070         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1071         VEX_LEN_0F2D_P_3): Delete.
1072         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1073         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1074         (prefix_table): ... here.
1075
1076 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1077
1078         * i386-dis.c (Iq): Delete.
1079         (Id): New.
1080         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1081         TBM insns.
1082         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1083         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1084         (OP_E_memory): Also honor needindex when deciding whether an
1085         address size prefix needs printing.
1086         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1087
1088 2019-06-26  Jim Wilson  <jimw@sifive.com>
1089
1090         PR binutils/24739
1091         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1092         Set info->display_endian to info->endian_code.
1093
1094 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1095
1096         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1097         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1098         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1099         OPERAND_TYPE_ACC64 entries.
1100         * i386-init.h: Re-generate.
1101
1102 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1103
1104         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1105         Delete.
1106         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1107         of dqa_mode.
1108         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1109         entries here.
1110         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1111         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1112
1113 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1114
1115         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1116         variables.
1117
1118 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1119
1120         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1121         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1122         movnti.
1123         * i386-opc.tbl (movnti): Add IgnoreSize.
1124         * i386-tbl.h: Re-generate.
1125
1126 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1127
1128         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1129         * i386-tbl.h: Re-generate.
1130
1131 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1132
1133         * i386-dis-evex.h: Break into ...
1134         * i386-dis-evex-len.h: New file.
1135         * i386-dis-evex-mod.h: Likewise.
1136         * i386-dis-evex-prefix.h: Likewise.
1137         * i386-dis-evex-reg.h: Likewise.
1138         * i386-dis-evex-w.h: Likewise.
1139         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1140         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1141         i386-dis-evex-mod.h.
1142
1143 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1144
1145         PR binutils/24700
1146         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1147         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1148         EVEX_W_0F385B_P_2.
1149         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1150         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1151         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1152         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1153         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1154         EVEX_LEN_0F385B_P_2_W_1.
1155         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1156         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1157         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1158         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1159         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1160         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1161         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1162         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1163         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1164         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1165
1166 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1167
1168         PR binutils/24691
1169         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1170         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1171         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1172         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1173         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1174         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1175         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1176         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1177         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1178         EVEX_LEN_0F3A43_P_2_W_1.
1179         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1180         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1181         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1182         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1183         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1184         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1185         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1186         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1187         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1188         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1189         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1190         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1191
1192 2019-06-14  Nick Clifton  <nickc@redhat.com>
1193
1194         * po/fr.po; Updated French translation.
1195
1196 2019-06-13  Stafford Horne  <shorne@gmail.com>
1197
1198         * or1k-asm.c: Regenerated.
1199         * or1k-desc.c: Regenerated.
1200         * or1k-desc.h: Regenerated.
1201         * or1k-dis.c: Regenerated.
1202         * or1k-ibld.c: Regenerated.
1203         * or1k-opc.c: Regenerated.
1204         * or1k-opc.h: Regenerated.
1205         * or1k-opinst.c: Regenerated.
1206
1207 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1208
1209         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1210
1211 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1212
1213         PR binutils/24633
1214         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1215         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1216         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1217         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1218         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1219         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1220         EVEX_LEN_0F3A1B_P_2_W_1.
1221         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1222         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1223         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1224         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1225         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1226         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1227         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1228         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1229
1230 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1231
1232         PR binutils/24626
1233         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1234         EVEX.vvvv when disassembling VEX and EVEX instructions.
1235         (OP_VEX): Set vex.register_specifier to 0 after readding
1236         vex.register_specifier.
1237         (OP_Vex_2src_1): Likewise.
1238         (OP_Vex_2src_2): Likewise.
1239         (OP_LWP_E): Likewise.
1240         (OP_EX_Vex): Don't check vex.register_specifier.
1241         (OP_XMM_Vex): Likewise.
1242
1243 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1244             Lili Cui  <lili.cui@intel.com>
1245
1246         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1247         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1248         instructions.
1249         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1250         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1251         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1252         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1253         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1254         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1255         * i386-init.h: Regenerated.
1256         * i386-tbl.h: Likewise.
1257
1258 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1259             Lili Cui  <lili.cui@intel.com>
1260
1261         * doc/c-i386.texi: Document enqcmd.
1262         * testsuite/gas/i386/enqcmd-intel.d: New file.
1263         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1264         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1265         * testsuite/gas/i386/enqcmd.d: Likewise.
1266         * testsuite/gas/i386/enqcmd.s: Likewise.
1267         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1268         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1269         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1270         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1271         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1272         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1273         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1274         and x86-64-enqcmd.
1275
1276 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1277
1278         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1279
1280 2019-06-03  Alan Modra  <amodra@gmail.com>
1281
1282         * ppc-dis.c (prefix_opcd_indices): Correct size.
1283
1284 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1285
1286         PR gas/24625
1287         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1288         Disp8ShiftVL.
1289         * i386-tbl.h: Regenerated.
1290
1291 2019-05-24  Alan Modra  <amodra@gmail.com>
1292
1293         * po/POTFILES.in: Regenerate.
1294
1295 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1296             Alan Modra  <amodra@gmail.com>
1297
1298         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1299         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1300         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1301         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1302         XTOP>): Define and add entries.
1303         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1304         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1305         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1306         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1307
1308 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1309             Alan Modra  <amodra@gmail.com>
1310
1311         * ppc-dis.c (ppc_opts): Add "future" entry.
1312         (PREFIX_OPCD_SEGS): Define.
1313         (prefix_opcd_indices): New array.
1314         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1315         (lookup_prefix): New function.
1316         (print_insn_powerpc): Handle 64-bit prefix instructions.
1317         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1318         (PMRR, POWERXX): Define.
1319         (prefix_opcodes): New instruction table.
1320         (prefix_num_opcodes): New constant.
1321
1322 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1323
1324         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1325         * configure: Regenerated.
1326         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1327         and cpu/bpf.opc.
1328         (HFILES): Add bpf-desc.h and bpf-opc.h.
1329         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1330         bpf-ibld.c and bpf-opc.c.
1331         (BPF_DEPS): Define.
1332         * Makefile.in: Regenerated.
1333         * disassemble.c (ARCH_bpf): Define.
1334         (disassembler): Add case for bfd_arch_bpf.
1335         (disassemble_init_for_target): Likewise.
1336         (enum epbf_isa_attr): Define.
1337         * disassemble.h: extern print_insn_bpf.
1338         * bpf-asm.c: Generated.
1339         * bpf-opc.h: Likewise.
1340         * bpf-opc.c: Likewise.
1341         * bpf-ibld.c: Likewise.
1342         * bpf-dis.c: Likewise.
1343         * bpf-desc.h: Likewise.
1344         * bpf-desc.c: Likewise.
1345
1346 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1347
1348         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1349         and VMSR with the new operands.
1350
1351 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1352
1353         * arm-dis.c (enum mve_instructions): New enum
1354         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1355         and cneg.
1356         (mve_opcodes): New instructions as above.
1357         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1358         csneg and csel.
1359         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1360
1361 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1362
1363         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1364         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1365         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1366         uqshl, urshrl and urshr.
1367         (is_mve_okay_in_it): Add new instructions to TRUE list.
1368         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1369         (print_insn_mve): Updated to accept new %j,
1370         %<bitfield>m and %<bitfield>n patterns.
1371
1372 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1373
1374         * mips-opc.c (mips_builtin_opcodes): Change source register
1375         constraint for DAUI.
1376
1377 2019-05-20  Nick Clifton  <nickc@redhat.com>
1378
1379         * po/fr.po: Updated French translation.
1380
1381 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1382             Michael Collison <michael.collison@arm.com>
1383
1384         * arm-dis.c (thumb32_opcodes): Add new instructions.
1385         (enum mve_instructions): Likewise.
1386         (enum mve_undefined): Add new reasons.
1387         (is_mve_encoding_conflict): Handle new instructions.
1388         (is_mve_undefined): Likewise.
1389         (is_mve_unpredictable): Likewise.
1390         (print_mve_undefined): Likewise.
1391         (print_mve_size): Likewise.
1392
1393 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1394             Michael Collison <michael.collison@arm.com>
1395
1396         * arm-dis.c (thumb32_opcodes): Add new instructions.
1397         (enum mve_instructions): Likewise.
1398         (is_mve_encoding_conflict): Handle new instructions.
1399         (is_mve_undefined): Likewise.
1400         (is_mve_unpredictable): Likewise.
1401         (print_mve_size): Likewise.
1402
1403 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1404             Michael Collison <michael.collison@arm.com>
1405
1406         * arm-dis.c (thumb32_opcodes): Add new instructions.
1407         (enum mve_instructions): Likewise.
1408         (is_mve_encoding_conflict): Likewise.
1409         (is_mve_unpredictable): Likewise.
1410         (print_mve_size): Likewise.
1411
1412 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1413             Michael Collison <michael.collison@arm.com>
1414
1415         * arm-dis.c (thumb32_opcodes): Add new instructions.
1416         (enum mve_instructions): Likewise.
1417         (is_mve_encoding_conflict): Handle new instructions.
1418         (is_mve_undefined): Likewise.
1419         (is_mve_unpredictable): Likewise.
1420         (print_mve_size): Likewise.
1421
1422 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1423             Michael Collison <michael.collison@arm.com>
1424
1425         * arm-dis.c (thumb32_opcodes): Add new instructions.
1426         (enum mve_instructions): Likewise.
1427         (is_mve_encoding_conflict): Handle new instructions.
1428         (is_mve_undefined): Likewise.
1429         (is_mve_unpredictable): Likewise.
1430         (print_mve_size): Likewise.
1431         (print_insn_mve): Likewise.
1432
1433 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1434             Michael Collison <michael.collison@arm.com>
1435
1436         * arm-dis.c (thumb32_opcodes): Add new instructions.
1437         (print_insn_thumb32): Handle new instructions.
1438
1439 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1440             Michael Collison <michael.collison@arm.com>
1441
1442         * arm-dis.c (enum mve_instructions): Add new instructions.
1443         (enum mve_undefined): Add new reasons.
1444         (is_mve_encoding_conflict): Handle new instructions.
1445         (is_mve_undefined): Likewise.
1446         (is_mve_unpredictable): Likewise.
1447         (print_mve_undefined): Likewise.
1448         (print_mve_size): Likewise.
1449         (print_mve_shift_n): Likewise.
1450         (print_insn_mve): Likewise.
1451
1452 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1453             Michael Collison <michael.collison@arm.com>
1454
1455         * arm-dis.c (enum mve_instructions): Add new instructions.
1456         (is_mve_encoding_conflict): Handle new instructions.
1457         (is_mve_unpredictable): Likewise.
1458         (print_mve_rotate): Likewise.
1459         (print_mve_size): Likewise.
1460         (print_insn_mve): Likewise.
1461
1462 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1463             Michael Collison <michael.collison@arm.com>
1464
1465         * arm-dis.c (enum mve_instructions): Add new instructions.
1466         (is_mve_encoding_conflict): Handle new instructions.
1467         (is_mve_unpredictable): Likewise.
1468         (print_mve_size): Likewise.
1469         (print_insn_mve): Likewise.
1470
1471 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1472             Michael Collison <michael.collison@arm.com>
1473
1474         * arm-dis.c (enum mve_instructions): Add new instructions.
1475         (enum mve_undefined): Add new reasons.
1476         (is_mve_encoding_conflict): Handle new instructions.
1477         (is_mve_undefined): Likewise.
1478         (is_mve_unpredictable): Likewise.
1479         (print_mve_undefined): Likewise.
1480         (print_mve_size): Likewise.
1481         (print_insn_mve): Likewise.
1482
1483 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1484             Michael Collison <michael.collison@arm.com>
1485
1486         * arm-dis.c (enum mve_instructions): Add new instructions.
1487         (is_mve_encoding_conflict): Handle new instructions.
1488         (is_mve_undefined): Likewise.
1489         (is_mve_unpredictable): Likewise.
1490         (print_mve_size): Likewise.
1491         (print_insn_mve): Likewise.
1492
1493 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1494             Michael Collison <michael.collison@arm.com>
1495
1496         * arm-dis.c (enum mve_instructions): Add new instructions.
1497         (enum mve_unpredictable): Add new reasons.
1498         (enum mve_undefined): Likewise.
1499         (is_mve_okay_in_it): Handle new isntructions.
1500         (is_mve_encoding_conflict): Likewise.
1501         (is_mve_undefined): Likewise.
1502         (is_mve_unpredictable): Likewise.
1503         (print_mve_vmov_index): Likewise.
1504         (print_simd_imm8): Likewise.
1505         (print_mve_undefined): Likewise.
1506         (print_mve_unpredictable): Likewise.
1507         (print_mve_size): Likewise.
1508         (print_insn_mve): Likewise.
1509
1510 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1511             Michael Collison <michael.collison@arm.com>
1512
1513         * arm-dis.c (enum mve_instructions): Add new instructions.
1514         (enum mve_unpredictable): Add new reasons.
1515         (enum mve_undefined): Likewise.
1516         (is_mve_encoding_conflict): Handle new instructions.
1517         (is_mve_undefined): Likewise.
1518         (is_mve_unpredictable): Likewise.
1519         (print_mve_undefined): Likewise.
1520         (print_mve_unpredictable): Likewise.
1521         (print_mve_rounding_mode): Likewise.
1522         (print_mve_vcvt_size): Likewise.
1523         (print_mve_size): Likewise.
1524         (print_insn_mve): Likewise.
1525
1526 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1527             Michael Collison <michael.collison@arm.com>
1528
1529         * arm-dis.c (enum mve_instructions): Add new instructions.
1530         (enum mve_unpredictable): Add new reasons.
1531         (enum mve_undefined): Likewise.
1532         (is_mve_undefined): Handle new instructions.
1533         (is_mve_unpredictable): Likewise.
1534         (print_mve_undefined): Likewise.
1535         (print_mve_unpredictable): Likewise.
1536         (print_mve_size): Likewise.
1537         (print_insn_mve): Likewise.
1538
1539 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1540             Michael Collison <michael.collison@arm.com>
1541
1542         * arm-dis.c (enum mve_instructions): Add new instructions.
1543         (enum mve_undefined): Add new reasons.
1544         (insns): Add new instructions.
1545         (is_mve_encoding_conflict):
1546         (print_mve_vld_str_addr): New print function.
1547         (is_mve_undefined): Handle new instructions.
1548         (is_mve_unpredictable): Likewise.
1549         (print_mve_undefined): Likewise.
1550         (print_mve_size): Likewise.
1551         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1552         (print_insn_mve):  Handle new operands.
1553
1554 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1555             Michael Collison <michael.collison@arm.com>
1556
1557         * arm-dis.c (enum mve_instructions): Add new instructions.
1558         (enum mve_unpredictable): Add new reasons.
1559         (is_mve_encoding_conflict): Handle new instructions.
1560         (is_mve_unpredictable): Likewise.
1561         (mve_opcodes): Add new instructions.
1562         (print_mve_unpredictable): Handle new reasons.
1563         (print_mve_register_blocks): New print function.
1564         (print_mve_size): Handle new instructions.
1565         (print_insn_mve): Likewise.
1566
1567 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1568             Michael Collison <michael.collison@arm.com>
1569
1570         * arm-dis.c (enum mve_instructions): Add new instructions.
1571         (enum mve_unpredictable): Add new reasons.
1572         (enum mve_undefined): Likewise.
1573         (is_mve_encoding_conflict): Handle new instructions.
1574         (is_mve_undefined): Likewise.
1575         (is_mve_unpredictable): Likewise.
1576         (coprocessor_opcodes): Move NEON VDUP from here...
1577         (neon_opcodes): ... to here.
1578         (mve_opcodes): Add new instructions.
1579         (print_mve_undefined):  Handle new reasons.
1580         (print_mve_unpredictable): Likewise.
1581         (print_mve_size): Handle new instructions.
1582         (print_insn_neon): Handle vdup.
1583         (print_insn_mve): Handle new operands.
1584
1585 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1586             Michael Collison <michael.collison@arm.com>
1587
1588         * arm-dis.c (enum mve_instructions): Add new instructions.
1589         (enum mve_unpredictable): Add new values.
1590         (mve_opcodes): Add new instructions.
1591         (vec_condnames): New array with vector conditions.
1592         (mve_predicatenames): New array with predicate suffixes.
1593         (mve_vec_sizename): New array with vector sizes.
1594         (enum vpt_pred_state): New enum with vector predication states.
1595         (struct vpt_block): New struct type for vpt blocks.
1596         (vpt_block_state): Global struct to keep track of state.
1597         (mve_extract_pred_mask): New helper function.
1598         (num_instructions_vpt_block): Likewise.
1599         (mark_outside_vpt_block): Likewise.
1600         (mark_inside_vpt_block): Likewise.
1601         (invert_next_predicate_state): Likewise.
1602         (update_next_predicate_state): Likewise.
1603         (update_vpt_block_state): Likewise.
1604         (is_vpt_instruction): Likewise.
1605         (is_mve_encoding_conflict): Add entries for new instructions.
1606         (is_mve_unpredictable): Likewise.
1607         (print_mve_unpredictable): Handle new cases.
1608         (print_instruction_predicate): Likewise.
1609         (print_mve_size): New function.
1610         (print_vec_condition): New function.
1611         (print_insn_mve): Handle vpt blocks and new print operands.
1612
1613 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1614
1615         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1616         8, 14 and 15 for Armv8.1-M Mainline.
1617
1618 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1619             Michael Collison <michael.collison@arm.com>
1620
1621         * arm-dis.c (enum mve_instructions): New enum.
1622         (enum mve_unpredictable): Likewise.
1623         (enum mve_undefined): Likewise.
1624         (struct mopcode32): New struct.
1625         (is_mve_okay_in_it): New function.
1626         (is_mve_architecture): Likewise.
1627         (arm_decode_field): Likewise.
1628         (arm_decode_field_multiple): Likewise.
1629         (is_mve_encoding_conflict): Likewise.
1630         (is_mve_undefined): Likewise.
1631         (is_mve_unpredictable): Likewise.
1632         (print_mve_undefined): Likewise.
1633         (print_mve_unpredictable): Likewise.
1634         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1635         (print_insn_mve): New function.
1636         (print_insn_thumb32): Handle MVE architecture.
1637         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1638
1639 2019-05-10  Nick Clifton  <nickc@redhat.com>
1640
1641         PR 24538
1642         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1643         end of the table prematurely.
1644
1645 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1646
1647         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1648         macros for R6.
1649
1650 2019-05-11  Alan Modra  <amodra@gmail.com>
1651
1652         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1653         when -Mraw is in effect.
1654
1655 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1656
1657         * aarch64-dis-2.c: Regenerate.
1658         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1659         (OP_SVE_BBB): New variant set.
1660         (OP_SVE_DDDD): New variant set.
1661         (OP_SVE_HHH): New variant set.
1662         (OP_SVE_HHHU): New variant set.
1663         (OP_SVE_SSS): New variant set.
1664         (OP_SVE_SSSU): New variant set.
1665         (OP_SVE_SHH): New variant set.
1666         (OP_SVE_SBBU): New variant set.
1667         (OP_SVE_DSS): New variant set.
1668         (OP_SVE_DHHU): New variant set.
1669         (OP_SVE_VMV_HSD_BHS): New variant set.
1670         (OP_SVE_VVU_HSD_BHS): New variant set.
1671         (OP_SVE_VVVU_SD_BH): New variant set.
1672         (OP_SVE_VVVU_BHSD): New variant set.
1673         (OP_SVE_VVV_QHD_DBS): New variant set.
1674         (OP_SVE_VVV_HSD_BHS): New variant set.
1675         (OP_SVE_VVV_HSD_BHS2): New variant set.
1676         (OP_SVE_VVV_BHS_HSD): New variant set.
1677         (OP_SVE_VV_BHS_HSD): New variant set.
1678         (OP_SVE_VVV_SD): New variant set.
1679         (OP_SVE_VVU_BHS_HSD): New variant set.
1680         (OP_SVE_VZVV_SD): New variant set.
1681         (OP_SVE_VZVV_BH): New variant set.
1682         (OP_SVE_VZV_SD): New variant set.
1683         (aarch64_opcode_table): Add sve2 instructions.
1684
1685 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1686
1687         * aarch64-asm-2.c: Regenerated.
1688         * aarch64-dis-2.c: Regenerated.
1689         * aarch64-opc-2.c: Regenerated.
1690         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1691         for SVE_SHLIMM_UNPRED_22.
1692         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1693         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1694         operand.
1695
1696 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1697
1698         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1699         sve_size_tsz_bhs iclass encode.
1700         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1701         sve_size_tsz_bhs iclass decode.
1702
1703 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1704
1705         * aarch64-asm-2.c: Regenerated.
1706         * aarch64-dis-2.c: Regenerated.
1707         * aarch64-opc-2.c: Regenerated.
1708         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1709         for SVE_Zm4_11_INDEX.
1710         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1711         (fields): Handle SVE_i2h field.
1712         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1713         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1714
1715 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1716
1717         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1718         sve_shift_tsz_bhsd iclass encode.
1719         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1720         sve_shift_tsz_bhsd iclass decode.
1721
1722 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1723
1724         * aarch64-asm-2.c: Regenerated.
1725         * aarch64-dis-2.c: Regenerated.
1726         * aarch64-opc-2.c: Regenerated.
1727         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1728         (aarch64_encode_variant_using_iclass): Handle
1729         sve_shift_tsz_hsd iclass encode.
1730         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1731         sve_shift_tsz_hsd iclass decode.
1732         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1733         for SVE_SHRIMM_UNPRED_22.
1734         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1735         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1736         operand.
1737
1738 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1739
1740         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1741         sve_size_013 iclass encode.
1742         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1743         sve_size_013 iclass decode.
1744
1745 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1746
1747         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1748         sve_size_bh iclass encode.
1749         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1750         sve_size_bh iclass decode.
1751
1752 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1753
1754         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1755         sve_size_sd2 iclass encode.
1756         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1757         sve_size_sd2 iclass decode.
1758         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1759         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1760
1761 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1762
1763         * aarch64-asm-2.c: Regenerated.
1764         * aarch64-dis-2.c: Regenerated.
1765         * aarch64-opc-2.c: Regenerated.
1766         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1767         for SVE_ADDR_ZX.
1768         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1769         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1770
1771 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1772
1773         * aarch64-asm-2.c: Regenerated.
1774         * aarch64-dis-2.c: Regenerated.
1775         * aarch64-opc-2.c: Regenerated.
1776         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1777         for SVE_Zm3_11_INDEX.
1778         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1779         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1780         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1781         fields.
1782         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1783
1784 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1785
1786         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1787         sve_size_hsd2 iclass encode.
1788         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1789         sve_size_hsd2 iclass decode.
1790         * aarch64-opc.c (fields): Handle SVE_size field.
1791         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1792
1793 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1794
1795         * aarch64-asm-2.c: Regenerated.
1796         * aarch64-dis-2.c: Regenerated.
1797         * aarch64-opc-2.c: Regenerated.
1798         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1799         for SVE_IMM_ROT3.
1800         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1801         (fields): Handle SVE_rot3 field.
1802         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1803         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1804
1805 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1806
1807         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1808         instructions.
1809
1810 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1811
1812         * aarch64-tbl.h
1813         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1814         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1815         aarch64_feature_sve2bitperm): New feature sets.
1816         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1817         for feature set addresses.
1818         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1819         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1820
1821 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1822             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1823
1824         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1825         argument and set ASE_EVA_R6 appropriately.
1826         (set_default_mips_dis_options): Pass ISA to above.
1827         (parse_mips_dis_option): Likewise.
1828         * mips-opc.c (EVAR6): New macro.
1829         (mips_builtin_opcodes): Add llwpe, scwpe.
1830
1831 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1832
1833         * aarch64-asm-2.c: Regenerated.
1834         * aarch64-dis-2.c: Regenerated.
1835         * aarch64-opc-2.c: Regenerated.
1836         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1837         AARCH64_OPND_TME_UIMM16.
1838         (aarch64_print_operand): Likewise.
1839         * aarch64-tbl.h (QL_IMM_NIL): New.
1840         (TME): New.
1841         (_TME_INSN): New.
1842         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1843
1844 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1845
1846         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1847
1848 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1849             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1850
1851         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1852
1853 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1854
1855         * s12z-opc.h: Add extern "C" bracketing to help
1856         users who wish to use this interface in c++ code.
1857
1858 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1859
1860         * s12z-opc.c (bm_decode): Handle bit map operations with the
1861         "reserved0" mode.
1862
1863 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1864
1865         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1866         specifier.  Add entries for VLDR and VSTR of system registers.
1867         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1868         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1869         of %J and %K format specifier.
1870
1871 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1872
1873         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1874         Add new entries for VSCCLRM instruction.
1875         (print_insn_coprocessor): Handle new %C format control code.
1876
1877 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1878
1879         * arm-dis.c (enum isa): New enum.
1880         (struct sopcode32): New structure.
1881         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1882         set isa field of all current entries to ANY.
1883         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1884         Only match an entry if its isa field allows the current mode.
1885
1886 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1887
1888         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1889         CLRM.
1890         (print_insn_thumb32): Add logic to print %n CLRM register list.
1891
1892 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1893
1894         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1895         and %Q patterns.
1896
1897 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1898
1899         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1900         (print_insn_thumb32): Edit the switch case for %Z.
1901
1902 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1903
1904         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1905
1906 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1907
1908         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1909
1910 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1911
1912         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1913
1914 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1915
1916         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1917         Arm register with r13 and r15 unpredictable.
1918         (thumb32_opcodes): New instructions for bfx and bflx.
1919
1920 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1921
1922         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1923
1924 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1925
1926         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1927
1928 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1929
1930         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1931
1932 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1933
1934         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1935
1936 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1937
1938         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1939         "optr". ("operator" is a reserved word in c++).
1940
1941 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1942
1943         * aarch64-opc.c (aarch64_print_operand): Add case for
1944         AARCH64_OPND_Rt_SP.
1945         (verify_constraints): Likewise.
1946         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1947         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1948         to accept Rt|SP as first operand.
1949         (AARCH64_OPERANDS): Add new Rt_SP.
1950         * aarch64-asm-2.c: Regenerated.
1951         * aarch64-dis-2.c: Regenerated.
1952         * aarch64-opc-2.c: Regenerated.
1953
1954 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1955
1956         * aarch64-asm-2.c: Regenerated.
1957         * aarch64-dis-2.c: Likewise.
1958         * aarch64-opc-2.c: Likewise.
1959         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1960
1961 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1962
1963         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1964
1965 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1966
1967         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1968         * i386-init.h: Regenerated.
1969
1970 2019-04-07  Alan Modra  <amodra@gmail.com>
1971
1972         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1973         op_separator to control printing of spaces, comma and parens
1974         rather than need_comma, need_paren and spaces vars.
1975
1976 2019-04-07  Alan Modra  <amodra@gmail.com>
1977
1978         PR 24421
1979         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1980         (print_insn_neon, print_insn_arm): Likewise.
1981
1982 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1983
1984         * i386-dis-evex.h (evex_table): Updated to support BF16
1985         instructions.
1986         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1987         and EVEX_W_0F3872_P_3.
1988         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1989         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1990         * i386-opc.h (enum): Add CpuAVX512_BF16.
1991         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1992         * i386-opc.tbl: Add AVX512 BF16 instructions.
1993         * i386-init.h: Regenerated.
1994         * i386-tbl.h: Likewise.
1995
1996 2019-04-05  Alan Modra  <amodra@gmail.com>
1997
1998         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1999         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2000         to favour printing of "-" branch hint when using the "y" bit.
2001         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2002
2003 2019-04-05  Alan Modra  <amodra@gmail.com>
2004
2005         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2006         opcode until first operand is output.
2007
2008 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2009
2010         PR gas/24349
2011         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2012         (valid_bo_post_v2): Add support for 'at' branch hints.
2013         (insert_bo): Only error on branch on ctr.
2014         (get_bo_hint_mask): New function.
2015         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2016         for inserting 'at' branch hints.
2017         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2018         for extracting 'at' branch hints.
2019         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2020         (BOE): Delete operand.
2021         (BOM, BOP): New operands.
2022         (RM): Update value.
2023         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2024         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2025         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2026         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2027         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2028         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2029         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2030         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2031         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2032         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2033         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2034         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2035         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2036         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2037         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2038         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2039         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2040         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2041         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2042         bttarl+>: New extended mnemonics.
2043
2044 2019-03-28  Alan Modra  <amodra@gmail.com>
2045
2046         PR 24390
2047         * ppc-opc.c (BTF): Define.
2048         (powerpc_opcodes): Use for mtfsb*.
2049         * ppc-dis.c (print_insn_powerpc): Print fields with both
2050         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2051
2052 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2053
2054         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2055         (mapping_symbol_for_insn): Implement new algorithm.
2056         (print_insn): Remove duplicate code.
2057
2058 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2059
2060         * aarch64-dis.c (print_insn_aarch64):
2061         Implement override.
2062
2063 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2064
2065         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2066         order.
2067
2068 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2069
2070         * aarch64-dis.c (last_stop_offset): New.
2071         (print_insn_aarch64): Use stop_offset.
2072
2073 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2074
2075         PR gas/24359
2076         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2077         CPU_ANY_AVX2_FLAGS.
2078         * i386-init.h: Regenerated.
2079
2080 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2081
2082         PR gas/24348
2083         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2084         vmovdqu16, vmovdqu32 and vmovdqu64.
2085         * i386-tbl.h: Regenerated.
2086
2087 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2088
2089         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2090         from vstrszb, vstrszh, and vstrszf.
2091
2092 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2093
2094         * s390-opc.txt: Add instruction descriptions.
2095
2096 2019-02-08  Jim Wilson  <jimw@sifive.com>
2097
2098         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2099         <bne>: Likewise.
2100
2101 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2102
2103         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2104
2105 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2106
2107         PR binutils/23212
2108         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2109         * aarch64-opc.c (verify_elem_sd): New.
2110         (fields): Add FLD_sz entr.
2111         * aarch64-tbl.h (_SIMD_INSN): New.
2112         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2113         fmulx scalar and vector by element isns.
2114
2115 2019-02-07  Nick Clifton  <nickc@redhat.com>
2116
2117         * po/sv.po: Updated Swedish translation.
2118
2119 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2120
2121         * s390-mkopc.c (main): Accept arch13 as cpu string.
2122         * s390-opc.c: Add new instruction formats and instruction opcode
2123         masks.
2124         * s390-opc.txt: Add new arch13 instructions.
2125
2126 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2127
2128         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2129         (aarch64_opcode): Change encoding for stg, stzg
2130         st2g and st2zg.
2131         * aarch64-asm-2.c: Regenerated.
2132         * aarch64-dis-2.c: Regenerated.
2133         * aarch64-opc-2.c: Regenerated.
2134
2135 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2136
2137         * aarch64-asm-2.c: Regenerated.
2138         * aarch64-dis-2.c: Likewise.
2139         * aarch64-opc-2.c: Likewise.
2140         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2141
2142 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2143             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2144
2145         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2146         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2147         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2148         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2149         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2150         case for ldstgv_indexed.
2151         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2152         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2153         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2154         * aarch64-asm-2.c: Regenerated.
2155         * aarch64-dis-2.c: Regenerated.
2156         * aarch64-opc-2.c: Regenerated.
2157
2158 2019-01-23  Nick Clifton  <nickc@redhat.com>
2159
2160         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2161
2162 2019-01-21  Nick Clifton  <nickc@redhat.com>
2163
2164         * po/de.po: Updated German translation.
2165         * po/uk.po: Updated Ukranian translation.
2166
2167 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2168         * mips-dis.c (mips_arch_choices): Fix typo in
2169         gs464, gs464e and gs264e descriptors.
2170
2171 2019-01-19  Nick Clifton  <nickc@redhat.com>
2172
2173         * configure: Regenerate.
2174         * po/opcodes.pot: Regenerate.
2175
2176 2018-06-24  Nick Clifton  <nickc@redhat.com>
2177
2178         2.32 branch created.
2179
2180 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2181
2182         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2183         if it is null.
2184         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2185         zero.
2186
2187 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2188
2189         * configure: Regenerate.
2190
2191 2019-01-07  Alan Modra  <amodra@gmail.com>
2192
2193         * configure: Regenerate.
2194         * po/POTFILES.in: Regenerate.
2195
2196 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2197
2198         * s12z-opc.c: New file.
2199         * s12z-opc.h: New file.
2200         * s12z-dis.c: Removed all code not directly related to display
2201         of instructions.  Used the interface provided by the new files
2202         instead.
2203         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2204         * Makefile.in: Regenerate.
2205         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2206         * configure: Regenerate.
2207
2208 2019-01-01  Alan Modra  <amodra@gmail.com>
2209
2210         Update year range in copyright notice of all files.
2211
2212 For older changes see ChangeLog-2018
2213 \f
2214 Copyright (C) 2019 Free Software Foundation, Inc.
2215
2216 Copying and distribution of this file, with or without modification,
2217 are permitted in any medium without royalty provided the copyright
2218 notice and this notice are preserved.
2219
2220 Local Variables:
2221 mode: change-log
2222 left-margin: 8
2223 fill-column: 74
2224 version-control: never
2225 End: