opcodes/ChangeLog

   1 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
   4         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
   5         Use +H rather than +C for the real "dext".
   6         * mips-opc.c (mips_builtin_opcodes): Likewise.
   7
   8 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
   9
  10         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
  11         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
  12         and OPTIONAL_MAPPED_REG.
  13         * mips-opc.c (decode_mips_operand): Likewise.
  14         * mips16-opc.c (decode_mips16_operand): Likewise.
  15         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
  16
  17 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
  18
  19         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
  20         (PREFIX_EVEX_0F3A3F): Likewise.
  21         * i386-dis-evex.h (evex_table): Updated.
  22
  23 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
  24
  25         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
  26         VCLIPW.
  27
  28 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
  29             Konrad Eisele  <konrad@gaisler.com>
  30
  31         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
  32         bfd_mach_sparc.
  33         * sparc-opc.c (MASK_LEON): Define.
  34         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
  35         (letandleon): New macro.
  36         (v9andleon): Likewise.
  37         (sparc_opc): Add leon.
  38         (umac): Enable for letandleon.
  39         (smac): Likewise.
  40         (casa): Enable for v9andleon.
  41         (cas): Likewise.
  42         (casl): Likewise.
  43
  44 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
  45             Richard Sandiford  <rdsandiford@googlemail.com>
  46
  47         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
  48         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
  49         (print_vu0_channel): New function.
  50         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
  51         (print_insn_args): Handle '#'.
  52         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
  53         * mips-opc.c (mips_vu0_channel_mask): New constant.
  54         (decode_mips_operand): Handle new VU0 operand types.
  55         (VU0, VU0CH): New macros.
  56         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
  57         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
  58         Use "+6" rather than "G" for QMFC2 and QMTC2.
  59
  60 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
  61
  62         * mips-formats.h (PCREL): Reorder parameters and update the definition
  63         to match new mips_pcrel_operand layout.
  64         (JUMP, JALX, BRANCH): Update accordingly.
  65         * mips16-opc.c (decode_mips16_operand): Likewise.
  66
  67 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  68
  69         * micromips-opc.c (WR_s): Delete.
  70
  71 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  72
  73         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
  74         New macros.
  75         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
  76         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
  77         (mips_builtin_opcodes): Use the new position-based read-write flags
  78         instead of field-based ones.  Use UDI for "udi..." instructions.
  79         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
  80         New macros.
  81         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
  82         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
  83         (WR_SP, RD_16): New macros.
  84         (RD_SP): Redefine as an INSN2_* flag.
  85         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
  86         (mips16_opcodes): Use the new position-based read-write flags
  87         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
  88         pinfo2 field.
  89         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
  90         New macros.
  91         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
  92         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
  93         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
  94         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
  95         (micromips_opcodes): Use the new position-based read-write flags
  96         instead of field-based ones.
  97         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
  98         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
  99         of field-based flags.
 100
 101 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 102
 103         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 104         (WR_SP): Replace with...
 105         (MOD_SP): ...this.
 106         (mips16_opcodes): Update accordingly.
 107         * mips-dis.c (print_insn_mips16): Likewise.
 108
 109 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 110
 111         * mips16-opc.c (mips16_opcodes): Reformat.
 112
 113 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 114
 115         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 116         for operands that are hard-coded to $0.
 117         * micromips-opc.c (micromips_opcodes): Likewise.
 118
 119 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 120
 121         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 122         for the single-operand forms of JALR and JALR.HB.
 123         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 124         and JALRS.HB.
 125
 126 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 127
 128         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 129         instructions.  Fix them to use WR_MACC instead of WR_CC and
 130         add missing RD_MACCs.
 131
 132 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 133
 134         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 135
 136 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 137
 138         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 139
 140 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 141             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 142             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 143             Sergey Lega  <sergey.s.lega@intel.com>
 144             Anna Tikhonova  <anna.tikhonova@intel.com>
 145             Ilya Tocar  <ilya.tocar@intel.com>
 146             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 147             Ilya Verbin  <ilya.verbin@intel.com>
 148             Kirill Yukhin  <kirill.yukhin@intel.com>
 149             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 150
 151         * i386-dis-evex.h: New.
 152         * i386-dis.c (OP_Rounding): New.
 153         (VPCMP_Fixup): New.
 154         (OP_Mask): New.
 155         (Rdq): New.
 156         (XMxmmq): New.
 157         (EXdScalarS): New.
 158         (EXymm): New.
 159         (EXEvexHalfBcstXmmq): New.
 160         (EXxmm_mdq): New.
 161         (EXEvexXGscat): New.
 162         (EXEvexXNoBcst): New.
 163         (VPCMP): New.
 164         (EXxEVexR): New.
 165         (EXxEVexS): New.
 166         (XMask): New.
 167         (MaskG): New.
 168         (MaskE): New.
 169         (MaskR): New.
 170         (MaskVex): New.
 171         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 172         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 173         evex_rounding_mode, evex_sae_mode, mask_mode.
 174         (USE_EVEX_TABLE): New.
 175         (EVEX_TABLE): New.
 176         (EVEX enum): New.
 177         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 178         REG_EVEX_0F38C7.
 179         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 180         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 181         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 182         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 183         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 184         MOD_EVEX_0F38C7_REG_6.
 185         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 186         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 187         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 188         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 189         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 190         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 191         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 192         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 193         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 194         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 195         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 196         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 197         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 198         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 199         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 200         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 201         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 202         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 203         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 204         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 205         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 206         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 207         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 208         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 209         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 210         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 211         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 212         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 213         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 214         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 215         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 216         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 217         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 218         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 219         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 220         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 221         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 222         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 223         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 224         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 225         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 226         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 227         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 228         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 229         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 230         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 231         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 232         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 233         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 234         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 235         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 236         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 237         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 238         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 239         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 240         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 241         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 242         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 243         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 244         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 245         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 246         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 247         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 248         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 249         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 250         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 251         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 252         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 253         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 254         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 255         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 256         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 257         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 258         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 259         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 260         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 261         PREFIX_EVEX_0F3A55.
 262         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 263         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 264         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 265         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 266         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 267         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 268         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 269         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 270         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 271         VEX_W_0F3A32_P_2_LEN_0.
 272         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 273         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 274         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 275         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 276         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 277         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 278         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 279         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 280         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 281         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 282         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 283         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 284         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 285         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 286         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 287         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 288         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 289         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 290         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 291         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 292         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 293         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 294         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 295         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 296         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 297         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 298         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 299         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 300         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 301         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 302         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 303         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 304         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 305         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 306         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 307         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 308         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 309         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 310         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 311         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 312         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 313         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 314         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 315         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 316         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 317         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 318         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 319         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 320         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 321         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 322         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 323         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 324         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 325         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 326         (struct vex): Add fields evex, r, v, mask_register_specifier,
 327         zeroing, ll, b.
 328         (intel_names_xmm): Add upper 16 registers.
 329         (att_names_xmm): Ditto.
 330         (intel_names_ymm): Ditto.
 331         (att_names_ymm): Ditto.
 332         (names_zmm): New.
 333         (intel_names_zmm): Ditto.
 334         (att_names_zmm): Ditto.
 335         (names_mask): Ditto.
 336         (intel_names_mask): Ditto.
 337         (att_names_mask): Ditto.
 338         (names_rounding): Ditto.
 339         (names_broadcast): Ditto.
 340         (x86_64_table): Add escape to evex-table.
 341         (reg_table): Include reg_table evex-entries from
 342         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 343         (prefix_table): Add entries for new instructions.
 344         (vex_table): Ditto.
 345         (vex_len_table): Ditto.
 346         (vex_w_table): Ditto.
 347         (mod_table): Ditto.
 348         (get_valid_dis386): Properly handle new instructions.
 349         (print_insn): Handle zmm and mask registers, print mask operand.
 350         (intel_operand_size): Support EVEX, new modes and sizes.
 351         (OP_E_register): Handle new modes.
 352         (OP_E_memory): Ditto.
 353         (OP_G): Ditto.
 354         (OP_XMM): Ditto.
 355         (OP_EX): Ditto.
 356         (OP_VEX): Ditto.
 357         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 358         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 359         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 360         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 361         CpuAVX512PF and CpuVREX.
 362         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 363         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 364         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 365         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 366         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 367         * i386-init.h: Regenerate.
 368         * i386-opc.h (CpuAVX512F): New.
 369         (CpuAVX512CD): New.
 370         (CpuAVX512ER): New.
 371         (CpuAVX512PF): New.
 372         (CpuVREX): New.
 373         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 374         cpuavx512pf and cpuvrex fields.
 375         (VecSIB): Add VecSIB512.
 376         (EVex): New.
 377         (Masking): New.
 378         (VecESize): New.
 379         (Broadcast): New.
 380         (StaticRounding): New.
 381         (SAE): New.
 382         (Disp8MemShift): New.
 383         (NoDefMask): New.
 384         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 385         staticrounding, sae, disp8memshift and nodefmask.
 386         (RegZMM): New.
 387         (Zmmword): Ditto.
 388         (Vec_Disp8): Ditto.
 389         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 390         fields.
 391         (RegVRex): New.
 392         * i386-opc.tbl: Add AVX512 instructions.
 393         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 394         registers, mask registers.
 395         * i386-tbl.h: Regenerate.
 396
 397 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 398
 399         PR gas/15220
 400         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 401         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 402
 403 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 404
 405         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 406         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 407         PREFIX_0F3ACC.
 408         (prefix_table): Updated.
 409         (three_byte_table): Likewise.
 410         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 411         (cpu_flags): Add CpuSHA.
 412         (i386_cpu_flags): Add cpusha.
 413         * i386-init.h: Regenerate.
 414         * i386-opc.h (CpuSHA): New.
 415         (CpuUnused): Restored.
 416         (i386_cpu_flags): Add cpusha.
 417         * i386-opc.tbl: Add SHA instructions.
 418         * i386-tbl.h: Regenerate.
 419
 420 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 421             Kirill Yukhin  <kirill.yukhin@intel.com>
 422             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 423
 424         * i386-dis.c (BND_Fixup): New.
 425         (Ebnd): New.
 426         (Ev_bnd): New.
 427         (Gbnd): New.
 428         (BND): New.
 429         (v_bnd_mode): New.
 430         (bnd_mode): New.
 431         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 432         MOD_0F1B_PREFIX_1.
 433         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 434         (dis tables): Replace XX with BND for near branch and call
 435         instructions.
 436         (prefix_table): Add new entries.
 437         (mod_table): Likewise.
 438         (names_bnd): New.
 439         (intel_names_bnd): New.
 440         (att_names_bnd): New.
 441         (BND_PREFIX): New.
 442         (prefix_name): Handle BND_PREFIX.
 443         (print_insn): Initialize names_bnd.
 444         (intel_operand_size): Handle new modes.
 445         (OP_E_register): Likewise.
 446         (OP_E_memory): Likewise.
 447         (OP_G): Likewise.
 448         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 449         (cpu_flags): Add CpuMPX.
 450         (operand_type_init): Add RegBND.
 451         (opcode_modifiers): Add BNDPrefixOk.
 452         (operand_types): Add RegBND.
 453         * i386-init.h: Regenerate.
 454         * i386-opc.h (CpuMPX): New.
 455         (CpuUnused): Comment out.
 456         (i386_cpu_flags): Add cpumpx.
 457         (BNDPrefixOk): New.
 458         (i386_opcode_modifier): Add bndprefixok.
 459         (RegBND): New.
 460         (i386_operand_type): Add regbnd.
 461         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 462         Add MPX instructions and bnd prefix.
 463         * i386-reg.tbl: Add bnd0-bnd3 registers.
 464         * i386-tbl.h: Regenerate.
 465
 466 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 467
 468         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 469         ATTRIBUTE_UNUSED.
 470
 471 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 472
 473         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 474         special rules.
 475         * Makefile.in: Regenerate.
 476         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 477         all fields.  Reformat.
 478
 479 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 480
 481         * mips16-opc.c: Include mips-formats.h.
 482         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 483         static arrays.
 484         (decode_mips16_operand): New function.
 485         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 486         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 487         Abort for OP_SAVE_RESTORE_LIST.
 488         (print_mips16_insn_arg): Change interface.  Use mips_operand
 489         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 490         (print_insn_mips16): ...here.  Call init_print_arg_state.
 491         Update the call to print_mips16_insn_arg.
 492
 493 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 494
 495         * mips-formats.h: New file.
 496         * mips-opc.c: Include mips-formats.h.
 497         (reg_0_map): New static array.
 498         (decode_mips_operand): New function.
 499         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 500         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 501         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 502         (int_c_map): New static arrays.
 503         (decode_micromips_operand): New function.
 504         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 505         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 506         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 507         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 508         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 509         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 510         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 511         (print_reg): New function.
 512         (mips_print_arg_state): New structure.
 513         (init_print_arg_state, print_insn_arg): New functions.
 514         (print_insn_args): Change interface and use mips_operand structures.
 515         Delete GET_OP_S.  Move GET_OP definition to...
 516         (print_insn_mips): ...here.  Update the call to print_insn_args.
 517         (print_insn_micromips): Use print_insn_args.
 518
 519 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 520
 521         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 522         in macros.
 523
 524 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 525
 526         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 527         ADDA.S, MULA.S and SUBA.S.
 528
 529 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 530
 531         PR gas/13572
 532         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 533         * i386-tbl.h: Regenerated.
 534
 535 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 536
 537         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 538         and SD A(B) macros up.
 539         * micromips-opc.c (micromips_opcodes): Likewise.
 540
 541 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 542
 543         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 544         instructions.
 545
 546 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 547
 548         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 549         MDMX-like instructions.
 550         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 551         printing "Q" operands for INSN_5400 instructions.
 552
 553 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 554
 555         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 556         "+S" for "cins".
 557         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 558         Combine cases.
 559
 560 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 561
 562         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 563         "jalx".
 564         * mips16-opc.c (mips16_opcodes): Likewise.
 565         * micromips-opc.c (micromips_opcodes): Likewise.
 566         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 567         (print_insn_mips16): Handle "+i".
 568         (print_insn_micromips): Likewise.  Conditionally preserve the
 569         ISA bit for "a" but not for "+i".
 570
 571 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 572
 573         * micromips-opc.c (WR_mhi): Rename to..
 574         (WR_mh): ...this.
 575         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 576         "mh,mi" with "mh".
 577         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 578         (micromips_to_32_reg_h_map1): ...this.
 579         (micromips_to_32_reg_i_map): Rename to...
 580         (micromips_to_32_reg_h_map2): ...this.
 581         (print_micromips_insn): Remove "mi" case.  Print both registers
 582         in the pair for "mh".
 583
 584 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 585
 586         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 587         * micromips-opc.c (micromips_opcodes): Likewise.
 588         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 589         and "+T" handling.  Check for a "0" suffix when deciding whether to
 590         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 591
 592 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 593
 594         * s390-opc.c (J12_12, J24_24): New macros.
 595         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 596         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 597         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 598
 599 2013-07-04  Alan Modra  <amodra@gmail.com>
 600
 601         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 602
 603 2013-06-26  Nick Clifton  <nickc@redhat.com>
 604
 605         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 606         field when checking for type 2 nop.
 607         * rx-decode.c: Regenerate.
 608
 609 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 610
 611         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 612         and "movep" macros.
 613
 614 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 615
 616         * mips-dis.c (is_mips16_plt_tail): New function.
 617         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 618         word.
 619         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 620
 621 2013-06-21  DJ Delorie  <dj@redhat.com>
 622
 623         * msp430-decode.opc: New.
 624         * msp430-decode.c: New/generated.
 625         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 626         (MAINTAINER_CLEANFILES): Likewise.
 627         Add rule to build msp430-decode.c frommsp430decode.opc
 628         using the opc2c program.
 629         * Makefile.in: Regenerate.
 630         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 631         * configure: Regenerate.
 632
 633 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 634
 635         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 636         (SYMTAB_AVAILABLE): Removed.
 637         (#include "elf/aarch64.h): Ditto.
 638
 639 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 640             Maciej W. Rozycki  <macro@codesourcery.com>
 641             Chao-Ying Fu  <fu@mips.com>
 642
 643         * micromips-opc.c (EVA): Define.
 644         (TLBINV): Define.
 645         (micromips_opcodes): Add EVA opcodes.
 646         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 647         (print_insn_args): Handle EVA offsets.
 648         (print_insn_micromips): Likewise.
 649         * mips-opc.c (EVA): Define.
 650         (TLBINV): Define.
 651         (mips_builtin_opcodes): Add EVA opcodes.
 652
 653 2013-06-17  Alan Modra  <amodra@gmail.com>
 654
 655         * Makefile.am (mips-opc.lo): Add rules to create automatic
 656         dependency files.  Pass archdefs.
 657         (micromips-opc.lo, mips16-opc.lo): Likewise.
 658         * Makefile.in: Regenerate.
 659
 660 2013-06-14  DJ Delorie  <dj@redhat.com>
 661
 662         * rx-decode.opc (rx_decode_opcode): Bit operations on
 663         registers are 32-bit operations, not 8-bit operations.
 664         * rx-decode.c: Regenerate.
 665
 666 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 667
 668         * micromips-opc.c (IVIRT): New define.
 669         (IVIRT64): New define.
 670         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 671         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 672
 673         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 674         dmtgc0 to print cp0 names.
 675
 676 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 677
 678         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 679         argument.
 680
 681 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 682             Richard Sandiford  <rdsandiford@googlemail.com>
 683
 684         * micromips-opc.c (D32, D33, MC): Update definitions.
 685         (micromips_opcodes):  Initialize ase field.
 686         * mips-dis.c (mips_arch_choice): Add ase field.
 687         (mips_arch_choices): Initialize ase field.
 688         (set_default_mips_dis_options): Declare and setup mips_ase.
 689         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 690         MT32, MC): Update definitions.
 691         (mips_builtin_opcodes): Initialize ase field.
 692
 693 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 694
 695         * s390-opc.txt (flogr): Require a register pair destination.
 696
 697 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 698
 699         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 700         instruction format.
 701
 702 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 703
 704         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 705
 706 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 707
 708         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 709         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 710         XLS_MASK, PPCVSX2): New defines.
 711         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 712         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 713         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 714         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 715         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 716         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 717         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 718         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 719         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 720         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 721         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 722         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 723         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 724         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 725         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 726         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 727         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 728         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 729         <lxvx, stxvx>: New extended mnemonics.
 730
 731 2013-05-17  Alan Modra  <amodra@gmail.com>
 732
 733         * ia64-raw.tbl: Replace non-ASCII char.
 734         * ia64-waw.tbl: Likewise.
 735         * ia64-asmtab.c: Regenerate.
 736
 737 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 738
 739         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 740         * i386-init.h: Regenerated.
 741
 742 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 743
 744         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 745         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 746         check from [0, 255] to [-128, 255].
 747
 748 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 749
 750         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 751         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 752         (parse_mips_dis_option): Handle the virt option.
 753         (print_insn_args): Handle "+J".
 754         (print_mips_disassembler_options): Print out message about virt64.
 755         * mips-opc.c (IVIRT): New define.
 756         (IVIRT64): New define.
 757         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 758         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 759         Move rfe to the bottom as it conflicts with tlbgp.
 760
 761 2013-05-09  Alan Modra  <amodra@gmail.com>
 762
 763         * ppc-opc.c (extract_vlesi): Properly sign extend.
 764         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 765
 766 2013-05-02  Nick Clifton  <nickc@redhat.com>
 767
 768         * msp430-dis.c: Add support for MSP430X instructions.
 769
 770 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 771
 772         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 773         to "eccinj".
 774
 775 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 776
 777         PR binutils/15369
 778         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 779         of CGEN_CPU_ENDIAN.
 780         (hash_insns_list): Likewise.
 781
 782 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 783
 784         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 785         warning workaround.
 786
 787 2013-04-08  Jan Beulich <jbeulich@suse.com>
 788
 789         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 790         * i386-tbl.h: Re-generate.
 791
 792 2013-04-06  David S. Miller  <davem@davemloft.net>
 793
 794         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 795         of an opcode, prefer the one with F_PREFERRED set.
 796         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 797         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 798         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 799         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 800         instructions generating condition codes, mark existing mnenomics
 801         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 802         existing mnenomics as aliases.
 803
 804 2013-04-03  Nick Clifton  <nickc@redhat.com>
 805
 806         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 807         destination address by subtracting the operand from the current
 808         address.
 809         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 810         a positive value in the insn.
 811         (extract_u16_loop): Do not negate the returned value.
 812         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 813
 814         (ceilf.sw): Remove duplicate entry.
 815         (cvtf.hs): New entry.
 816         (cvtf.sh): Likewise.
 817         (fmaf.s): Likewise.
 818         (fmsf.s): Likewise.
 819         (fnmaf.s): Likewise.
 820         (fnmsf.s): Likewise.
 821         (maddf.s): Restrict to E3V5 architectures.
 822         (msubf.s): Likewise.
 823         (nmaddf.s): Likewise.
 824         (nmsubf.s): Likewise.
 825
 826 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 827
 828         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 829         check address mode.
 830         (print_insn): Pass sizeflag to get_sib.
 831
 832 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 833
 834         PR binutils/15068
 835         * tic6x-dis.c: Add support for displaying 16-bit insns.
 836
 837 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 838
 839         PR gas/15095
 840         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 841         individual msb and lsb halves in src1 & src2 fields.  Discard the
 842         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 843         follow what Ti SDK does in that case as any value in the src1
 844         field yields the same output with SDK disassembler.
 845
 846 2013-03-12  Michael Eager <eager@eagercon.com>
 847
 848         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 849
 850 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 851
 852         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 853
 854 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 855
 856         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 857
 858 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 859
 860         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 861
 862 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 863
 864         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 865         (thumb32_opcodes): Likewise.
 866         (print_insn_thumb32): Handle 'S' control char.
 867
 868 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 869
 870         * lm32-desc.c: Regenerate.
 871
 872 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 873
 874         * i386-reg.tbl (riz): Add RegRex64.
 875         * i386-tbl.h: Regenerated.
 876
 877 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 878
 879         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 880         (aarch64_feature_crc): New static.
 881         (CRC): New macro.
 882         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 883         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 884         * aarch64-asm-2.c: Re-generate.
 885         * aarch64-dis-2.c: Ditto.
 886         * aarch64-opc-2.c: Ditto.
 887
 888 2013-02-27  Alan Modra  <amodra@gmail.com>
 889
 890         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 891         * rl78-decode.c: Regenerate.
 892
 893 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 894
 895         * rl78-decode.opc: Fix encoding of DIVWU insn.
 896         * rl78-decode.c: Regenerate.
 897
 898 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 899
 900         PR gas/15159
 901         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 902
 903         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 904         (cpu_flags): Add CpuSMAP.
 905
 906         * i386-opc.h (CpuSMAP): New.
 907         (i386_cpu_flags): Add cpusmap.
 908
 909         * i386-opc.tbl: Add clac and stac.
 910
 911         * i386-init.h: Regenerated.
 912         * i386-tbl.h: Likewise.
 913
 914 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 915
 916         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 917         which also makes the disassembler output be in little
 918         endian like it should be.
 919
 920 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 921
 922         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 923         fields to NULL.
 924         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 925
 926 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 927
 928         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 929         section disassembled.
 930
 931 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 932
 933         * arm-dis.c: Update strht pattern.
 934
 935 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 936
 937         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 938         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 939         trunc.w.s macro for EE.
 940
 941 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 942             Andrew Jenner <andrew@codesourcery.com>
 943
 944         Based on patches from Altera Corporation.
 945
 946         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 947         nios2-opc.c.
 948         * Makefile.in: Regenerated.
 949         * configure.in: Add case for bfd_nios2_arch.
 950         * configure: Regenerated.
 951         * disassemble.c (ARCH_nios2): Define.
 952         (disassembler): Add case for bfd_arch_nios2.
 953         * nios2-dis.c: New file.
 954         * nios2-opc.c: New file.
 955
 956 2013-02-04  Alan Modra  <amodra@gmail.com>
 957
 958         * po/POTFILES.in: Regenerate.
 959         * rl78-decode.c: Regenerate.
 960         * rx-decode.c: Regenerate.
 961
 962 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 963
 964         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 965         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 966         * aarch64-asm.c (convert_xtl_to_shll): New function.
 967         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 968         calling convert_xtl_to_shll.
 969         * aarch64-dis.c (convert_shll_to_xtl): New function.
 970         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 971         calling convert_shll_to_xtl.
 972         * aarch64-gen.c: Update copyright year.
 973         * aarch64-asm-2.c: Re-generate.
 974         * aarch64-dis-2.c: Re-generate.
 975         * aarch64-opc-2.c: Re-generate.
 976
 977 2013-01-24  Nick Clifton  <nickc@redhat.com>
 978
 979         * v850-dis.c: Add support for e3v5 architecture.
 980         * v850-opc.c: Likewise.
 981
 982 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 983
 984         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 985         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 986         * aarch64-opc.c (operand_general_constraint_met_p): For
 987         AARCH64_MOD_LSL, move the range check on the shift amount before the
 988         alignment check; change to call set_sft_amount_out_of_range_error
 989         instead of set_imm_out_of_range_error.
 990         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 991         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 992         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 993         SIMD_IMM_SFT.
 994
 995 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 996
 997         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 998
 999         * i386-init.h: Regenerated.
1000         * i386-tbl.h: Likewise.
1001
1002 2013-01-15  Nick Clifton  <nickc@redhat.com>
1003
1004         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1005         values.
1006         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1007
1008 2013-01-14  Will Newton <will.newton@imgtec.com>
1009
1010         * metag-dis.c (REG_WIDTH): Increase to 64.
1011
1012 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1013
1014         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1015         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1016         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1017         (SH6): Update.
1018         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1019         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1020         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1021         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1022
1023 2013-01-10  Will Newton <will.newton@imgtec.com>
1024
1025         * Makefile.am: Add Meta.
1026         * configure.in: Add Meta.
1027         * disassemble.c: Add Meta support.
1028         * metag-dis.c: New file.
1029         * Makefile.in: Regenerate.
1030         * configure: Regenerate.
1031
1032 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1033
1034         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1035         (match_opcode): Rename to cr16_match_opcode.
1036
1037 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1038
1039         * mips-dis.c: Add names for CP0 registers of r5900.
1040         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1041         instructions sq and lq.
1042         Add support for MIPS r5900 CPU.
1043         Add support for 128 bit MMI (Multimedia Instructions).
1044         Add support for EE instructions (Emotion Engine).
1045         Disable unsupported floating point instructions (64 bit and
1046         undefined compare operations).
1047         Enable instructions of MIPS ISA IV which are supported by r5900.
1048         Disable 64 bit co processor instructions.
1049         Disable 64 bit multiplication and division instructions.
1050         Disable instructions for co-processor 2 and 3, because these are
1051         not supported (preparation for later VU0 support (Vector Unit)).
1052         Disable cvt.w.s because this behaves like trunc.w.s and the
1053         correct execution can't be ensured on r5900.
1054         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1055         will confuse less developers and compilers.
1056
1057 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1058
1059         * aarch64-opc.c (aarch64_print_operand): Change to print
1060         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1061         in comment.
1062         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1063         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1064         OP_MOV_IMM_WIDE.
1065
1066 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1067
1068         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1069         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1070
1071 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1072
1073         * i386-gen.c (process_copyright): Update copyright year to 2013.
1074
1075 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1076
1077         * cr16-dis.c (match_opcode,make_instruction): Remove static
1078         declaration.
1079         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1080         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1081
1082 For older changes see ChangeLog-2012
1083 \f
1084 Copyright (C) 2013 Free Software Foundation, Inc.
1085
1086 Copying and distribution of this file, with or without modification,
1087 are permitted in any medium without royalty provided the copyright
1088 notice and this notice are preserved.
1089
1090 Local Variables:
1091 mode: change-log
1092 left-margin: 8
1093 fill-column: 74
1094 version-control: never
1095 End: