opcodes/ChangeLog

   1 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/20799
   4         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
   5         * i386-dis.c (EdqwS): Removed.
   6         (dqw_swap_mode): Likewise.
   7         (intel_operand_size): Don't check dqw_swap_mode.
   8         (OP_E_register): Likewise.
   9         (OP_E_memory): Likewise.
  10         (OP_G): Likewise.
  11         (OP_EX): Likewise.
  12         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
  13         * i386-tbl.h: Regerated.
  14
  15 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
  16
  17         * i386-opc.tbl: Merge AVX512F vmovq.
  18         * i386-tbl.h: Regerated.
  19
  20 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  21
  22         PR binutils/20701
  23         * i386-dis.c (THREE_BYTE_0F7A): Removed.
  24         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
  25         (three_byte_table): Remove THREE_BYTE_0F7A.
  26
  27 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
  28
  29         PR binutils/20775
  30         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
  31         (FGRPd9_4): Replace 1 with 2.
  32         (FGRPd9_5): Replace 2 with 3.
  33         (FGRPd9_6): Replace 3 with 4.
  34         (FGRPd9_7): Replace 4 with 5.
  35         (FGRPda_5): Replace 5 with 6.
  36         (FGRPdb_4): Replace 6 with 7.
  37         (FGRPde_3): Replace 7 with 8.
  38         (FGRPdf_4): Replace 8 with 9.
  39         (fgrps): Add an entry for Bad_Opcode.
  40
  41 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
  42
  43         * arc-opc.c (arc_flag_operands): Add F_DI14.
  44         (arc_flag_classes): Add C_DI14.
  45         * arc-nps400-tbl.h: Add new exc instructions.
  46
  47 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
  48
  49         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
  50         major opcode 0xa.
  51         * arc-nps-400-tbl.h: Add dcmac instruction.
  52         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
  53         (insert_nps_rbdouble_64): Added.
  54         (extract_nps_rbdouble_64): Added.
  55         (insert_nps_proto_size): Added.
  56         (extract_nps_proto_size): Added.
  57
  58 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
  59
  60         * arc-dis.c (struct arc_operand_iterator): Remove all fields
  61         relating to long instruction processing, add new limm field.
  62         (OPCODE): Rename to...
  63         (OPCODE_32BIT_INSN): ...this.
  64         (OPCODE_AC): Delete.
  65         (skip_this_opcode): Handle different instruction lengths, update
  66         macro name.
  67         (special_flag_p): Update parameter type.
  68         (find_format_from_table): Update for more instruction lengths.
  69         (find_format_long_instructions): Delete.
  70         (find_format): Update for more instruction lengths.
  71         (arc_insn_length): Likewise.
  72         (extract_operand_value): Update for more instruction lengths.
  73         (operand_iterator_next): Remove code relating to long
  74         instructions.
  75         (arc_opcode_to_insn_type): New function.
  76         (print_insn_arc):Update for more instructions lengths.
  77         * arc-ext.c (extInstruction_t): Change argument type.
  78         * arc-ext.h (extInstruction_t): Change argument type.
  79         * arc-fxi.h: Change type unsigned to unsigned long long
  80         extensively throughout.
  81         * arc-nps400-tbl.h: Add long instructions taken from
  82         arc_long_opcodes table in arc-opc.c.
  83         * arc-opc.c: Update parameter types on insert/extract handlers.
  84         (arc_long_opcodes): Delete.
  85         (arc_num_long_opcodes): Delete.
  86         (arc_opcode_len): Update for more instruction lengths.
  87
  88 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
  89
  90         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
  91
  92 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
  93
  94         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
  95         with arc_opcode_len.
  96         (find_format_long_instructions): Likewise.
  97         * arc-opc.c (arc_opcode_len): New function.
  98
  99 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 100
 101         * arc-nps400-tbl.h: Fix some instruction masks.
 102
 103 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 104
 105         * i386-dis.c (REG_82): Removed.
 106         (X86_64_82_REG_0): Likewise.
 107         (X86_64_82_REG_1): Likewise.
 108         (X86_64_82_REG_2): Likewise.
 109         (X86_64_82_REG_3): Likewise.
 110         (X86_64_82_REG_4): Likewise.
 111         (X86_64_82_REG_5): Likewise.
 112         (X86_64_82_REG_6): Likewise.
 113         (X86_64_82_REG_7): Likewise.
 114         (X86_64_82): New.
 115         (dis386): Use X86_64_82 instead of REG_82.
 116         (reg_table): Remove REG_82.
 117         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 118         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 119         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 120         X86_64_82_REG_7.
 121
 122 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 123
 124         PR binutils/20754
 125         * i386-dis.c (REG_82): New.
 126         (X86_64_82_REG_0): Likewise.
 127         (X86_64_82_REG_1): Likewise.
 128         (X86_64_82_REG_2): Likewise.
 129         (X86_64_82_REG_3): Likewise.
 130         (X86_64_82_REG_4): Likewise.
 131         (X86_64_82_REG_5): Likewise.
 132         (X86_64_82_REG_6): Likewise.
 133         (X86_64_82_REG_7): Likewise.
 134         (dis386): Use REG_82.
 135         (reg_table): Add REG_82.
 136         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 137         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 138         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 139
 140 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 141
 142         * i386-dis.c (REG_82): Renamed to ...
 143         (REG_83): This.
 144         (dis386): Updated.
 145         (reg_table): Likewise.
 146
 147 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 148
 149         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 150         * i386-dis-evex.h (evex_table): Updated.
 151         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 152         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 153         (cpu_flags): Add CpuAVX512_4VNNIW.
 154         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 155         (i386_cpu_flags): Add cpuavx512_4vnniw.
 156         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 157         * i386-init.h: Regenerate.
 158         * i386-tbl.h: Ditto.
 159
 160 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 161
 162         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 163         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 164         * i386-dis-evex.h (evex_table): Updated.
 165         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 166         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 167         (cpu_flags): Add CpuAVX512_4FMAPS.
 168         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 169         * i386-opc.h (AVX512_4FMAP): New.
 170         (i386_cpu_flags): Add cpuavx512_4fmaps.
 171         (ImplicitQuadGroup): New.
 172         (i386_opcode_modifier): Add implicitquadgroup.
 173         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 174         * i386-init.h: Regenerate.
 175         * i386-tbl.h: Ditto.
 176
 177 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 178             Andrew Waterman <andrew@sifive.com>
 179
 180         Add support for RISC-V architecture.
 181         * configure.ac: Add entry for bfd_riscv_arch.
 182         * configure: Regenerate.
 183         * disassemble.c (disassembler): Add support for riscv.
 184         (disassembler_usage): Likewise.
 185         * riscv-dis.c: New file.
 186         * riscv-opc.c: New file.
 187
 188 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 189
 190         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 191         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 192         (rm_table): Update the RM_0FAE_REG_7 entry.
 193         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 194         (cpu_flags): Remove CpuPCOMMIT.
 195         * i386-opc.h (CpuPCOMMIT): Removed.
 196         (i386_cpu_flags): Remove cpupcommit.
 197         * i386-opc.tbl: Remove pcommit.
 198         * i386-init.h: Regenerated.
 199         * i386-tbl.h: Likewise.
 200
 201 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 202
 203         PR binutis/20705
 204         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 205         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 206         32-bit mode.  Don't check vex.register_specifier in 32-bit
 207         mode.
 208         (OP_VEX): Check for invalid mask registers.
 209
 210 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 211
 212         PR binutis/20699
 213         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 214         sizeflag.
 215
 216 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 217
 218         PR binutis/20704
 219         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 220
 221 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 222
 223         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 224         local variable to `index_regno'.
 225
 226 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 227
 228         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 229
 230 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 231
 232         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 233         usage on ISA basis.
 234
 235 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 236
 237         PR target/20666
 238         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 239
 240 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 241
 242         PR target/20667
 243         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 244         available.
 245
 246 2016-10-07  Alan Modra  <amodra@gmail.com>
 247
 248         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 249
 250 2016-10-06  Alan Modra  <amodra@gmail.com>
 251
 252         * aarch64-opc.c: Spell fall through comments consistently.
 253         * i386-dis.c: Likewise.
 254         * aarch64-dis.c: Add missing fall through comments.
 255         * aarch64-opc.c: Likewise.
 256         * arc-dis.c: Likewise.
 257         * arm-dis.c: Likewise.
 258         * i386-dis.c: Likewise.
 259         * m68k-dis.c: Likewise.
 260         * mep-asm.c: Likewise.
 261         * ns32k-dis.c: Likewise.
 262         * sh-dis.c: Likewise.
 263         * tic4x-dis.c: Likewise.
 264         * tic6x-dis.c: Likewise.
 265         * vax-dis.c: Likewise.
 266
 267 2016-10-06  Alan Modra  <amodra@gmail.com>
 268
 269         * arc-ext.c (create_map): Add missing break.
 270         * msp430-decode.opc (encode_as): Likewise.
 271         * msp430-decode.c: Regenerate.
 272
 273 2016-10-06  Alan Modra  <amodra@gmail.com>
 274
 275         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 276         * crx-dis.c (print_insn_crx): Likewise.
 277
 278 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 279
 280         PR binutils/20657
 281         * i386-dis.c (putop): Don't assign alt twice.
 282
 283 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 284
 285         PR target/20553
 286         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 287
 288 2016-09-29  Alan Modra  <amodra@gmail.com>
 289
 290         * ppc-opc.c (L): Make compulsory.
 291         (LOPT): New, optional form of L.
 292         (HTM_R): Define as LOPT.
 293         (L0, L1): Delete.
 294         (L32OPT): New, optional for 32-bit L.
 295         (L2OPT): New, 2-bit L for dcbf.
 296         (SVC_LEC): Update.
 297         (L2): Define.
 298         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 299         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 300         <dcbf>: Use L2OPT.
 301         <tlbiel, tlbie>: Use LOPT.
 302         <wclr, wclrall>: Use L2.
 303
 304 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 305
 306         * Makefile.in: Regenerate.
 307         * configure: Likewise.
 308
 309 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 310
 311         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 312         (EXTINSN2OP): Use EXTINSN2OPF.
 313         (bspeekm, bspop, modapp): New extension instructions.
 314         * arc-opc.c (F_DNZ_ND): Define.
 315         (F_DNZ_D): Likewise.
 316         (F_SIZEB1): Changed.
 317         (C_DNZ_D): Define.
 318         (C_HARD): Changed.
 319         * arc-tbl.h (dbnz): New instruction.
 320         (prealloc): Allow it for ARC EM.
 321         (xbfu): Likewise.
 322
 323 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 324
 325         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 326         after commas in addresses.
 327         (aarch64_print_operand): Likewise.
 328
 329 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 330
 331         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 332         rather than "should be" or "expected to be" in error messages.
 333
 334 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 335
 336         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 337         (print_mnemonic_name): ...here.
 338         (print_comment): New function.
 339         (print_aarch64_insn): Call it.
 340         * aarch64-opc.c (aarch64_conds): Add SVE names.
 341         (aarch64_print_operand): Print alternative condition names in
 342         a comment.
 343
 344 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 345
 346         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 347         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 348         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 349         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 350         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 351         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 352         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 353         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 354         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 355         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 356         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 357         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 358         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 359         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 360         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 361         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 362         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 363         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 364         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 365         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 366         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 367         (aarch64_feature_sve): New variable.
 368         (SVE): New macro.
 369         (_SVE_INSN): Likewise.
 370         (aarch64_opcode_table): Add SVE instructions.
 371         * aarch64-opc.h (extract_fields): Declare.
 372         * aarch64-opc-2.c: Regenerate.
 373         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 374         * aarch64-asm-2.c: Regenerate.
 375         * aarch64-dis.c (extract_fields): Make global.
 376         (do_misc_decoding): Handle the new SVE aarch64_ops.
 377         * aarch64-dis-2.c: Regenerate.
 378
 379 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 380
 381         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 382         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 383         aarch64_field_kinds.
 384         * aarch64-opc.c (fields): Add corresponding entries.
 385         * aarch64-asm.c (aarch64_get_variant): New function.
 386         (aarch64_encode_variant_using_iclass): Likewise.
 387         (aarch64_opcode_encode): Call it.
 388         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 389         (aarch64_opcode_decode): Call it.
 390
 391 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 392
 393         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 394         and FP register operands.
 395         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 396         (FLD_SVE_Vn): New aarch64_field_kinds.
 397         * aarch64-opc.c (fields): Add corresponding entries.
 398         (aarch64_print_operand): Handle the new SVE core and FP register
 399         operands.
 400         * aarch64-opc-2.c: Regenerate.
 401         * aarch64-asm-2.c: Likewise.
 402         * aarch64-dis-2.c: Likewise.
 403
 404 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 405
 406         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 407         immediate operands.
 408         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 409         * aarch64-opc.c (fields): Add corresponding entry.
 410         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 411         operands.
 412         (aarch64_print_operand): Likewise.
 413         * aarch64-opc-2.c: Regenerate.
 414         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 415         (ins_sve_float_zero_one): New inserters.
 416         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 417         (aarch64_ins_sve_float_half_two): Likewise.
 418         (aarch64_ins_sve_float_zero_one): Likewise.
 419         * aarch64-asm-2.c: Regenerate.
 420         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 421         (ext_sve_float_zero_one): New extractors.
 422         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 423         (aarch64_ext_sve_float_half_two): Likewise.
 424         (aarch64_ext_sve_float_zero_one): Likewise.
 425         * aarch64-dis-2.c: Regenerate.
 426
 427 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 428
 429         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 430         integer immediate operands.
 431         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 432         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 433         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 434         * aarch64-opc.c (fields): Add corresponding entries.
 435         (operand_general_constraint_met_p): Handle the new SVE integer
 436         immediate operands.
 437         (aarch64_print_operand): Likewise.
 438         (aarch64_sve_dupm_mov_immediate_p): New function.
 439         * aarch64-opc-2.c: Regenerate.
 440         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 441         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 442         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 443         (aarch64_ins_limm): ...here.
 444         (aarch64_ins_inv_limm): New function.
 445         (aarch64_ins_sve_aimm): Likewise.
 446         (aarch64_ins_sve_asimm): Likewise.
 447         (aarch64_ins_sve_limm_mov): Likewise.
 448         (aarch64_ins_sve_shlimm): Likewise.
 449         (aarch64_ins_sve_shrimm): Likewise.
 450         * aarch64-asm-2.c: Regenerate.
 451         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 452         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 453         * aarch64-dis.c (decode_limm): New function, split out from...
 454         (aarch64_ext_limm): ...here.
 455         (aarch64_ext_inv_limm): New function.
 456         (decode_sve_aimm): Likewise.
 457         (aarch64_ext_sve_aimm): Likewise.
 458         (aarch64_ext_sve_asimm): Likewise.
 459         (aarch64_ext_sve_limm_mov): Likewise.
 460         (aarch64_top_bit): Likewise.
 461         (aarch64_ext_sve_shlimm): Likewise.
 462         (aarch64_ext_sve_shrimm): Likewise.
 463         * aarch64-dis-2.c: Regenerate.
 464
 465 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 466
 467         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 468         operands.
 469         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 470         the AARCH64_MOD_MUL_VL entry.
 471         (value_aligned_p): Cope with non-power-of-two alignments.
 472         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 473         (print_immediate_offset_address): Likewise.
 474         (aarch64_print_operand): Likewise.
 475         * aarch64-opc-2.c: Regenerate.
 476         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 477         (ins_sve_addr_ri_s9xvl): New inserters.
 478         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 479         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 480         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 481         * aarch64-asm-2.c: Regenerate.
 482         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 483         (ext_sve_addr_ri_s9xvl): New extractors.
 484         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 485         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 486         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 487         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 488         * aarch64-dis-2.c: Regenerate.
 489
 490 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 491
 492         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 493         address operands.
 494         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 495         (FLD_SVE_xs_22): New aarch64_field_kinds.
 496         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 497         (get_operand_specific_data): New function.
 498         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 499         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 500         (operand_general_constraint_met_p): Handle the new SVE address
 501         operands.
 502         (sve_reg): New array.
 503         (get_addr_sve_reg_name): New function.
 504         (aarch64_print_operand): Handle the new SVE address operands.
 505         * aarch64-opc-2.c: Regenerate.
 506         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 507         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 508         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 509         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 510         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 511         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 512         (aarch64_ins_sve_addr_zi_u5): Likewise.
 513         (aarch64_ins_sve_addr_zz): Likewise.
 514         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 515         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 516         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 517         * aarch64-asm-2.c: Regenerate.
 518         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 519         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 520         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 521         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 522         (aarch64_ext_sve_addr_ri_u6): Likewise.
 523         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 524         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 525         (aarch64_ext_sve_addr_zi_u5): Likewise.
 526         (aarch64_ext_sve_addr_zz): Likewise.
 527         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 528         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 529         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 530         * aarch64-dis-2.c: Regenerate.
 531
 532 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 533
 534         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 535         AARCH64_OPND_SVE_PATTERN_SCALED.
 536         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 537         * aarch64-opc.c (fields): Add a corresponding entry.
 538         (set_multiplier_out_of_range_error): New function.
 539         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 540         (operand_general_constraint_met_p): Handle
 541         AARCH64_OPND_SVE_PATTERN_SCALED.
 542         (print_register_offset_address): Use PRIi64 to print the
 543         shift amount.
 544         (aarch64_print_operand): Likewise.  Handle
 545         AARCH64_OPND_SVE_PATTERN_SCALED.
 546         * aarch64-opc-2.c: Regenerate.
 547         * aarch64-asm.h (ins_sve_scale): New inserter.
 548         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 549         * aarch64-asm-2.c: Regenerate.
 550         * aarch64-dis.h (ext_sve_scale): New inserter.
 551         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 552         * aarch64-dis-2.c: Regenerate.
 553
 554 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 555
 556         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 557         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 558         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 559         (FLD_SVE_prfop): Likewise.
 560         * aarch64-opc.c: Include libiberty.h.
 561         (aarch64_sve_pattern_array): New variable.
 562         (aarch64_sve_prfop_array): Likewise.
 563         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 564         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 565         AARCH64_OPND_SVE_PRFOP.
 566         * aarch64-asm-2.c: Regenerate.
 567         * aarch64-dis-2.c: Likewise.
 568         * aarch64-opc-2.c: Likewise.
 569
 570 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 571
 572         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 573         AARCH64_OPND_QLF_P_[ZM].
 574         (aarch64_print_operand): Print /z and /m where appropriate.
 575
 576 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 577
 578         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 579         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 580         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 581         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 582         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 583         * aarch64-opc.c (fields): Add corresponding entries here.
 584         (operand_general_constraint_met_p): Check that SVE register lists
 585         have the correct length.  Check the ranges of SVE index registers.
 586         Check for cases where p8-p15 are used in 3-bit predicate fields.
 587         (aarch64_print_operand): Handle the new SVE operands.
 588         * aarch64-opc-2.c: Regenerate.
 589         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 590         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 591         (aarch64_ins_sve_reglist): Likewise.
 592         * aarch64-asm-2.c: Regenerate.
 593         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 594         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 595         (aarch64_ext_sve_reglist): Likewise.
 596         * aarch64-dis-2.c: Regenerate.
 597
 598 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 599
 600         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 601         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 602         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 603         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 604         tied operands.
 605
 606 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 607
 608         * aarch64-opc.c (get_offset_int_reg_name): New function.
 609         (print_immediate_offset_address): Likewise.
 610         (print_register_offset_address): Take the base and offset
 611         registers as parameters.
 612         (aarch64_print_operand): Update caller accordingly.  Use
 613         print_immediate_offset_address.
 614
 615 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 616
 617         * aarch64-opc.c (BANK): New macro.
 618         (R32, R64): Take a register number as argument
 619         (int_reg): Use BANK.
 620
 621 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 622
 623         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 624         (aarch64_print_operand): Update accordingly.
 625
 626 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 627
 628         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 629         for FPIMM.
 630         * aarch64-asm.h (ins_fpimm): New inserter.
 631         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 632         * aarch64-asm-2.c: Regenerate.
 633         * aarch64-dis.h (ext_fpimm): New extractor.
 634         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 635         (aarch64_ext_fpimm): New function.
 636         * aarch64-dis-2.c: Regenerate.
 637
 638 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 639
 640         * aarch64-asm.c: Include libiberty.h.
 641         (insert_fields): New function.
 642         (aarch64_ins_imm): Use it.
 643         * aarch64-dis.c (extract_fields): New function.
 644         (aarch64_ext_imm): Use it.
 645
 646 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 647
 648         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 649         with an esize parameter.
 650         (operand_general_constraint_met_p): Update accordingly.
 651         Fix misindented code.
 652         * aarch64-asm.c (aarch64_ins_limm): Update call to
 653         aarch64_logical_immediate_p.
 654
 655 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 656
 657         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 658
 659 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 660
 661         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 662
 663 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 664
 665         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 666
 667 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 668
 669         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 670         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 671         xor3>: Delete mnemonics.
 672         <cp_abort>: Rename mnemonic from ...
 673         <cpabort>: ...to this.
 674         <setb>: Change to a X form instruction.
 675         <sync>: Change to 1 operand form.
 676         <copy>: Delete mnemonic.
 677         <copy_first>: Rename mnemonic from ...
 678         <copy>: ...to this.
 679         <paste, paste.>: Delete mnemonics.
 680         <paste_last>: Rename mnemonic from ...
 681         <paste.>: ...to this.
 682
 683 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 684
 685         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 686
 687 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 688
 689         * s390-mkopc.c (main): Support alternate arch strings.
 690
 691 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 692
 693         * s390-opc.txt: Fix kmctr instruction type.
 694
 695 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 696
 697         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 698         * i386-init.h: Regenerated.
 699
 700 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 701
 702         * opcodes/arc-dis.c (print_insn_arc): Changed.
 703
 704 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 705
 706         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 707         camellia_fl.
 708
 709 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 710
 711         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 712         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 713         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 714
 715 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 716
 717         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 718         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 719         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 720         PREFIX_MOD_3_0FAE_REG_4.
 721         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 722         PREFIX_MOD_3_0FAE_REG_4.
 723         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 724         (cpu_flags): Add CpuPTWRITE.
 725         * i386-opc.h (CpuPTWRITE): New.
 726         (i386_cpu_flags): Add cpuptwrite.
 727         * i386-opc.tbl: Add ptwrite instruction.
 728         * i386-init.h: Regenerated.
 729         * i386-tbl.h: Likewise.
 730
 731 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 732
 733         * arc-dis.h: Wrap around in extern "C".
 734
 735 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 736
 737         * aarch64-tbl.h (V8_2_INSN): New macro.
 738         (aarch64_opcode_table): Use it.
 739
 740 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 741
 742         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 743         CORE_INSN, __FP_INSN and SIMD_INSN.
 744
 745 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 746
 747         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 748         (aarch64_opcode_table): Update uses accordingly.
 749
 750 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 751         Kwok Cheung Yeung  <kcy@codesourcery.com>
 752
 753         opcodes/
 754         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 755         'e_cmplwi' to 'e_cmpli' instead.
 756         (OPVUPRT, OPVUPRT_MASK): Define.
 757         (powerpc_opcodes): Add E200Z4 insns.
 758         (vle_opcodes): Add context save/restore insns.
 759
 760 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 761
 762         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 763         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 764         "j".
 765
 766 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 767
 768         * arc-nps400-tbl.h: Change block comments to GNU format.
 769         * arc-dis.c: Add new globals addrtypenames,
 770         addrtypenames_max, and addtypeunknown.
 771         (get_addrtype): New function.
 772         (print_insn_arc): Print colons and address types when
 773         required.
 774         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 775         define insert and extract functions for all address types.
 776         (arc_operands): Add operands for colon and all address
 777         types.
 778         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 779         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 780         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 781         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 782         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 783         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 784
 785 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 786
 787         * configure: Regenerated.
 788
 789 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 790
 791         * arc-dis.c (skipclass): New structure.
 792         (decodelist): New variable.
 793         (is_compatible_p): New function.
 794         (new_element): Likewise.
 795         (skip_class_p): Likewise.
 796         (find_format_from_table): Use skip_class_p function.
 797         (find_format): Decode first the extension instructions.
 798         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 799         e_flags.
 800         (parse_option): New function.
 801         (parse_disassembler_options): Likewise.
 802         (print_arc_disassembler_options): Likewise.
 803         (print_insn_arc): Use parse_disassembler_options function.  Proper
 804         select ARCv2 cpu variant.
 805         * disassemble.c (disassembler_usage): Add ARC disassembler
 806         options.
 807
 808 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 809
 810         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 811         annotation from the "nal" entry and reorder it beyond "bltzal".
 812
 813 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 814
 815         * sparc-opc.c (ldtxa): New macro.
 816         (sparc_opcodes): Use the macro defined above to add entries for
 817         the LDTXA instructions.
 818         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 819         instruction.
 820
 821 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 822
 823         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 824         and "jmpc".
 825
 826 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 827
 828         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 829         (movzb): Adjust to cover all permitted suffixes.
 830         (movzw): New.
 831         * i386-tbl.h: Re-generate.
 832
 833 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 834
 835         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 836         (lgdt): Remove Tbyte from non-64-bit variant.
 837         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 838         xsaves64, xsavec64): Remove Disp16.
 839         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 840         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 841         64-bit variants.
 842         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 843         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 844         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 845         64-bit variants.
 846         * i386-tbl.h: Re-generate.
 847
 848 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 849
 850         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 851         * i386-tbl.h: Re-generate.
 852
 853 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 854
 855         * arm-dis.c (print_insn): Fix typo in comment.
 856
 857 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 858
 859         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 860         range of ldst_elemlist operands.
 861         (print_register_list): Use PRIi64 to print the index.
 862         (aarch64_print_operand): Likewise.
 863
 864 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 865
 866         * mcore-opc.h: Remove sentinal.
 867         * mcore-dis.c (print_insn_mcore): Adjust.
 868
 869 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 870
 871         * arc-opc.c: Correct description of availability of NPS400
 872         features.
 873
 874 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 875
 876         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 877         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 878         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 879         xor3>: New mnemonics.
 880         <setb>: Change to a VX form instruction.
 881         (insert_sh6): Add support for rldixor.
 882         (extract_sh6): Likewise.
 883
 884 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 885
 886         * arc-ext.h: Wrap in extern C.
 887
 888 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 889
 890         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 891         Use same method for determining instruction length on ARC700 and
 892         NPS-400.
 893         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 894         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 895         with the NPS400 subclass.
 896         * arc-opc.c: Likewise.
 897
 898 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 899
 900         * sparc-opc.c (rdasr): New macro.
 901         (wrasr): Likewise.
 902         (rdpr): Likewise.
 903         (wrpr): Likewise.
 904         (rdhpr): Likewise.
 905         (wrhpr): Likewise.
 906         (sparc_opcodes): Use the macros above to fix and expand the
 907         definition of read/write instructions from/to
 908         asr/privileged/hyperprivileged instructions.
 909         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 910         %hva_mask_nz.  Prefer softint_set and softint_clear over
 911         set_softint and clear_softint.
 912         (print_insn_sparc): Support %ver in Rd.
 913
 914 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 915
 916         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 917         architecture according to the hardware capabilities they require.
 918
 919 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 920
 921         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 922         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 923         bfd_mach_sparc_v9{c,d,e,v,m}.
 924         * sparc-opc.c (MASK_V9C): Define.
 925         (MASK_V9D): Likewise.
 926         (MASK_V9E): Likewise.
 927         (MASK_V9V): Likewise.
 928         (MASK_V9M): Likewise.
 929         (v6): Add MASK_V9{C,D,E,V,M}.
 930         (v6notlet): Likewise.
 931         (v7): Likewise.
 932         (v8): Likewise.
 933         (v9): Likewise.
 934         (v9andleon): Likewise.
 935         (v9a): Likewise.
 936         (v9b): Likewise.
 937         (v9c): Define.
 938         (v9d): Likewise.
 939         (v9e): Likewise.
 940         (v9v): Likewise.
 941         (v9m): Likewise.
 942         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 943
 944 2016-06-15  Nick Clifton  <nickc@redhat.com>
 945
 946         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 947         constants to match expected behaviour.
 948         (nds32_parse_opcode): Likewise.  Also for whitespace.
 949
 950 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 951
 952         * arc-opc.c (extract_rhv1): Extract value from insn.
 953
 954 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 955
 956         * arc-nps400-tbl.h: Add ldbit instruction.
 957         * arc-opc.c: Add flag classes required for ldbit.
 958
 959 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 960
 961         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 962         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 963         support the above instructions.
 964
 965 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 966
 967         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 968         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 969         csma, cbba, zncv, and hofs.
 970         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 971         support the above instructions.
 972
 973 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 974
 975         * arc-nps400-tbl.h: Add andab and orab instructions.
 976
 977 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 978
 979         * arc-nps400-tbl.h: Add addl-like instructions.
 980
 981 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 982
 983         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 984
 985 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 986
 987         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 988         instructions.
 989
 990 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 991
 992         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 993         variable.
 994         (init_disasm): Handle new command line option "insnlength".
 995         (print_s390_disassembler_options): Mention new option in help
 996         output.
 997         (print_insn_s390): Use the encoded insn length when dumping
 998         unknown instructions.
 999
1000 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1001
1002         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1003          to the address and set as symbol address for LDS/ STS immediate operands.
1004
1005 2016-06-07  Alan Modra  <amodra@gmail.com>
1006
1007         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1008         cpu for "vle" to e500.
1009         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1010         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1011         (PPCNONE): Delete, substitute throughout.
1012         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1013         except for major opcode 4 and 31.
1014         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1015
1016 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1017
1018         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1019         ARM_EXT_RAS in relevant entries.
1020
1021 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1022
1023         PR binutils/20196
1024         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1025         opcodes for E6500.
1026
1027 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1028
1029         PR binutis/18386
1030         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1031         (indir_v_mode): New.
1032         Add comments for '&'.
1033         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1034         (putop): Handle '&'.
1035         (intel_operand_size): Handle indir_v_mode.
1036         (OP_E_register): Likewise.
1037         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1038         64-bit indirect call/jmp for AMD64.
1039         * i386-tbl.h: Regenerated
1040
1041 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1042
1043         * arc-dis.c (struct arc_operand_iterator): New structure.
1044         (find_format_from_table): All the old content from find_format,
1045         with some minor adjustments, and parameter renaming.
1046         (find_format_long_instructions): New function.
1047         (find_format): Rewritten.
1048         (arc_insn_length): Add LSB parameter.
1049         (extract_operand_value): New function.
1050         (operand_iterator_next): New function.
1051         (print_insn_arc): Use new functions to find opcode, and iterator
1052         over operands.
1053         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1054         (extract_nps_3bit_dst_short): New function.
1055         (insert_nps_3bit_src2_short): New function.
1056         (extract_nps_3bit_src2_short): New function.
1057         (insert_nps_bitop1_size): New function.
1058         (extract_nps_bitop1_size): New function.
1059         (insert_nps_bitop2_size): New function.
1060         (extract_nps_bitop2_size): New function.
1061         (insert_nps_bitop_mod4_msb): New function.
1062         (extract_nps_bitop_mod4_msb): New function.
1063         (insert_nps_bitop_mod4_lsb): New function.
1064         (extract_nps_bitop_mod4_lsb): New function.
1065         (insert_nps_bitop_dst_pos3_pos4): New function.
1066         (extract_nps_bitop_dst_pos3_pos4): New function.
1067         (insert_nps_bitop_ins_ext): New function.
1068         (extract_nps_bitop_ins_ext): New function.
1069         (arc_operands): Add new operands.
1070         (arc_long_opcodes): New global array.
1071         (arc_num_long_opcodes): New global.
1072         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1073
1074 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1075
1076         * nds32-asm.h: Add extern "C".
1077         * sh-opc.h: Likewise.
1078
1079 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1080
1081         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1082         0,b,limm to the rflt instruction.
1083
1084 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1085
1086         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1087         constant.
1088
1089 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1090
1091         PR gas/20145
1092         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1093         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1094         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1095         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1096         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1097         * i386-init.h: Regenerated.
1098
1099 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1100
1101         PR gas/20145
1102         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1103         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1104         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1105         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1106         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1107         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1108         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1109         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1110         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1111         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1112         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1113         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1114         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1115         CpuRegMask for AVX512.
1116         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1117         and CpuRegMask.
1118         (set_bitfield_from_cpu_flag_init): New function.
1119         (set_bitfield): Remove const on f.  Call
1120         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1121         * i386-opc.h (CpuRegMMX): New.
1122         (CpuRegXMM): Likewise.
1123         (CpuRegYMM): Likewise.
1124         (CpuRegZMM): Likewise.
1125         (CpuRegMask): Likewise.
1126         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1127         and cpuregmask.
1128         * i386-init.h: Regenerated.
1129         * i386-tbl.h: Likewise.
1130
1131 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1132
1133         PR gas/20154
1134         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1135         (opcode_modifiers): Add AMD64 and Intel64.
1136         (main): Properly verify CpuMax.
1137         * i386-opc.h (CpuAMD64): Removed.
1138         (CpuIntel64): Likewise.
1139         (CpuMax): Set to CpuNo64.
1140         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1141         (AMD64): New.
1142         (Intel64): Likewise.
1143         (i386_opcode_modifier): Add amd64 and intel64.
1144         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1145         on call and jmp.
1146         * i386-init.h: Regenerated.
1147         * i386-tbl.h: Likewise.
1148
1149 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1150
1151         PR gas/20154
1152         * i386-gen.c (main): Fail if CpuMax is incorrect.
1153         * i386-opc.h (CpuMax): Set to CpuIntel64.
1154         * i386-tbl.h: Regenerated.
1155
1156 2016-05-27  Nick Clifton  <nickc@redhat.com>
1157
1158         PR target/20150
1159         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1160         (msp430dis_opcode_unsigned): New function.
1161         (msp430dis_opcode_signed): New function.
1162         (msp430_singleoperand): Use the new opcode reading functions.
1163         Only disassenmble bytes if they were successfully read.
1164         (msp430_doubleoperand): Likewise.
1165         (msp430_branchinstr): Likewise.
1166         (msp430x_callx_instr): Likewise.
1167         (print_insn_msp430): Check that it is safe to read bytes before
1168         attempting disassembly.  Use the new opcode reading functions.
1169
1170 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1171
1172         * ppc-opc.c (CY): New define.  Document it.
1173         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1174
1175 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1176
1177         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1178         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1179         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1180         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1181         CPU_ANY_AVX_FLAGS.
1182         * i386-init.h: Regenerated.
1183
1184 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1185
1186         PR gas/20141
1187         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1188         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1189         * i386-init.h: Regenerated.
1190
1191 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1192
1193         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1194         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1195         * i386-init.h: Regenerated.
1196
1197 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1198
1199         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1200         information.
1201         (print_insn_arc): Set insn_type information.
1202         * arc-opc.c (C_CC): Add F_CLASS_COND.
1203         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1204         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1205         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1206         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1207         (brne, brne_s, jeq_s, jne_s): Likewise.
1208
1209 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1210
1211         * arc-tbl.h (neg): New instruction variant.
1212
1213 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1214
1215         * arc-dis.c (find_format, find_format, get_auxreg)
1216         (print_insn_arc): Changed.
1217         * arc-ext.h (INSERT_XOP): Likewise.
1218
1219 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1220
1221         * tic54x-dis.c (sprint_mmr): Adjust.
1222         * tic54x-opc.c: Likewise.
1223
1224 2016-05-19  Alan Modra  <amodra@gmail.com>
1225
1226         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1227
1228 2016-05-19  Alan Modra  <amodra@gmail.com>
1229
1230         * ppc-opc.c: Formatting.
1231         (NSISIGNOPT): Define.
1232         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1233
1234 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1235
1236         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1237         replacing references to `micromips_ase' throughout.
1238         (_print_insn_mips): Don't use file-level microMIPS annotation to
1239         determine the disassembly mode with the symbol table.
1240
1241 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1242
1243         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1244
1245 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1246
1247         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1248         mips64r6.
1249         * mips-opc.c (D34): New macro.
1250         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1251
1252 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1253
1254         * i386-dis.c (prefix_table): Add RDPID instruction.
1255         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1256         (cpu_flags): Add RDPID bitfield.
1257         * i386-opc.h (enum): Add RDPID element.
1258         (i386_cpu_flags): Add RDPID field.
1259         * i386-opc.tbl: Add RDPID instruction.
1260         * i386-init.h: Regenerate.
1261         * i386-tbl.h: Regenerate.
1262
1263 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1264
1265         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1266         branch type of a symbol.
1267         (print_insn): Likewise.
1268
1269 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1270
1271         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1272         Mainline Security Extensions instructions.
1273         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1274         Extensions instructions.
1275         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1276         instructions.
1277         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1278         special registers.
1279
1280 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1281
1282         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1283
1284 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1285
1286         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1287         (arcExtMap_genOpcode): Likewise.
1288         * arc-opc.c (arg_32bit_rc): Define new variable.
1289         (arg_32bit_u6): Likewise.
1290         (arg_32bit_limm): Likewise.
1291
1292 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1293
1294         * aarch64-gen.c (VERIFIER): Define.
1295         * aarch64-opc.c (VERIFIER): Define.
1296         (verify_ldpsw): Use static linkage.
1297         * aarch64-opc.h (verify_ldpsw): Remove.
1298         * aarch64-tbl.h: Use VERIFIER for verifiers.
1299
1300 2016-04-28  Nick Clifton  <nickc@redhat.com>
1301
1302         PR target/19722
1303         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1304         * aarch64-opc.c (verify_ldpsw): New function.
1305         * aarch64-opc.h (verify_ldpsw): New prototype.
1306         * aarch64-tbl.h: Add initialiser for verifier field.
1307         (LDPSW): Set verifier to verify_ldpsw.
1308
1309 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1310
1311         PR binutils/19983
1312         PR binutils/19984
1313         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1314         smaller than address size.
1315
1316 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1317
1318         * alpha-dis.c: Regenerate.
1319         * crx-dis.c: Likewise.
1320         * disassemble.c: Likewise.
1321         * epiphany-opc.c: Likewise.
1322         * fr30-opc.c: Likewise.
1323         * frv-opc.c: Likewise.
1324         * ip2k-opc.c: Likewise.
1325         * iq2000-opc.c: Likewise.
1326         * lm32-opc.c: Likewise.
1327         * lm32-opinst.c: Likewise.
1328         * m32c-opc.c: Likewise.
1329         * m32r-opc.c: Likewise.
1330         * m32r-opinst.c: Likewise.
1331         * mep-opc.c: Likewise.
1332         * mt-opc.c: Likewise.
1333         * or1k-opc.c: Likewise.
1334         * or1k-opinst.c: Likewise.
1335         * tic80-opc.c: Likewise.
1336         * xc16x-opc.c: Likewise.
1337         * xstormy16-opc.c: Likewise.
1338
1339 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1340
1341         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1342         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1343         calcsd, and calcxd instructions.
1344         * arc-opc.c (insert_nps_bitop_size): Delete.
1345         (extract_nps_bitop_size): Delete.
1346         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1347         (extract_nps_qcmp_m3): Define.
1348         (extract_nps_qcmp_m2): Define.
1349         (extract_nps_qcmp_m1): Define.
1350         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1351         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1352         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1353         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1354         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1355         NPS_QCMP_M3.
1356
1357 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1358
1359         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1360
1361 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1362
1363         * Makefile.in: Regenerated with automake 1.11.6.
1364         * aclocal.m4: Likewise.
1365
1366 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1367
1368         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1369         instructions.
1370         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1371         (extract_nps_cmem_uimm16): New function.
1372         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1373
1374 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1375
1376         * arc-dis.c (arc_insn_length): New function.
1377         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1378         (find_format): Change insnLen parameter to unsigned.
1379
1380 2016-04-13  Nick Clifton  <nickc@redhat.com>
1381
1382         PR target/19937
1383         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1384         the LD.B and LD.BU instructions.
1385
1386 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1387
1388         * arc-dis.c (find_format): Check for extension flags.
1389         (print_flags): New function.
1390         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1391         .extAuxRegister.
1392         * arc-ext.c (arcExtMap_coreRegName): Use
1393         LAST_EXTENSION_CORE_REGISTER.
1394         (arcExtMap_coreReadWrite): Likewise.
1395         (dump_ARC_extmap): Update printing.
1396         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1397         (arc_aux_regs): Add cpu field.
1398         * arc-regs.h: Add cpu field, lower case name aux registers.
1399
1400 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1401
1402         * arc-tbl.h: Add rtsc, sleep with no arguments.
1403
1404 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1405
1406         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1407         Initialize.
1408         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1409         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1410         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1411         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1412         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1413         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1414         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1415         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1416         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1417         (arc_opcode arc_opcodes): Null terminate the array.
1418         (arc_num_opcodes): Remove.
1419         * arc-ext.h (INSERT_XOP): Define.
1420         (extInstruction_t): Likewise.
1421         (arcExtMap_instName): Delete.
1422         (arcExtMap_insn): New function.
1423         (arcExtMap_genOpcode): Likewise.
1424         * arc-ext.c (ExtInstruction): Remove.
1425         (create_map): Zero initialize instruction fields.
1426         (arcExtMap_instName): Remove.
1427         (arcExtMap_insn): New function.
1428         (dump_ARC_extmap): More info while debuging.
1429         (arcExtMap_genOpcode): New function.
1430         * arc-dis.c (find_format): New function.
1431         (print_insn_arc): Use find_format.
1432         (arc_get_disassembler): Enable dump_ARC_extmap only when
1433         debugging.
1434
1435 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1436
1437         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1438         instruction bits out.
1439
1440 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1441
1442         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1443         * arc-opc.c (arc_flag_operands): Add new flags.
1444         (arc_flag_classes): Add new classes.
1445
1446 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1447
1448         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1449
1450 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1451
1452         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1453         encode1, rflt, crc16, and crc32 instructions.
1454         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1455         (arc_flag_classes): Add C_NPS_R.
1456         (insert_nps_bitop_size_2b): New function.
1457         (extract_nps_bitop_size_2b): Likewise.
1458         (insert_nps_bitop_uimm8): Likewise.
1459         (extract_nps_bitop_uimm8): Likewise.
1460         (arc_operands): Add new operand entries.
1461
1462 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1463
1464         * arc-regs.h: Add a new subclass field.  Add double assist
1465         accumulator register values.
1466         * arc-tbl.h: Use DPA subclass to mark the double assist
1467         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1468         * arc-opc.c (RSP): Define instead of SP.
1469         (arc_aux_regs): Add the subclass field.
1470
1471 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1472
1473         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1474
1475 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1476
1477         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1478         NPS_R_SRC1.
1479
1480 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1481
1482         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1483         issues.  No functional changes.
1484
1485 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1486
1487         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1488         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1489         (RTT): Remove duplicate.
1490         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1491         (PCT_CONFIG*): Remove.
1492         (D1L, D1H, D2H, D2L): Define.
1493
1494 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1495
1496         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1497
1498 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1499
1500         * arc-tbl.h (invld07): Remove.
1501         * arc-ext-tbl.h: New file.
1502         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1503         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1504
1505 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1506
1507         Fix -Wstack-usage warnings.
1508         * aarch64-dis.c (print_operands): Substitute size.
1509         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1510
1511 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1512
1513         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1514         to get a proper diagnostic when an invalid ASR register is used.
1515
1516 2016-03-22  Nick Clifton  <nickc@redhat.com>
1517
1518         * configure: Regenerate.
1519
1520 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1521
1522         * arc-nps400-tbl.h: New file.
1523         * arc-opc.c: Add top level comment.
1524         (insert_nps_3bit_dst): New function.
1525         (extract_nps_3bit_dst): New function.
1526         (insert_nps_3bit_src2): New function.
1527         (extract_nps_3bit_src2): New function.
1528         (insert_nps_bitop_size): New function.
1529         (extract_nps_bitop_size): New function.
1530         (arc_flag_operands): Add nps400 entries.
1531         (arc_flag_classes): Add nps400 entries.
1532         (arc_operands): Add nps400 entries.
1533         (arc_opcodes): Add nps400 include.
1534
1535 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1536
1537         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1538         the new class enum values.
1539
1540 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1541
1542         * arc-dis.c (print_insn_arc): Handle nps400.
1543
1544 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1545
1546         * arc-opc.c (BASE): Delete.
1547
1548 2016-03-18  Nick Clifton  <nickc@redhat.com>
1549
1550         PR target/19721
1551         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1552         of MOV insn that aliases an ORR insn.
1553
1554 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1555
1556         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1557
1558 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1559
1560         * mcore-opc.h: Add const qualifiers.
1561         * microblaze-opc.h (struct op_code_struct): Likewise.
1562         * sh-opc.h: Likewise.
1563         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1564         (tic4x_print_op): Likewise.
1565
1566 2016-03-02  Alan Modra  <amodra@gmail.com>
1567
1568         * or1k-desc.h: Regenerate.
1569         * fr30-ibld.c: Regenerate.
1570         * rl78-decode.c: Regenerate.
1571
1572 2016-03-01  Nick Clifton  <nickc@redhat.com>
1573
1574         PR target/19747
1575         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1576
1577 2016-02-24  Renlin Li  <renlin.li@arm.com>
1578
1579         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1580         (print_insn_coprocessor): Support fp16 instructions.
1581
1582 2016-02-24  Renlin Li  <renlin.li@arm.com>
1583
1584         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1585         vminnm, vrint(mpna).
1586
1587 2016-02-24  Renlin Li  <renlin.li@arm.com>
1588
1589         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1590         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1591
1592 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1593
1594         * i386-dis.c (print_insn): Parenthesize expression to prevent
1595         truncated addresses.
1596         (OP_J): Likewise.
1597
1598 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1599             Janek van Oirschot  <jvanoirs@synopsys.com>
1600
1601         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1602         variable.
1603
1604 2016-02-04  Nick Clifton  <nickc@redhat.com>
1605
1606         PR target/19561
1607         * msp430-dis.c (print_insn_msp430): Add a special case for
1608         decoding an RRC instruction with the ZC bit set in the extension
1609         word.
1610
1611 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1612
1613         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1614         * epiphany-ibld.c: Regenerate.
1615         * fr30-ibld.c: Regenerate.
1616         * frv-ibld.c: Regenerate.
1617         * ip2k-ibld.c: Regenerate.
1618         * iq2000-ibld.c: Regenerate.
1619         * lm32-ibld.c: Regenerate.
1620         * m32c-ibld.c: Regenerate.
1621         * m32r-ibld.c: Regenerate.
1622         * mep-ibld.c: Regenerate.
1623         * mt-ibld.c: Regenerate.
1624         * or1k-ibld.c: Regenerate.
1625         * xc16x-ibld.c: Regenerate.
1626         * xstormy16-ibld.c: Regenerate.
1627
1628 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1629
1630         * epiphany-dis.c: Regenerated from latest cpu files.
1631
1632 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1633
1634         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1635         test bit.
1636
1637 2016-01-25  Renlin Li  <renlin.li@arm.com>
1638
1639         * arm-dis.c (mapping_symbol_for_insn): New function.
1640         (find_ifthen_state): Call mapping_symbol_for_insn().
1641
1642 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1643
1644         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1645         of MSR UAO immediate operand.
1646
1647 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1648
1649         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1650         instruction support.
1651
1652 2016-01-17  Alan Modra  <amodra@gmail.com>
1653
1654         * configure: Regenerate.
1655
1656 2016-01-14  Nick Clifton  <nickc@redhat.com>
1657
1658         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1659         instructions that can support stack pointer operations.
1660         * rl78-decode.c: Regenerate.
1661         * rl78-dis.c: Fix display of stack pointer in MOVW based
1662         instructions.
1663
1664 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1665
1666         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1667         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1668         erxtatus_el1 and erxaddr_el1.
1669
1670 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1671
1672         * arm-dis.c (arm_opcodes): Add "esb".
1673         (thumb_opcodes): Likewise.
1674
1675 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1676
1677         * ppc-opc.c <xscmpnedp>: Delete.
1678         <xvcmpnedp>: Likewise.
1679         <xvcmpnedp.>: Likewise.
1680         <xvcmpnesp>: Likewise.
1681         <xvcmpnesp.>: Likewise.
1682
1683 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1684
1685         PR gas/13050
1686         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1687         addition to ISA_A.
1688
1689 2016-01-01  Alan Modra  <amodra@gmail.com>
1690
1691         Update year range in copyright notice of all files.
1692
1693 For older changes see ChangeLog-2015
1694 \f
1695 Copyright (C) 2016 Free Software Foundation, Inc.
1696
1697 Copying and distribution of this file, with or without modification,
1698 are permitted in any medium without royalty provided the copyright
1699 notice and this notice are preserved.
1700
1701 Local Variables:
1702 mode: change-log
1703 left-margin: 8
1704 fill-column: 74
1705 version-control: never
1706 End: