opcodes/ChangeLog

   1 2019-09-09  Phil Blundell  <pb@pbcl.net>
   2
   3         binutils 2.33 branch created.
   4
   5 2019-09-03  Nick Clifton  <nickc@redhat.com>
   6
   7         PR 24961
   8         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
   9         greater than zero before indexing via (bufcnt -1).
  10
  11 2019-09-03  Nick Clifton  <nickc@redhat.com>
  12
  13         PR 24958
  14         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
  15         (MAX_SPEC_REG_NAME_LEN): Define.
  16         (struct mmix_dis_info): Use defined constants for array lengths.
  17         (get_reg_name): New function.
  18         (get_sprec_reg_name): New function.
  19         (print_insn_mmix): Use new functions.
  20
  21 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  22
  23         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
  24         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
  25         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
  26
  27 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
  28
  29         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
  30         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
  31         (aarch64_sys_reg_supported_p): Update checks for the above.
  32
  33 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  34
  35         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
  36         cases MVE_SQRSHRL and MVE_UQRSHLL.
  37         (print_insn_mve): Add case for specifier 'k' to check
  38         specific bit of the instruction.
  39
  40 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
  41
  42         PR 24854
  43         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
  44         encountering an unknown machine type.
  45         (print_insn_arc): Handle arc_insn_length returning 0.  In error
  46         cases return -1 rather than calling abort.
  47
  48 2019-08-07  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
  51         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
  52         IgnoreSize.
  53         * i386-tbl.h: Re-generate.
  54
  55 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
  56
  57         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
  58         instructions.
  59
  60 2019-07-30  Mel Chen <mel.chen@sifive.com>
  61
  62         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
  63         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
  64
  65         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
  66         fscsr.
  67
  68 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  69
  70         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
  71         and MPY class instructions.
  72         (parse_option): Add nps400 option.
  73         (print_arc_disassembler_options): Add nps400 info.
  74
  75 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  76
  77         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
  78         (bspop): Likewise.
  79         (modapp): Likewise.
  80         * arc-opc.c (RAD_CHK): Add.
  81         * arc-tbl.h: Regenerate.
  82
  83 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  84
  85         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
  86         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
  87
  88 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
  89
  90         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
  91         instructions as UNPREDICTABLE.
  92
  93 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
  94
  95         * bpf-desc.c: Regenerated.
  96
  97 2019-07-17  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-gen.c (static_assert): Define.
 100         (main): Use it.
 101         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 102         (Opcode_Modifier_Num): ... this.
 103         (Mem): Delete.
 104
 105 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-gen.c (operand_types): Move RegMem ...
 108         (opcode_modifiers): ... here.
 109         * i386-opc.h (RegMem): Move to opcode modifer enum.
 110         (union i386_operand_type): Move regmem field ...
 111         (struct i386_opcode_modifier): ... here.
 112         * i386-opc.tbl (RegMem): Define.
 113         (mov, movq): Move RegMem on segment, control, debug, and test
 114         register flavors.
 115         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 116         to non-SSE2AVX flavor.
 117         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 118         Move RegMem on register only flavors. Drop IgnoreSize from
 119         legacy encoding flavors.
 120         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 121         flavors.
 122         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 123         register only flavors.
 124         (vmovd): Move RegMem and drop IgnoreSize on register only
 125         flavor. Change opcode and operand order to store form.
 126         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 127
 128 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 129
 130         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 131         entries.
 132         * i386-opc.h (SReg2, SReg3): Replace by ...
 133         (SReg): ... this.
 134         (union i386_operand_type): Replace sreg fields.
 135         * i386-opc.tbl (mov, ): Use SReg.
 136         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 137         register flavors.
 138         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 139         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 140
 141 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 142
 143         * bpf-desc.c: Regenerate.
 144         * bpf-opc.c: Likewise.
 145         * bpf-opc.h: Likewise.
 146
 147 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 148
 149         * bpf-desc.c: Regenerate.
 150         * bpf-opc.c: Likewise.
 151
 152 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 153
 154         * arm-dis.c (print_insn_coprocessor): Rename index to
 155         index_operand.
 156
 157 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 158
 159         * riscv-opc.c (riscv_insn_types): Add r4 type.
 160
 161         * riscv-opc.c (riscv_insn_types): Add b and j type.
 162
 163         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 164         format for sb type and correct s type.
 165
 166 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 167
 168         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 169         SVE FMOV alias of FCPY.
 170
 171 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 172
 173         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 174         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 175
 176 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 177
 178         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 179         registers in an instruction prefixed by MOVPRFX.
 180
 181 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 182
 183         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 184         sve_size_13 icode to account for variant behaviour of
 185         pmull{t,b}.
 186         * aarch64-dis-2.c: Regenerate.
 187         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 188         sve_size_13 icode to account for variant behaviour of
 189         pmull{t,b}.
 190         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 191         (OP_SVE_VVV_Q_D): Add new qualifier.
 192         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 193         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 194         AES and those not.
 195
 196 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 197
 198         * opcodes/i386-gen.c (operand_type_init): Remove
 199         OPERAND_TYPE_VEC_IMM4 entry.
 200         (operand_types): Remove Vec_Imm4.
 201         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 202         (union i386_operand_type): Remove vec_imm4.
 203         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 204         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 205
 206 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 207
 208         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 209         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 210         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 211         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 212         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 213         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 214         * i386-tbl.h: Re-generate.
 215
 216 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 219         register operands.
 220         * i386-tbl.h: Re-generate.
 221
 222 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 223
 224         * i386-opc.tbl (C): New.
 225         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 226         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 227         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 228         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 229         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 230         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 231         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 232         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 233         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 234         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 235         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 236         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 237         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 238         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 239         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 240         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 241         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 242         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 243         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 244         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 245         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 246         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 247         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 248         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 249         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 250         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 251         flavors.
 252         * i386-tbl.h: Re-generate.
 253
 254 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 255
 256         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 257         register operands.
 258         * i386-tbl.h: Re-generate.
 259
 260 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 263         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 264         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 265         * i386-tbl.h: Re-generate.
 266
 267 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 268
 269         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 270         Disp8MemShift from register only templates.
 271         * i386-tbl.h: Re-generate.
 272
 273 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 274
 275         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 276         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 277         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 278         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 279         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 280         EVEX_W_0F11_P_3_M_1): Delete.
 281         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 282         EVEX_W_0F11_P_3): New.
 283         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 284         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 285         MOD_EVEX_0F11_PREFIX_3 table entries.
 286         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 287         PREFIX_EVEX_0F11 table entries.
 288         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 289         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 290         EVEX_W_0F11_P_3_M_{0,1} table entries.
 291
 292 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 295         Delete.
 296
 297 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 298
 299         PR binutils/24719
 300         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 301         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 302         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 303         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 304         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 305         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 306         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 307         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 308         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 309         PREFIX_EVEX_0F38C6_REG_6 entries.
 310         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 311         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 312         EVEX_W_0F38C7_R_6_P_2 entries.
 313         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 314         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 315         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 316         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 317         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 318         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 319         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 320
 321 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 324         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 325         VEX_LEN_0F2D_P_3): Delete.
 326         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 327         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 328         (prefix_table): ... here.
 329
 330 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-dis.c (Iq): Delete.
 333         (Id): New.
 334         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 335         TBM insns.
 336         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 337         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 338         (OP_E_memory): Also honor needindex when deciding whether an
 339         address size prefix needs printing.
 340         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 341
 342 2019-06-26  Jim Wilson  <jimw@sifive.com>
 343
 344         PR binutils/24739
 345         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 346         Set info->display_endian to info->endian_code.
 347
 348 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 351         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 352         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 353         OPERAND_TYPE_ACC64 entries.
 354         * i386-init.h: Re-generate.
 355
 356 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 357
 358         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 359         Delete.
 360         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 361         of dqa_mode.
 362         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 363         entries here.
 364         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 365         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 366
 367 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 368
 369         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 370         variables.
 371
 372 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 373
 374         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 375         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 376         movnti.
 377         * i386-opc.tbl (movnti): Add IgnoreSize.
 378         * i386-tbl.h: Re-generate.
 379
 380 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 383         * i386-tbl.h: Re-generate.
 384
 385 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 386
 387         * i386-dis-evex.h: Break into ...
 388         * i386-dis-evex-len.h: New file.
 389         * i386-dis-evex-mod.h: Likewise.
 390         * i386-dis-evex-prefix.h: Likewise.
 391         * i386-dis-evex-reg.h: Likewise.
 392         * i386-dis-evex-w.h: Likewise.
 393         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 394         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 395         i386-dis-evex-mod.h.
 396
 397 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 398
 399         PR binutils/24700
 400         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 401         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 402         EVEX_W_0F385B_P_2.
 403         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 404         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 405         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 406         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 407         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 408         EVEX_LEN_0F385B_P_2_W_1.
 409         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 410         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 411         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 412         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 413         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 414         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 415         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 416         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 417         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 418         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 419
 420 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 421
 422         PR binutils/24691
 423         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 424         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 425         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 426         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 427         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 428         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 429         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 430         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 431         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 432         EVEX_LEN_0F3A43_P_2_W_1.
 433         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 434         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 435         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 436         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 437         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 438         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 439         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 440         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 441         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 442         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 443         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 444         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 445
 446 2019-06-14  Nick Clifton  <nickc@redhat.com>
 447
 448         * po/fr.po; Updated French translation.
 449
 450 2019-06-13  Stafford Horne  <shorne@gmail.com>
 451
 452         * or1k-asm.c: Regenerated.
 453         * or1k-desc.c: Regenerated.
 454         * or1k-desc.h: Regenerated.
 455         * or1k-dis.c: Regenerated.
 456         * or1k-ibld.c: Regenerated.
 457         * or1k-opc.c: Regenerated.
 458         * or1k-opc.h: Regenerated.
 459         * or1k-opinst.c: Regenerated.
 460
 461 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 462
 463         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 464
 465 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 466
 467         PR binutils/24633
 468         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 469         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 470         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 471         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 472         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 473         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 474         EVEX_LEN_0F3A1B_P_2_W_1.
 475         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 476         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 477         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 478         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 479         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 480         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 481         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 482         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 483
 484 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 485
 486         PR binutils/24626
 487         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 488         EVEX.vvvv when disassembling VEX and EVEX instructions.
 489         (OP_VEX): Set vex.register_specifier to 0 after readding
 490         vex.register_specifier.
 491         (OP_Vex_2src_1): Likewise.
 492         (OP_Vex_2src_2): Likewise.
 493         (OP_LWP_E): Likewise.
 494         (OP_EX_Vex): Don't check vex.register_specifier.
 495         (OP_XMM_Vex): Likewise.
 496
 497 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 498             Lili Cui  <lili.cui@intel.com>
 499
 500         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 501         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 502         instructions.
 503         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 504         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 505         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 506         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 507         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 508         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 509         * i386-init.h: Regenerated.
 510         * i386-tbl.h: Likewise.
 511
 512 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 513             Lili Cui  <lili.cui@intel.com>
 514
 515         * doc/c-i386.texi: Document enqcmd.
 516         * testsuite/gas/i386/enqcmd-intel.d: New file.
 517         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 518         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 519         * testsuite/gas/i386/enqcmd.d: Likewise.
 520         * testsuite/gas/i386/enqcmd.s: Likewise.
 521         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 522         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 523         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 524         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 525         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 526         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 527         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 528         and x86-64-enqcmd.
 529
 530 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 531
 532         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 533
 534 2019-06-03  Alan Modra  <amodra@gmail.com>
 535
 536         * ppc-dis.c (prefix_opcd_indices): Correct size.
 537
 538 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 539
 540         PR gas/24625
 541         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 542         Disp8ShiftVL.
 543         * i386-tbl.h: Regenerated.
 544
 545 2019-05-24  Alan Modra  <amodra@gmail.com>
 546
 547         * po/POTFILES.in: Regenerate.
 548
 549 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 550             Alan Modra  <amodra@gmail.com>
 551
 552         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 553         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 554         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 555         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 556         XTOP>): Define and add entries.
 557         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 558         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 559         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 560         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 561
 562 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 563             Alan Modra  <amodra@gmail.com>
 564
 565         * ppc-dis.c (ppc_opts): Add "future" entry.
 566         (PREFIX_OPCD_SEGS): Define.
 567         (prefix_opcd_indices): New array.
 568         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 569         (lookup_prefix): New function.
 570         (print_insn_powerpc): Handle 64-bit prefix instructions.
 571         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 572         (PMRR, POWERXX): Define.
 573         (prefix_opcodes): New instruction table.
 574         (prefix_num_opcodes): New constant.
 575
 576 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 577
 578         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 579         * configure: Regenerated.
 580         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 581         and cpu/bpf.opc.
 582         (HFILES): Add bpf-desc.h and bpf-opc.h.
 583         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 584         bpf-ibld.c and bpf-opc.c.
 585         (BPF_DEPS): Define.
 586         * Makefile.in: Regenerated.
 587         * disassemble.c (ARCH_bpf): Define.
 588         (disassembler): Add case for bfd_arch_bpf.
 589         (disassemble_init_for_target): Likewise.
 590         (enum epbf_isa_attr): Define.
 591         * disassemble.h: extern print_insn_bpf.
 592         * bpf-asm.c: Generated.
 593         * bpf-opc.h: Likewise.
 594         * bpf-opc.c: Likewise.
 595         * bpf-ibld.c: Likewise.
 596         * bpf-dis.c: Likewise.
 597         * bpf-desc.h: Likewise.
 598         * bpf-desc.c: Likewise.
 599
 600 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 601
 602         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 603         and VMSR with the new operands.
 604
 605 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 606
 607         * arm-dis.c (enum mve_instructions): New enum
 608         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 609         and cneg.
 610         (mve_opcodes): New instructions as above.
 611         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 612         csneg and csel.
 613         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 614
 615 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 616
 617         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 618         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 619         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 620         uqshl, urshrl and urshr.
 621         (is_mve_okay_in_it): Add new instructions to TRUE list.
 622         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 623         (print_insn_mve): Updated to accept new %j,
 624         %<bitfield>m and %<bitfield>n patterns.
 625
 626 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 627
 628         * mips-opc.c (mips_builtin_opcodes): Change source register
 629         constraint for DAUI.
 630
 631 2019-05-20  Nick Clifton  <nickc@redhat.com>
 632
 633         * po/fr.po: Updated French translation.
 634
 635 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 636             Michael Collison <michael.collison@arm.com>
 637
 638         * arm-dis.c (thumb32_opcodes): Add new instructions.
 639         (enum mve_instructions): Likewise.
 640         (enum mve_undefined): Add new reasons.
 641         (is_mve_encoding_conflict): Handle new instructions.
 642         (is_mve_undefined): Likewise.
 643         (is_mve_unpredictable): Likewise.
 644         (print_mve_undefined): Likewise.
 645         (print_mve_size): Likewise.
 646
 647 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 648             Michael Collison <michael.collison@arm.com>
 649
 650         * arm-dis.c (thumb32_opcodes): Add new instructions.
 651         (enum mve_instructions): Likewise.
 652         (is_mve_encoding_conflict): Handle new instructions.
 653         (is_mve_undefined): Likewise.
 654         (is_mve_unpredictable): Likewise.
 655         (print_mve_size): Likewise.
 656
 657 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 658             Michael Collison <michael.collison@arm.com>
 659
 660         * arm-dis.c (thumb32_opcodes): Add new instructions.
 661         (enum mve_instructions): Likewise.
 662         (is_mve_encoding_conflict): Likewise.
 663         (is_mve_unpredictable): Likewise.
 664         (print_mve_size): Likewise.
 665
 666 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 667             Michael Collison <michael.collison@arm.com>
 668
 669         * arm-dis.c (thumb32_opcodes): Add new instructions.
 670         (enum mve_instructions): Likewise.
 671         (is_mve_encoding_conflict): Handle new instructions.
 672         (is_mve_undefined): Likewise.
 673         (is_mve_unpredictable): Likewise.
 674         (print_mve_size): Likewise.
 675
 676 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 677             Michael Collison <michael.collison@arm.com>
 678
 679         * arm-dis.c (thumb32_opcodes): Add new instructions.
 680         (enum mve_instructions): Likewise.
 681         (is_mve_encoding_conflict): Handle new instructions.
 682         (is_mve_undefined): Likewise.
 683         (is_mve_unpredictable): Likewise.
 684         (print_mve_size): Likewise.
 685         (print_insn_mve): Likewise.
 686
 687 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 688             Michael Collison <michael.collison@arm.com>
 689
 690         * arm-dis.c (thumb32_opcodes): Add new instructions.
 691         (print_insn_thumb32): Handle new instructions.
 692
 693 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 694             Michael Collison <michael.collison@arm.com>
 695
 696         * arm-dis.c (enum mve_instructions): Add new instructions.
 697         (enum mve_undefined): Add new reasons.
 698         (is_mve_encoding_conflict): Handle new instructions.
 699         (is_mve_undefined): Likewise.
 700         (is_mve_unpredictable): Likewise.
 701         (print_mve_undefined): Likewise.
 702         (print_mve_size): Likewise.
 703         (print_mve_shift_n): Likewise.
 704         (print_insn_mve): Likewise.
 705
 706 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 707             Michael Collison <michael.collison@arm.com>
 708
 709         * arm-dis.c (enum mve_instructions): Add new instructions.
 710         (is_mve_encoding_conflict): Handle new instructions.
 711         (is_mve_unpredictable): Likewise.
 712         (print_mve_rotate): Likewise.
 713         (print_mve_size): Likewise.
 714         (print_insn_mve): Likewise.
 715
 716 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 717             Michael Collison <michael.collison@arm.com>
 718
 719         * arm-dis.c (enum mve_instructions): Add new instructions.
 720         (is_mve_encoding_conflict): Handle new instructions.
 721         (is_mve_unpredictable): Likewise.
 722         (print_mve_size): Likewise.
 723         (print_insn_mve): Likewise.
 724
 725 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 726             Michael Collison <michael.collison@arm.com>
 727
 728         * arm-dis.c (enum mve_instructions): Add new instructions.
 729         (enum mve_undefined): Add new reasons.
 730         (is_mve_encoding_conflict): Handle new instructions.
 731         (is_mve_undefined): Likewise.
 732         (is_mve_unpredictable): Likewise.
 733         (print_mve_undefined): Likewise.
 734         (print_mve_size): Likewise.
 735         (print_insn_mve): Likewise.
 736
 737 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 738             Michael Collison <michael.collison@arm.com>
 739
 740         * arm-dis.c (enum mve_instructions): Add new instructions.
 741         (is_mve_encoding_conflict): Handle new instructions.
 742         (is_mve_undefined): Likewise.
 743         (is_mve_unpredictable): Likewise.
 744         (print_mve_size): Likewise.
 745         (print_insn_mve): Likewise.
 746
 747 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 748             Michael Collison <michael.collison@arm.com>
 749
 750         * arm-dis.c (enum mve_instructions): Add new instructions.
 751         (enum mve_unpredictable): Add new reasons.
 752         (enum mve_undefined): Likewise.
 753         (is_mve_okay_in_it): Handle new isntructions.
 754         (is_mve_encoding_conflict): Likewise.
 755         (is_mve_undefined): Likewise.
 756         (is_mve_unpredictable): Likewise.
 757         (print_mve_vmov_index): Likewise.
 758         (print_simd_imm8): Likewise.
 759         (print_mve_undefined): Likewise.
 760         (print_mve_unpredictable): Likewise.
 761         (print_mve_size): Likewise.
 762         (print_insn_mve): Likewise.
 763
 764 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 765             Michael Collison <michael.collison@arm.com>
 766
 767         * arm-dis.c (enum mve_instructions): Add new instructions.
 768         (enum mve_unpredictable): Add new reasons.
 769         (enum mve_undefined): Likewise.
 770         (is_mve_encoding_conflict): Handle new instructions.
 771         (is_mve_undefined): Likewise.
 772         (is_mve_unpredictable): Likewise.
 773         (print_mve_undefined): Likewise.
 774         (print_mve_unpredictable): Likewise.
 775         (print_mve_rounding_mode): Likewise.
 776         (print_mve_vcvt_size): Likewise.
 777         (print_mve_size): Likewise.
 778         (print_insn_mve): Likewise.
 779
 780 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 781             Michael Collison <michael.collison@arm.com>
 782
 783         * arm-dis.c (enum mve_instructions): Add new instructions.
 784         (enum mve_unpredictable): Add new reasons.
 785         (enum mve_undefined): Likewise.
 786         (is_mve_undefined): Handle new instructions.
 787         (is_mve_unpredictable): Likewise.
 788         (print_mve_undefined): Likewise.
 789         (print_mve_unpredictable): Likewise.
 790         (print_mve_size): Likewise.
 791         (print_insn_mve): Likewise.
 792
 793 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 794             Michael Collison <michael.collison@arm.com>
 795
 796         * arm-dis.c (enum mve_instructions): Add new instructions.
 797         (enum mve_undefined): Add new reasons.
 798         (insns): Add new instructions.
 799         (is_mve_encoding_conflict):
 800         (print_mve_vld_str_addr): New print function.
 801         (is_mve_undefined): Handle new instructions.
 802         (is_mve_unpredictable): Likewise.
 803         (print_mve_undefined): Likewise.
 804         (print_mve_size): Likewise.
 805         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 806         (print_insn_mve):  Handle new operands.
 807
 808 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 809             Michael Collison <michael.collison@arm.com>
 810
 811         * arm-dis.c (enum mve_instructions): Add new instructions.
 812         (enum mve_unpredictable): Add new reasons.
 813         (is_mve_encoding_conflict): Handle new instructions.
 814         (is_mve_unpredictable): Likewise.
 815         (mve_opcodes): Add new instructions.
 816         (print_mve_unpredictable): Handle new reasons.
 817         (print_mve_register_blocks): New print function.
 818         (print_mve_size): Handle new instructions.
 819         (print_insn_mve): Likewise.
 820
 821 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 822             Michael Collison <michael.collison@arm.com>
 823
 824         * arm-dis.c (enum mve_instructions): Add new instructions.
 825         (enum mve_unpredictable): Add new reasons.
 826         (enum mve_undefined): Likewise.
 827         (is_mve_encoding_conflict): Handle new instructions.
 828         (is_mve_undefined): Likewise.
 829         (is_mve_unpredictable): Likewise.
 830         (coprocessor_opcodes): Move NEON VDUP from here...
 831         (neon_opcodes): ... to here.
 832         (mve_opcodes): Add new instructions.
 833         (print_mve_undefined):  Handle new reasons.
 834         (print_mve_unpredictable): Likewise.
 835         (print_mve_size): Handle new instructions.
 836         (print_insn_neon): Handle vdup.
 837         (print_insn_mve): Handle new operands.
 838
 839 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 840             Michael Collison <michael.collison@arm.com>
 841
 842         * arm-dis.c (enum mve_instructions): Add new instructions.
 843         (enum mve_unpredictable): Add new values.
 844         (mve_opcodes): Add new instructions.
 845         (vec_condnames): New array with vector conditions.
 846         (mve_predicatenames): New array with predicate suffixes.
 847         (mve_vec_sizename): New array with vector sizes.
 848         (enum vpt_pred_state): New enum with vector predication states.
 849         (struct vpt_block): New struct type for vpt blocks.
 850         (vpt_block_state): Global struct to keep track of state.
 851         (mve_extract_pred_mask): New helper function.
 852         (num_instructions_vpt_block): Likewise.
 853         (mark_outside_vpt_block): Likewise.
 854         (mark_inside_vpt_block): Likewise.
 855         (invert_next_predicate_state): Likewise.
 856         (update_next_predicate_state): Likewise.
 857         (update_vpt_block_state): Likewise.
 858         (is_vpt_instruction): Likewise.
 859         (is_mve_encoding_conflict): Add entries for new instructions.
 860         (is_mve_unpredictable): Likewise.
 861         (print_mve_unpredictable): Handle new cases.
 862         (print_instruction_predicate): Likewise.
 863         (print_mve_size): New function.
 864         (print_vec_condition): New function.
 865         (print_insn_mve): Handle vpt blocks and new print operands.
 866
 867 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 868
 869         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 870         8, 14 and 15 for Armv8.1-M Mainline.
 871
 872 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 873             Michael Collison <michael.collison@arm.com>
 874
 875         * arm-dis.c (enum mve_instructions): New enum.
 876         (enum mve_unpredictable): Likewise.
 877         (enum mve_undefined): Likewise.
 878         (struct mopcode32): New struct.
 879         (is_mve_okay_in_it): New function.
 880         (is_mve_architecture): Likewise.
 881         (arm_decode_field): Likewise.
 882         (arm_decode_field_multiple): Likewise.
 883         (is_mve_encoding_conflict): Likewise.
 884         (is_mve_undefined): Likewise.
 885         (is_mve_unpredictable): Likewise.
 886         (print_mve_undefined): Likewise.
 887         (print_mve_unpredictable): Likewise.
 888         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 889         (print_insn_mve): New function.
 890         (print_insn_thumb32): Handle MVE architecture.
 891         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 892
 893 2019-05-10  Nick Clifton  <nickc@redhat.com>
 894
 895         PR 24538
 896         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 897         end of the table prematurely.
 898
 899 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 900
 901         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 902         macros for R6.
 903
 904 2019-05-11  Alan Modra  <amodra@gmail.com>
 905
 906         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 907         when -Mraw is in effect.
 908
 909 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 910
 911         * aarch64-dis-2.c: Regenerate.
 912         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 913         (OP_SVE_BBB): New variant set.
 914         (OP_SVE_DDDD): New variant set.
 915         (OP_SVE_HHH): New variant set.
 916         (OP_SVE_HHHU): New variant set.
 917         (OP_SVE_SSS): New variant set.
 918         (OP_SVE_SSSU): New variant set.
 919         (OP_SVE_SHH): New variant set.
 920         (OP_SVE_SBBU): New variant set.
 921         (OP_SVE_DSS): New variant set.
 922         (OP_SVE_DHHU): New variant set.
 923         (OP_SVE_VMV_HSD_BHS): New variant set.
 924         (OP_SVE_VVU_HSD_BHS): New variant set.
 925         (OP_SVE_VVVU_SD_BH): New variant set.
 926         (OP_SVE_VVVU_BHSD): New variant set.
 927         (OP_SVE_VVV_QHD_DBS): New variant set.
 928         (OP_SVE_VVV_HSD_BHS): New variant set.
 929         (OP_SVE_VVV_HSD_BHS2): New variant set.
 930         (OP_SVE_VVV_BHS_HSD): New variant set.
 931         (OP_SVE_VV_BHS_HSD): New variant set.
 932         (OP_SVE_VVV_SD): New variant set.
 933         (OP_SVE_VVU_BHS_HSD): New variant set.
 934         (OP_SVE_VZVV_SD): New variant set.
 935         (OP_SVE_VZVV_BH): New variant set.
 936         (OP_SVE_VZV_SD): New variant set.
 937         (aarch64_opcode_table): Add sve2 instructions.
 938
 939 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 940
 941         * aarch64-asm-2.c: Regenerated.
 942         * aarch64-dis-2.c: Regenerated.
 943         * aarch64-opc-2.c: Regenerated.
 944         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 945         for SVE_SHLIMM_UNPRED_22.
 946         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 947         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 948         operand.
 949
 950 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 951
 952         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 953         sve_size_tsz_bhs iclass encode.
 954         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 955         sve_size_tsz_bhs iclass decode.
 956
 957 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 958
 959         * aarch64-asm-2.c: Regenerated.
 960         * aarch64-dis-2.c: Regenerated.
 961         * aarch64-opc-2.c: Regenerated.
 962         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 963         for SVE_Zm4_11_INDEX.
 964         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 965         (fields): Handle SVE_i2h field.
 966         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 967         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 968
 969 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 970
 971         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 972         sve_shift_tsz_bhsd iclass encode.
 973         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 974         sve_shift_tsz_bhsd iclass decode.
 975
 976 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 977
 978         * aarch64-asm-2.c: Regenerated.
 979         * aarch64-dis-2.c: Regenerated.
 980         * aarch64-opc-2.c: Regenerated.
 981         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 982         (aarch64_encode_variant_using_iclass): Handle
 983         sve_shift_tsz_hsd iclass encode.
 984         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 985         sve_shift_tsz_hsd iclass decode.
 986         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 987         for SVE_SHRIMM_UNPRED_22.
 988         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 989         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 990         operand.
 991
 992 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 993
 994         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 995         sve_size_013 iclass encode.
 996         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 997         sve_size_013 iclass decode.
 998
 999 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1000
1001         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1002         sve_size_bh iclass encode.
1003         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1004         sve_size_bh iclass decode.
1005
1006 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1007
1008         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1009         sve_size_sd2 iclass encode.
1010         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1011         sve_size_sd2 iclass decode.
1012         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1013         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1014
1015 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1016
1017         * aarch64-asm-2.c: Regenerated.
1018         * aarch64-dis-2.c: Regenerated.
1019         * aarch64-opc-2.c: Regenerated.
1020         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1021         for SVE_ADDR_ZX.
1022         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1023         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1024
1025 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1026
1027         * aarch64-asm-2.c: Regenerated.
1028         * aarch64-dis-2.c: Regenerated.
1029         * aarch64-opc-2.c: Regenerated.
1030         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1031         for SVE_Zm3_11_INDEX.
1032         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1033         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1034         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1035         fields.
1036         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1037
1038 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1039
1040         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1041         sve_size_hsd2 iclass encode.
1042         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1043         sve_size_hsd2 iclass decode.
1044         * aarch64-opc.c (fields): Handle SVE_size field.
1045         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1046
1047 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1048
1049         * aarch64-asm-2.c: Regenerated.
1050         * aarch64-dis-2.c: Regenerated.
1051         * aarch64-opc-2.c: Regenerated.
1052         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1053         for SVE_IMM_ROT3.
1054         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1055         (fields): Handle SVE_rot3 field.
1056         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1057         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1058
1059 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1060
1061         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1062         instructions.
1063
1064 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1065
1066         * aarch64-tbl.h
1067         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1068         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1069         aarch64_feature_sve2bitperm): New feature sets.
1070         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1071         for feature set addresses.
1072         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1073         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1074
1075 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1076             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1077
1078         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1079         argument and set ASE_EVA_R6 appropriately.
1080         (set_default_mips_dis_options): Pass ISA to above.
1081         (parse_mips_dis_option): Likewise.
1082         * mips-opc.c (EVAR6): New macro.
1083         (mips_builtin_opcodes): Add llwpe, scwpe.
1084
1085 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1086
1087         * aarch64-asm-2.c: Regenerated.
1088         * aarch64-dis-2.c: Regenerated.
1089         * aarch64-opc-2.c: Regenerated.
1090         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1091         AARCH64_OPND_TME_UIMM16.
1092         (aarch64_print_operand): Likewise.
1093         * aarch64-tbl.h (QL_IMM_NIL): New.
1094         (TME): New.
1095         (_TME_INSN): New.
1096         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1097
1098 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1099
1100         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1101
1102 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1103             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1104
1105         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1106
1107 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1108
1109         * s12z-opc.h: Add extern "C" bracketing to help
1110         users who wish to use this interface in c++ code.
1111
1112 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1113
1114         * s12z-opc.c (bm_decode): Handle bit map operations with the
1115         "reserved0" mode.
1116
1117 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1118
1119         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1120         specifier.  Add entries for VLDR and VSTR of system registers.
1121         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1122         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1123         of %J and %K format specifier.
1124
1125 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1126
1127         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1128         Add new entries for VSCCLRM instruction.
1129         (print_insn_coprocessor): Handle new %C format control code.
1130
1131 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1132
1133         * arm-dis.c (enum isa): New enum.
1134         (struct sopcode32): New structure.
1135         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1136         set isa field of all current entries to ANY.
1137         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1138         Only match an entry if its isa field allows the current mode.
1139
1140 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1141
1142         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1143         CLRM.
1144         (print_insn_thumb32): Add logic to print %n CLRM register list.
1145
1146 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1147
1148         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1149         and %Q patterns.
1150
1151 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1152
1153         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1154         (print_insn_thumb32): Edit the switch case for %Z.
1155
1156 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1157
1158         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1159
1160 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1161
1162         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1163
1164 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1165
1166         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1167
1168 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1169
1170         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1171         Arm register with r13 and r15 unpredictable.
1172         (thumb32_opcodes): New instructions for bfx and bflx.
1173
1174 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1175
1176         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1177
1178 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1179
1180         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1181
1182 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1183
1184         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1185
1186 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1187
1188         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1189
1190 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1191
1192         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1193         "optr". ("operator" is a reserved word in c++).
1194
1195 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1196
1197         * aarch64-opc.c (aarch64_print_operand): Add case for
1198         AARCH64_OPND_Rt_SP.
1199         (verify_constraints): Likewise.
1200         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1201         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1202         to accept Rt|SP as first operand.
1203         (AARCH64_OPERANDS): Add new Rt_SP.
1204         * aarch64-asm-2.c: Regenerated.
1205         * aarch64-dis-2.c: Regenerated.
1206         * aarch64-opc-2.c: Regenerated.
1207
1208 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1209
1210         * aarch64-asm-2.c: Regenerated.
1211         * aarch64-dis-2.c: Likewise.
1212         * aarch64-opc-2.c: Likewise.
1213         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1214
1215 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1216
1217         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1218
1219 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1220
1221         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1222         * i386-init.h: Regenerated.
1223
1224 2019-04-07  Alan Modra  <amodra@gmail.com>
1225
1226         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1227         op_separator to control printing of spaces, comma and parens
1228         rather than need_comma, need_paren and spaces vars.
1229
1230 2019-04-07  Alan Modra  <amodra@gmail.com>
1231
1232         PR 24421
1233         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1234         (print_insn_neon, print_insn_arm): Likewise.
1235
1236 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1237
1238         * i386-dis-evex.h (evex_table): Updated to support BF16
1239         instructions.
1240         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1241         and EVEX_W_0F3872_P_3.
1242         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1243         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1244         * i386-opc.h (enum): Add CpuAVX512_BF16.
1245         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1246         * i386-opc.tbl: Add AVX512 BF16 instructions.
1247         * i386-init.h: Regenerated.
1248         * i386-tbl.h: Likewise.
1249
1250 2019-04-05  Alan Modra  <amodra@gmail.com>
1251
1252         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1253         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1254         to favour printing of "-" branch hint when using the "y" bit.
1255         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1256
1257 2019-04-05  Alan Modra  <amodra@gmail.com>
1258
1259         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1260         opcode until first operand is output.
1261
1262 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1263
1264         PR gas/24349
1265         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1266         (valid_bo_post_v2): Add support for 'at' branch hints.
1267         (insert_bo): Only error on branch on ctr.
1268         (get_bo_hint_mask): New function.
1269         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1270         for inserting 'at' branch hints.
1271         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1272         for extracting 'at' branch hints.
1273         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1274         (BOE): Delete operand.
1275         (BOM, BOP): New operands.
1276         (RM): Update value.
1277         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1278         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1279         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1280         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1281         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1282         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1283         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1284         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1285         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1286         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1287         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1288         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1289         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1290         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1291         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1292         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1293         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1294         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1295         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1296         bttarl+>: New extended mnemonics.
1297
1298 2019-03-28  Alan Modra  <amodra@gmail.com>
1299
1300         PR 24390
1301         * ppc-opc.c (BTF): Define.
1302         (powerpc_opcodes): Use for mtfsb*.
1303         * ppc-dis.c (print_insn_powerpc): Print fields with both
1304         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1305
1306 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1307
1308         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1309         (mapping_symbol_for_insn): Implement new algorithm.
1310         (print_insn): Remove duplicate code.
1311
1312 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1313
1314         * aarch64-dis.c (print_insn_aarch64):
1315         Implement override.
1316
1317 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1318
1319         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1320         order.
1321
1322 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1323
1324         * aarch64-dis.c (last_stop_offset): New.
1325         (print_insn_aarch64): Use stop_offset.
1326
1327 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1328
1329         PR gas/24359
1330         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1331         CPU_ANY_AVX2_FLAGS.
1332         * i386-init.h: Regenerated.
1333
1334 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1335
1336         PR gas/24348
1337         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1338         vmovdqu16, vmovdqu32 and vmovdqu64.
1339         * i386-tbl.h: Regenerated.
1340
1341 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1342
1343         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1344         from vstrszb, vstrszh, and vstrszf.
1345
1346 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1347
1348         * s390-opc.txt: Add instruction descriptions.
1349
1350 2019-02-08  Jim Wilson  <jimw@sifive.com>
1351
1352         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1353         <bne>: Likewise.
1354
1355 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1356
1357         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1358
1359 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1360
1361         PR binutils/23212
1362         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1363         * aarch64-opc.c (verify_elem_sd): New.
1364         (fields): Add FLD_sz entr.
1365         * aarch64-tbl.h (_SIMD_INSN): New.
1366         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1367         fmulx scalar and vector by element isns.
1368
1369 2019-02-07  Nick Clifton  <nickc@redhat.com>
1370
1371         * po/sv.po: Updated Swedish translation.
1372
1373 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1374
1375         * s390-mkopc.c (main): Accept arch13 as cpu string.
1376         * s390-opc.c: Add new instruction formats and instruction opcode
1377         masks.
1378         * s390-opc.txt: Add new arch13 instructions.
1379
1380 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1381
1382         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1383         (aarch64_opcode): Change encoding for stg, stzg
1384         st2g and st2zg.
1385         * aarch64-asm-2.c: Regenerated.
1386         * aarch64-dis-2.c: Regenerated.
1387         * aarch64-opc-2.c: Regenerated.
1388
1389 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1390
1391         * aarch64-asm-2.c: Regenerated.
1392         * aarch64-dis-2.c: Likewise.
1393         * aarch64-opc-2.c: Likewise.
1394         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1395
1396 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1397             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1398
1399         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1400         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1401         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1402         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1403         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1404         case for ldstgv_indexed.
1405         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1406         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1407         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1408         * aarch64-asm-2.c: Regenerated.
1409         * aarch64-dis-2.c: Regenerated.
1410         * aarch64-opc-2.c: Regenerated.
1411
1412 2019-01-23  Nick Clifton  <nickc@redhat.com>
1413
1414         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1415
1416 2019-01-21  Nick Clifton  <nickc@redhat.com>
1417
1418         * po/de.po: Updated German translation.
1419         * po/uk.po: Updated Ukranian translation.
1420
1421 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1422         * mips-dis.c (mips_arch_choices): Fix typo in
1423         gs464, gs464e and gs264e descriptors.
1424
1425 2019-01-19  Nick Clifton  <nickc@redhat.com>
1426
1427         * configure: Regenerate.
1428         * po/opcodes.pot: Regenerate.
1429
1430 2018-06-24  Nick Clifton  <nickc@redhat.com>
1431
1432         2.32 branch created.
1433
1434 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1435
1436         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1437         if it is null.
1438         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1439         zero.
1440
1441 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1442
1443         * configure: Regenerate.
1444
1445 2019-01-07  Alan Modra  <amodra@gmail.com>
1446
1447         * configure: Regenerate.
1448         * po/POTFILES.in: Regenerate.
1449
1450 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1451
1452         * s12z-opc.c: New file.
1453         * s12z-opc.h: New file.
1454         * s12z-dis.c: Removed all code not directly related to display
1455         of instructions.  Used the interface provided by the new files
1456         instead.
1457         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1458         * Makefile.in: Regenerate.
1459         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1460         * configure: Regenerate.
1461
1462 2019-01-01  Alan Modra  <amodra@gmail.com>
1463
1464         Update year range in copyright notice of all files.
1465
1466 For older changes see ChangeLog-2018
1467 \f
1468 Copyright (C) 2019 Free Software Foundation, Inc.
1469
1470 Copying and distribution of this file, with or without modification,
1471 are permitted in any medium without royalty provided the copyright
1472 notice and this notice are preserved.
1473
1474 Local Variables:
1475 mode: change-log
1476 left-margin: 8
1477 fill-column: 74
1478 version-control: never
1479 End: