opcodes/ChangeLog

   1 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
   2
   3         * opcodes/arm-dis.c: Support MVFR2 in disassembly
   4         with vmrs and vmsr.
   5
   6 2017-07-04  Tristan Gingold  <gingold@adacore.com>
   7
   8         * configure: Regenerate.
   9
  10 2017-07-03  Tristan Gingold  <gingold@adacore.com>
  11
  12         * po/opcodes.pot: Regenerate.
  13
  14 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
  15
  16         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
  17         entries to the MSA ASE instruction block.
  18
  19 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
  20             Maciej W. Rozycki  <macro@imgtec.com>
  21
  22         * micromips-opc.c (XPA, XPAVZ): New macros.
  23         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
  24         "mthgc0".
  25
  26 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
  27             Maciej W. Rozycki  <macro@imgtec.com>
  28
  29         * micromips-opc.c (I36): New macro.
  30         (micromips_opcodes): Add "eretnc".
  31
  32 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
  33             Andrew Bennett  <andrew.bennett@imgtec.com>
  34
  35         * mips-dis.c (mips_calculate_combination_ases): Handle the
  36         ASE_XPA_VIRT flag.
  37         (parse_mips_ase_option): New function.
  38         (parse_mips_dis_option): Factor out ASE option handling to the
  39         new function.  Call `mips_calculate_combination_ases'.
  40         * mips-opc.c (XPAVZ): New macro.
  41         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
  42         "mfhgc0", "mthc0" and "mthgc0".
  43
  44 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
  45
  46         * mips-dis.c (mips_calculate_combination_ases): New function.
  47         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
  48         calculation to the new function.
  49         (set_default_mips_dis_options): Call the new function.
  50
  51 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  52
  53         * arc-dis.c (parse_disassembler_options): Use
  54         FOR_EACH_DISASSEMBLER_OPTION.
  55
  56 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  57
  58         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
  59         disassembler option strings.
  60         (parse_cpu_option): Likewise.
  61
  62 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
  63
  64         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
  65         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
  66         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
  67         (aarch64_feature_dotprod, DOT_INSN): New.
  68         (udot, sdot): New.
  69         * aarch64-dis-2.c: Regenerated.
  70
  71 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
  72
  73         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
  74
  75 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
  76             Matthew Fortune  <matthew.fortune@imgtec.com>
  77             Andrew Bennett  <andrew.bennett@imgtec.com>
  78
  79         * mips-formats.h (INT_BIAS): New macro.
  80         (INT_ADJ): Redefine in INT_BIAS terms.
  81         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
  82         (mips_print_save_restore): New function.
  83         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
  84         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
  85         call.
  86         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
  87         (print_mips16_insn_arg): Call `mips_print_save_restore' for
  88         OP_SAVE_RESTORE_LIST handling, factored out from here.
  89         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
  90         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
  91         (mips_builtin_opcodes): Add "restore" and "save" entries.
  92         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
  93         (IAMR2): New macro.
  94         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
  95
  96 2017-06-23  Andrew Waterman  <andrew@sifive.com>
  97
  98         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
  99         alias; do not mark SLTI instruction as an alias.
 100
 101 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 102
 103         * i386-dis.c (RM_0FAE_REG_5): Removed.
 104         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 105         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 106         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 107         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 108         PREFIX_MOD_3_0F01_REG_5_RM_0.
 109         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 110         PREFIX_MOD_3_0FAE_REG_5.
 111         (mod_table): Update MOD_0FAE_REG_5.
 112         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 113         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 114         * i386-tbl.h: Regenerated.
 115
 116 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 117
 118         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 119         * i386-opc.tbl: Likewise.
 120         * i386-tbl.h: Regenerated.
 121
 122 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 123
 124         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 125         and "jmp{&|}".
 126         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 127         prefix.
 128
 129 2017-06-19  Nick Clifton  <nickc@redhat.com>
 130
 131         PR binutils/21614
 132         * score-dis.c (score_opcodes): Add sentinel.
 133
 134 2017-06-16  Alan Modra  <amodra@gmail.com>
 135
 136         * rx-decode.c: Regenerate.
 137
 138 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 139
 140         PR binutils/21594
 141         * i386-dis.c (OP_E_register): Check valid bnd register.
 142         (OP_G): Likewise.
 143
 144 2017-06-15  Nick Clifton  <nickc@redhat.com>
 145
 146         PR binutils/21595
 147         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 148         range value.
 149
 150 2017-06-15  Nick Clifton  <nickc@redhat.com>
 151
 152         PR binutils/21588
 153         * rl78-decode.opc (OP_BUF_LEN): Define.
 154         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 155         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 156         array.
 157         * rl78-decode.c: Regenerate.
 158
 159 2017-06-15  Nick Clifton  <nickc@redhat.com>
 160
 161         PR binutils/21586
 162         * bfin-dis.c (gregs): Clip index to prevent overflow.
 163         (regs): Likewise.
 164         (regs_lo): Likewise.
 165         (regs_hi): Likewise.
 166
 167 2017-06-14  Nick Clifton  <nickc@redhat.com>
 168
 169         PR binutils/21576
 170         * score7-dis.c (score_opcodes): Add sentinel.
 171
 172 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 173
 174         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 175         * arm-dis.c: Likewise.
 176         * ia64-dis.c: Likewise.
 177         * mips-dis.c: Likewise.
 178         * spu-dis.c: Likewise.
 179         * disassemble.h (print_insn_aarch64): New declaration, moved from
 180         include/dis-asm.h.
 181         (print_insn_big_arm, print_insn_big_mips): Likewise.
 182         (print_insn_i386, print_insn_ia64): Likewise.
 183         (print_insn_little_arm, print_insn_little_mips): Likewise.
 184
 185 2017-06-14  Nick Clifton  <nickc@redhat.com>
 186
 187         PR binutils/21587
 188         * rx-decode.opc: Include libiberty.h
 189         (GET_SCALE): New macro - validates access to SCALE array.
 190         (GET_PSCALE): New macro - validates access to PSCALE array.
 191         (DIs, SIs, S2Is, rx_disp): Use new macros.
 192         * rx-decode.c: Regenerate.
 193
 194 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 195
 196         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 197
 198 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 199
 200         * arc-dis.c (enforced_isa_mask): Declare.
 201         (cpu_types): Likewise.
 202         (parse_cpu_option): New function.
 203         (parse_disassembler_options): Use it.
 204         (print_insn_arc): Use enforced_isa_mask.
 205         (print_arc_disassembler_options): Document new options.
 206
 207 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 208
 209         * alpha-dis.c: Include disassemble.h, don't include
 210         dis-asm.h.
 211         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 212         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 213         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 214         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 215         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 216         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 217         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 218         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 219         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 220         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 221         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 222         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 223         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 224         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 225         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 226         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 227         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 228         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 229         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 230         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 231         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 232         * z80-dis.c, z8k-dis.c: Likewise.
 233         * disassemble.h: New file.
 234
 235 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 236
 237         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 238         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 239
 240 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 241
 242         * disassemble.c (disassembler): Add arguments a, big and mach.
 243         Use them.
 244
 245 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 246
 247         * i386-dis.c (NOTRACK_Fixup): New.
 248         (NOTRACK): Likewise.
 249         (NOTRACK_PREFIX): Likewise.
 250         (last_active_prefix): Likewise.
 251         (reg_table): Use NOTRACK on indirect call and jmp.
 252         (ckprefix): Set last_active_prefix.
 253         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 254         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 255         * i386-opc.h (NoTrackPrefixOk): New.
 256         (i386_opcode_modifier): Add notrackprefixok.
 257         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 258         Add notrack.
 259         * i386-tbl.h: Regenerated.
 260
 261 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 262
 263         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 264         (X_IMM2): Define.
 265         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 266         bfd_mach_sparc_v9m8.
 267         (print_insn_sparc): Handle new operand types.
 268         * sparc-opc.c (MASK_M8): Define.
 269         (v6): Add MASK_M8.
 270         (v6notlet): Likewise.
 271         (v7): Likewise.
 272         (v8): Likewise.
 273         (v9): Likewise.
 274         (v9a): Likewise.
 275         (v9b): Likewise.
 276         (v9c): Likewise.
 277         (v9d): Likewise.
 278         (v9e): Likewise.
 279         (v9v): Likewise.
 280         (v9m): Likewise.
 281         (v9andleon): Likewise.
 282         (m8): Define.
 283         (HWS_VM8): Define.
 284         (HWS2_VM8): Likewise.
 285         (sparc_opcode_archs): Add entry for "m8".
 286         (sparc_opcodes): Add OSA2017 and M8 instructions
 287         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 288         fpx{ll,ra,rl}64x,
 289         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 290         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 291         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 292         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 293         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 294         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 295         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 296         ASI_CORE_SELECT_COMMIT_NHT.
 297
 298 2017-05-18  Alan Modra  <amodra@gmail.com>
 299
 300         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 301         * aarch64-dis.c: Likewise.
 302         * aarch64-gen.c: Likewise.
 303         * aarch64-opc.c: Likewise.
 304
 305 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 306             Matthew Fortune  <matthew.fortune@imgtec.com>
 307
 308         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 309         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 310         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 311         (print_insn_arg) <OP_REG28>: Add handler.
 312         (validate_insn_args) <OP_REG28>: Handle.
 313         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 314         32-bit encoding and 9-bit immediates.
 315         (print_insn_mips16): Handle MIPS16 instructions that require
 316         32-bit encoding and MFC0/MTC0 operand decoding.
 317         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 318         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 319         (RD_C0, WR_C0, E2, E2MT): New macros.
 320         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 321         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 322         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 323         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 324         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 325         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 326         instructions, "swl", "swr", "sync" and its "sync_acquire",
 327         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 328         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 329         regular/extended entries for original MIPS16 ISA revision
 330         instructions whose extended forms are subdecoded in the MIPS16e2
 331         ISA revision: "li", "sll" and "srl".
 332
 333 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 334
 335         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 336         reference in CP0 move operand decoding.
 337
 338 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 339
 340         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 341         type to hexadecimal.
 342         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 343
 344 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 345
 346         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 347         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 348         "sync_rmb" and "sync_wmb" as aliases.
 349         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 350         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 351
 352 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 353
 354         * arc-dis.c (parse_option): Update quarkse_em option..
 355         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 356         QUARKSE1.
 357         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 358
 359 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 360
 361         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 362
 363 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 364
 365         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 366         register.
 367
 368 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 369
 370         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 371         and branches and not synthetic data instructions.
 372
 373 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 374
 375         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 376
 377 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 378
 379         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 380         * arc-opc.c (insert_r13el): New function.
 381         (R13_EL): Define.
 382         * arc-tbl.h: Add new enter/leave variants.
 383
 384 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 385
 386         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 387
 388 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 389
 390         * mips-dis.c (print_mips_disassembler_options): Add
 391         `no-aliases'.
 392
 393 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 394
 395         * mips16-opc.c (AL): New macro.
 396         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 397         of "ld" and "lw" as aliases.
 398
 399 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 400
 401         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 402         arguments.
 403
 404 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 405             Alan Modra  <amodra@gmail.com>
 406
 407         * ppc-opc.c (ELEV): Define.
 408         (vle_opcodes): Add se_rfgi and e_sc.
 409         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 410         for E200Z4.
 411
 412 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 413
 414         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 415
 416 2017-04-21  Nick Clifton  <nickc@redhat.com>
 417
 418         PR binutils/21380
 419         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 420         LD3R and LD4R.
 421
 422 2017-04-13  Alan Modra  <amodra@gmail.com>
 423
 424         * epiphany-desc.c: Regenerate.
 425         * fr30-desc.c: Regenerate.
 426         * frv-desc.c: Regenerate.
 427         * ip2k-desc.c: Regenerate.
 428         * iq2000-desc.c: Regenerate.
 429         * lm32-desc.c: Regenerate.
 430         * m32c-desc.c: Regenerate.
 431         * m32r-desc.c: Regenerate.
 432         * mep-desc.c: Regenerate.
 433         * mt-desc.c: Regenerate.
 434         * or1k-desc.c: Regenerate.
 435         * xc16x-desc.c: Regenerate.
 436         * xstormy16-desc.c: Regenerate.
 437
 438 2017-04-11  Alan Modra  <amodra@gmail.com>
 439
 440         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 441         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 442         PPC_OPCODE_TMR for e6500.
 443         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 444         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 445         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 446         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 447         (PPCHTM): Define as PPC_OPCODE_POWER8.
 448         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 449
 450 2017-04-10  Alan Modra  <amodra@gmail.com>
 451
 452         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 453         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 454         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 455         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 456
 457 2017-04-09  Pip Cet  <pipcet@gmail.com>
 458
 459         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 460         appropriate floating-point precision directly.
 461
 462 2017-04-07  Alan Modra  <amodra@gmail.com>
 463
 464         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 465         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 466         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 467         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 468         vector instructions with E6500 not PPCVEC2.
 469
 470 2017-04-06  Pip Cet  <pipcet@gmail.com>
 471
 472         * Makefile.am: Add wasm32-dis.c.
 473         * configure.ac: Add wasm32-dis.c to wasm32 target.
 474         * disassemble.c: Add wasm32 disassembler code.
 475         * wasm32-dis.c: New file.
 476         * Makefile.in: Regenerate.
 477         * configure: Regenerate.
 478         * po/POTFILES.in: Regenerate.
 479         * po/opcodes.pot: Regenerate.
 480
 481 2017-04-05  Pedro Alves  <palves@redhat.com>
 482
 483         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 484         * arm-dis.c (parse_arm_disassembler_options): Constify.
 485         * ppc-dis.c (powerpc_init_dialect): Constify local.
 486         * vax-dis.c (parse_disassembler_options): Constify.
 487
 488 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 489
 490         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 491         RISCV_GP_SYMBOL.
 492
 493 2017-03-30  Pip Cet  <pipcet@gmail.com>
 494
 495         * configure.ac: Add (empty) bfd_wasm32_arch target.
 496         * configure: Regenerate
 497         * po/opcodes.pot: Regenerate.
 498
 499 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 500
 501         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 502         OSA2015.
 503         * opcodes/sparc-opc.c (asi_table): New ASIs.
 504
 505 2017-03-29  Alan Modra  <amodra@gmail.com>
 506
 507         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 508         "raw" option.
 509         (lookup_powerpc): Don't special case -1 dialect.  Handle
 510         PPC_OPCODE_RAW.
 511         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 512         lookup_powerpc call, pass it on second.
 513
 514 2017-03-27  Alan Modra  <amodra@gmail.com>
 515
 516         PR 21303
 517         * ppc-dis.c (struct ppc_mopt): Comment.
 518         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 519
 520 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 521
 522         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 523         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 524         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 525         (insert_nps_misc_imm_offset): New function.
 526         (extract_nps_misc imm_offset): New function.
 527         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 528         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 529
 530 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 531
 532         * s390-mkopc.c (main): Remove vx2 check.
 533         * s390-opc.txt: Remove vx2 instruction flags.
 534
 535 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 536
 537         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 538         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 539         (insert_nps_imm_offset): New function.
 540         (extract_nps_imm_offset): New function.
 541         (insert_nps_imm_entry): New function.
 542         (extract_nps_imm_entry): New function.
 543
 544 2017-03-17  Alan Modra  <amodra@gmail.com>
 545
 546         PR 21248
 547         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 548         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 549         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 550
 551 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 552
 553         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 554         <c.andi>: Likewise.
 555         <c.addiw> Likewise.
 556
 557 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 558
 559         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 560
 561 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 562
 563         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 564         <srl> Likewise.
 565         <srai> Likewise.
 566         <sra> Likewise.
 567
 568 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 569
 570         * i386-gen.c (opcode_modifiers): Replace S with Load.
 571         * i386-opc.h (S): Removed.
 572         (Load): New.
 573         (i386_opcode_modifier): Replace s with load.
 574         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 575         and {evex}.  Replace S with Load.
 576         * i386-tbl.h: Regenerated.
 577
 578 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 579
 580         * i386-opc.tbl: Use CpuCET on rdsspq.
 581         * i386-tbl.h: Regenerated.
 582
 583 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 584
 585         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 586         <vsx>: Do not use PPC_OPCODE_VSX3;
 587
 588 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 589
 590         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 591
 592 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 593
 594         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 595         (MOD_0F1E_PREFIX_1): Likewise.
 596         (MOD_0F38F5_PREFIX_2): Likewise.
 597         (MOD_0F38F6_PREFIX_0): Likewise.
 598         (RM_0F1E_MOD_3_REG_7): Likewise.
 599         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 600         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 601         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 602         (PREFIX_0F1E): Likewise.
 603         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 604         (PREFIX_0F38F5): Likewise.
 605         (dis386_twobyte): Use PREFIX_0F1E.
 606         (reg_table): Add REG_0F1E_MOD_3.
 607         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 608         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 609         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 610         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 611         (three_byte_table): Use PREFIX_0F38F5.
 612         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 613         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 614         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 615         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 616         PREFIX_MOD_3_0F01_REG_5_RM_2.
 617         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 618         (cpu_flags): Add CpuCET.
 619         * i386-opc.h (CpuCET): New enum.
 620         (CpuUnused): Commented out.
 621         (i386_cpu_flags): Add cpucet.
 622         * i386-opc.tbl: Add Intel CET instructions.
 623         * i386-init.h: Regenerated.
 624         * i386-tbl.h: Likewise.
 625
 626 2017-03-06  Alan Modra  <amodra@gmail.com>
 627
 628         PR 21124
 629         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 630         (extract_raq, extract_ras, extract_rbx): New functions.
 631         (powerpc_operands): Use opposite corresponding insert function.
 632         (Q_MASK): Define.
 633         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 634         register restriction.
 635
 636 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 637
 638         * disassemble.c Include "safe-ctype.h".
 639         (disassemble_init_for_target): Handle s390 init.
 640         (remove_whitespace_and_extra_commas): New function.
 641         (disassembler_options_cmp): Likewise.
 642         * arm-dis.c: Include "libiberty.h".
 643         (NUM_ELEM): Delete.
 644         (regnames): Use long disassembler style names.
 645         Add force-thumb and no-force-thumb options.
 646         (NUM_ARM_REGNAMES): Rename from this...
 647         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 648         (get_arm_regname_num_options): Delete.
 649         (set_arm_regname_option): Likewise.
 650         (get_arm_regnames): Likewise.
 651         (parse_disassembler_options): Likewise.
 652         (parse_arm_disassembler_option): Rename from this...
 653         (parse_arm_disassembler_options): ...to this.  Make static.
 654         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 655         (print_insn): Use parse_arm_disassembler_options.
 656         (disassembler_options_arm): New function.
 657         (print_arm_disassembler_options): Handle updated regnames.
 658         * ppc-dis.c: Include "libiberty.h".
 659         (ppc_opts): Add "32" and "64" entries.
 660         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 661         (powerpc_init_dialect): Add break to switch statement.
 662         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 663         (disassembler_options_powerpc): New function.
 664         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 665         Remove printing of "32" and "64".
 666         * s390-dis.c: Include "libiberty.h".
 667         (init_flag): Remove unneeded variable.
 668         (struct s390_options_t): New structure type.
 669         (options): New structure.
 670         (init_disasm): Rename from this...
 671         (disassemble_init_s390): ...to this.  Add initializations for
 672         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 673         (print_insn_s390): Delete call to init_disasm.
 674         (disassembler_options_s390): New function.
 675         (print_s390_disassembler_options): Print using information from
 676         struct 'options'.
 677         * po/opcodes.pot: Regenerate.
 678
 679 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 680
 681         * i386-dis.c (PCMPESTR_Fixup): New.
 682         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 683         (prefix_table): Use PCMPESTR_Fixup.
 684         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 685         PCMPESTR_Fixup.
 686         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 687         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 688         Split 64-bit and non-64-bit variants.
 689         * opcodes/i386-tbl.h: Re-generate.
 690
 691 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 692
 693         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 694         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 695         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 696         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 697         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 698         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 699         (OP_SVE_V_HSD): New macros.
 700         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 701         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 702         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 703         (aarch64_opcode_table): Add new SVE instructions.
 704         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 705         for rotation operands.  Add new SVE operands.
 706         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 707         (ins_sve_quad_index): Likewise.
 708         (ins_imm_rotate): Split into...
 709         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 710         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 711         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 712         functions.
 713         (aarch64_ins_sve_addr_ri_s4): New function.
 714         (aarch64_ins_sve_quad_index): Likewise.
 715         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 716         * aarch64-asm-2.c: Regenerate.
 717         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 718         (ext_sve_quad_index): Likewise.
 719         (ext_imm_rotate): Split into...
 720         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 721         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 722         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 723         functions.
 724         (aarch64_ext_sve_addr_ri_s4): New function.
 725         (aarch64_ext_sve_quad_index): Likewise.
 726         (aarch64_ext_sve_index): Allow quad indices.
 727         (do_misc_decoding): Likewise.
 728         * aarch64-dis-2.c: Regenerate.
 729         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 730         aarch64_field_kinds.
 731         (OPD_F_OD_MASK): Widen by one bit.
 732         (OPD_F_NO_ZR): Bump accordingly.
 733         (get_operand_field_width): New function.
 734         * aarch64-opc.c (fields): Add new SVE fields.
 735         (operand_general_constraint_met_p): Handle new SVE operands.
 736         (aarch64_print_operand): Likewise.
 737         * aarch64-opc-2.c: Regenerate.
 738
 739 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 740
 741         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 742         (aarch64_feature_compnum): ...this.
 743         (SIMD_V8_3): Replace with...
 744         (COMPNUM): ...this.
 745         (CNUM_INSN): New macro.
 746         (aarch64_opcode_table): Use it for the complex number instructions.
 747
 748 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 749
 750         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 751
 752 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 753
 754         Add support for associating SPARC ASIs with an architecture level.
 755         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 756         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 757         decoding of SPARC ASIs.
 758
 759 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 760
 761         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 762         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 763
 764 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 765
 766         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 767         1 (instead of to itself). Correct typo.
 768
 769 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 770
 771         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 772         pseudoinstructions.
 773
 774 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 775
 776         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 777         (aarch64_sys_reg_supported_p): Handle them.
 778
 779 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 780
 781         * arc-opc.c (UIMM6_20R): Define.
 782         (SIMM12_20): Use above.
 783         (SIMM12_20R): Define.
 784         (SIMM3_5_S): Use above.
 785         (UIMM7_A32_11R_S): Define.
 786         (UIMM7_9_S): Use above.
 787         (UIMM3_13R_S): Define.
 788         (SIMM11_A32_7_S): Use above.
 789         (SIMM9_8R): Define.
 790         (UIMM10_A32_8_S): Use above.
 791         (UIMM8_8R_S): Define.
 792         (W6): Use above.
 793         (arc_relax_opcodes): Use all above defines.
 794
 795 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 796
 797         * arc-regs.h: Distinguish some of the registers different on
 798         ARC700 and HS38 cpus.
 799
 800 2017-02-14  Alan Modra  <amodra@gmail.com>
 801
 802         PR 21118
 803         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 804         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 805
 806 2017-02-11  Stafford Horne  <shorne@gmail.com>
 807             Alan Modra  <amodra@gmail.com>
 808
 809         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 810         Use insn_bytes_value and insn_int_value directly instead.  Don't
 811         free allocated memory until function exit.
 812
 813 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 814
 815         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 816
 817 2017-02-03  Nick Clifton  <nickc@redhat.com>
 818
 819         PR 21096
 820         * aarch64-opc.c (print_register_list): Ensure that the register
 821         list index will fir into the tb buffer.
 822         (print_register_offset_address): Likewise.
 823         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 824
 825 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 826
 827         PR 21056
 828         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 829         instructions when the previous fetch packet ends with a 32-bit
 830         instruction.
 831
 832 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 833
 834         * pru-opc.c: Remove vague reference to a future GDB port.
 835
 836 2017-01-20  Nick Clifton  <nickc@redhat.com>
 837
 838         * po/ga.po: Updated Irish translation.
 839
 840 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 841
 842         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 843
 844 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 845
 846         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 847         if FETCH_DATA returns 0.
 848         (m68k_scan_mask): Likewise.
 849         (print_insn_m68k): Update code to handle -1 return value.
 850
 851 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 852
 853         * m68k-dis.c (enum print_insn_arg_error): New.
 854         (NEXTBYTE): Replace -3 with
 855         PRINT_INSN_ARG_MEMORY_ERROR.
 856         (NEXTULONG): Likewise.
 857         (NEXTSINGLE): Likewise.
 858         (NEXTDOUBLE): Likewise.
 859         (NEXTDOUBLE): Likewise.
 860         (NEXTPACKED): Likewise.
 861         (FETCH_ARG): Likewise.
 862         (FETCH_DATA): Update comments.
 863         (print_insn_arg): Update comments. Replace magic numbers with
 864         enum.
 865         (match_insn_m68k): Likewise.
 866
 867 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 868
 869         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 870         * i386-dis-evex.h (evex_table): Updated.
 871         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 872         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 873         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 874         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 875         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 876         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 877         * i386-init.h: Regenerate.
 878         * i386-tbl.h: Ditto.
 879
 880 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 881
 882         * msp430-dis.c (msp430_singleoperand): Return -1 if
 883         msp430dis_opcode_signed returns false.
 884         (msp430_doubleoperand): Likewise.
 885         (msp430_branchinstr): Return -1 if
 886         msp430dis_opcode_unsigned returns false.
 887         (msp430x_calla_instr): Likewise.
 888         (print_insn_msp430): Likewise.
 889
 890 2017-01-05  Nick Clifton  <nickc@redhat.com>
 891
 892         PR 20946
 893         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 894         could not be matched.
 895         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 896         NULL.
 897
 898 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 899
 900         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 901         (aarch64_opcode_table): Use RCPC_INSN.
 902
 903 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 904
 905         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 906         extension.
 907         * riscv-opcodes/all-opcodes: Likewise.
 908
 909 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 910
 911         * riscv-dis.c (print_insn_args): Add fall through comment.
 912
 913 2017-01-03  Nick Clifton  <nickc@redhat.com>
 914
 915         * po/sr.po: New Serbian translation.
 916         * configure.ac (ALL_LINGUAS): Add sr.
 917         * configure: Regenerate.
 918
 919 2017-01-02  Alan Modra  <amodra@gmail.com>
 920
 921         * epiphany-desc.h: Regenerate.
 922         * epiphany-opc.h: Regenerate.
 923         * fr30-desc.h: Regenerate.
 924         * fr30-opc.h: Regenerate.
 925         * frv-desc.h: Regenerate.
 926         * frv-opc.h: Regenerate.
 927         * ip2k-desc.h: Regenerate.
 928         * ip2k-opc.h: Regenerate.
 929         * iq2000-desc.h: Regenerate.
 930         * iq2000-opc.h: Regenerate.
 931         * lm32-desc.h: Regenerate.
 932         * lm32-opc.h: Regenerate.
 933         * m32c-desc.h: Regenerate.
 934         * m32c-opc.h: Regenerate.
 935         * m32r-desc.h: Regenerate.
 936         * m32r-opc.h: Regenerate.
 937         * mep-desc.h: Regenerate.
 938         * mep-opc.h: Regenerate.
 939         * mt-desc.h: Regenerate.
 940         * mt-opc.h: Regenerate.
 941         * or1k-desc.h: Regenerate.
 942         * or1k-opc.h: Regenerate.
 943         * xc16x-desc.h: Regenerate.
 944         * xc16x-opc.h: Regenerate.
 945         * xstormy16-desc.h: Regenerate.
 946         * xstormy16-opc.h: Regenerate.
 947
 948 2017-01-02  Alan Modra  <amodra@gmail.com>
 949
 950         Update year range in copyright notice of all files.
 951
 952 For older changes see ChangeLog-2016
 953 \f
 954 Copyright (C) 2017 Free Software Foundation, Inc.
 955
 956 Copying and distribution of this file, with or without modification,
 957 are permitted in any medium without royalty provided the copyright
 958 notice and this notice are preserved.
 959
 960 Local Variables:
 961 mode: change-log
 962 left-margin: 8
 963 fill-column: 74
 964 version-control: never
 965 End: