opcodes/ChangeLog

   1 2017-10-24  Andrew Waterman  <andrew@sifive.com>
   2
   3         * riscv-opc.c (match_c_addi16sp) : New function.
   4         (match_c_addi4spn): New function.
   5         (match_c_lui): Don't allow 0-immediate encodings.
   6         (riscv_opcodes) <addi>: Use the above functions.
   7         <add>: Likewise.
   8         <c.addi4spn>: Likewise.
   9         <c.addi16sp>: Likewise.
  10
  11 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  12
  13         * i386-init.h: Regenerate
  14         * i386-tbl.h: Likewise
  15
  16 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  17
  18         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
  19         (enum): Add EVEX_W_0F3854_P_2.
  20         * i386-dis-evex.h (evex_table): Updated.
  21         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
  22         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  23         (cpu_flags): Add CpuAVX512_BITALG.
  24         * i386-opc.h (enum): Add CpuAVX512_BITALG.
  25         (i386_cpu_flags): Add cpuavx512_bitalg..
  26         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
  27         * i386-init.h: Regenerate.
  28         * i386-tbl.h: Likewise.
  29
  30 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  31
  32         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
  33         * i386-dis-evex.h (evex_table): Updated.
  34         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
  35         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  36         (cpu_flags): Add CpuAVX512_VNNI.
  37         * i386-opc.h (enum): Add CpuAVX512_VNNI.
  38         (i386_cpu_flags): Add cpuavx512_vnni.
  39         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
  40         * i386-init.h: Regenerate.
  41         * i386-tbl.h: Likewise.
  42
  43 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  44
  45         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
  46         (enum): Remove VEX_LEN_0F3A44_P_2.
  47         (vex_len_table): Ditto.
  48         (enum): Remove VEX_W_0F3A44_P_2.
  49         (vew_w_table): Ditto.
  50         (prefix_table): Adjust instructions (see prefixes above).
  51         * i386-dis-evex.h (evex_table):
  52         Add new instructions (see prefixes above).
  53         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
  54         (bitfield_cpu_flags): Ditto.
  55         * i386-opc.h (enum): Ditto.
  56         (i386_cpu_flags): Ditto.
  57         (CpuUnused): Comment out to avoid zero-width field problem.
  58         * i386-opc.tbl (vpclmulqdq): New instruction.
  59         * i386-init.h: Regenerate.
  60         * i386-tbl.h: Ditto.
  61
  62 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  63
  64         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
  65         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
  66         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
  67         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
  68         (vex_len_table): Ditto.
  69         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
  70         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
  71         (vew_w_table): Ditto.
  72         (prefix_table): Adjust instructions (see prefixes above).
  73         * i386-dis-evex.h (evex_table):
  74         Add new instructions (see prefixes above).
  75         * i386-gen.c (cpu_flag_init): Add VAES.
  76         (bitfield_cpu_flags): Ditto.
  77         * i386-opc.h (enum): Ditto.
  78         (i386_cpu_flags): Ditto.
  79         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
  80         * i386-init.h: Regenerate.
  81         * i386-tbl.h: Ditto.
  82
  83 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  84
  85         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
  86         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
  87         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
  88         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
  89         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
  90         (prefix_table): Updated (see prefixes above).
  91         (three_byte_table): Likewise.
  92         (vex_w_table): Likewise.
  93         * i386-dis-evex.h: Likewise.
  94         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
  95         (cpu_flags): Add CpuGFNI.
  96         * i386-opc.h (enum): Add CpuGFNI.
  97         (i386_cpu_flags): Add cpugfni.
  98         * i386-opc.tbl: Add Intel GFNI instructions.
  99         * i386-init.h: Regenerate.
 100         * i386-tbl.h: Likewise.
 101
 102 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 103
 104         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 105         Define EXbScalar and EXwScalar for OP_EX.
 106         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 107         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 108         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 109         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 110         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 111         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 112         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 113         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 114         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 115         (OP_E_memory): Likewise.
 116         * i386-dis-evex.h: Updated.
 117         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 118         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 119         (cpu_flags): Add CpuAVX512_VBMI2.
 120         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 121         (i386_cpu_flags): Add cpuavx512_vbmi2.
 122         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 123         * i386-init.h: Regenerate.
 124         * i386-tbl.h: Likewise.
 125
 126 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 127
 128         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 129
 130 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 131
 132         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 133         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 134         K15. Add jmpix pattern.
 135
 136 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 137
 138         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 139
 140 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 141
 142         * s390-opc.c (INSTR_SI_RD): New macro.
 143         (INSTR_S_RD): Adjust example instruction.
 144         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 145         SI_RD.
 146
 147 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 148
 149         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 150         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 151         VLE multimple load/store instructions. Old e_ldm* variants are
 152         kept as aliases.
 153         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 154
 155 2017-09-27  Nick Clifton  <nickc@redhat.com>
 156
 157         PR 22179
 158         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 159         names for the fmv.x.s and fmv.s.x instructions respectively.
 160
 161 2017-09-26  do  <do@nerilex.org>
 162
 163         PR 22123
 164         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 165         be used on CPUs that have emacs support.
 166
 167 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 168
 169         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 170
 171 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 172
 173         * nds32-asm.c: Rename __BIT() to N32_BIT().
 174         * nds32-asm.h: Likewise.
 175         * nds32-dis.c: Likewise.
 176
 177 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 178
 179         * i386-dis.c (last_active_prefix): Removed.
 180         (ckprefix): Don't set last_active_prefix.
 181         (NOTRACK_Fixup): Don't check last_active_prefix.
 182
 183 2017-08-31  Nick Clifton  <nickc@redhat.com>
 184
 185         * po/fr.po: Updated French translation.
 186
 187 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 188
 189         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 190         fields.
 191
 192 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 193             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 194
 195         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 196         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 197         New entries efs2 and spe2.
 198         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 199         (SPE2_OPCD_SEGS): New macro.
 200         (spe2_opcd_indices): New.
 201         (disassemble_init_powerpc): Handle SPE2 opcodes.
 202         (lookup_spe2): New function.
 203         (print_insn_powerpc): call lookup_spe2.
 204         * ppc-opc.c (insert_evuimm1_ex0): New function.
 205         (extract_evuimm1_ex0): Likewise.
 206         (insert_evuimm_lt8): Likewise.
 207         (extract_evuimm_lt8): Likewise.
 208         (insert_off_spe2): Likewise.
 209         (extract_off_spe2): Likewise.
 210         (insert_Ddd): Likewise.
 211         (extract_Ddd): Likewise.
 212         (DD): New operand.
 213         (EVUIMM_LT8): Likewise.
 214         (EVUIMM_LT16): Adjust.
 215         (MMMM): New operand.
 216         (EVUIMM_1): Likewise.
 217         (EVUIMM_1_EX0): Likewise.
 218         (EVUIMM_2): Adjust.
 219         (NNN): New operand.
 220         (VX_OFF_SPE2): Likewise.
 221         (BBB): Likewise.
 222         (DDD): Likewise.
 223         (VX_MASK_DDD): New mask.
 224         (HH): New operand.
 225         (VX_RA_CONST): New macro.
 226         (VX_RA_CONST_MASK): Likewise.
 227         (VX_RB_CONST): Likewise.
 228         (VX_RB_CONST_MASK): Likewise.
 229         (VX_OFF_SPE2_MASK): Likewise.
 230         (VX_SPE_CRFD): Likewise.
 231         (VX_SPE_CRFD_MASK VX): Likewise.
 232         (VX_SPE2_CLR): Likewise.
 233         (VX_SPE2_CLR_MASK): Likewise.
 234         (VX_SPE2_SPLATB): Likewise.
 235         (VX_SPE2_SPLATB_MASK): Likewise.
 236         (VX_SPE2_OCTET): Likewise.
 237         (VX_SPE2_OCTET_MASK): Likewise.
 238         (VX_SPE2_DDHH): Likewise.
 239         (VX_SPE2_DDHH_MASK): Likewise.
 240         (VX_SPE2_HH): Likewise.
 241         (VX_SPE2_HH_MASK): Likewise.
 242         (VX_SPE2_EVMAR): Likewise.
 243         (VX_SPE2_EVMAR_MASK): Likewise.
 244         (PPCSPE2): Likewise.
 245         (PPCEFS2): Likewise.
 246         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 247         (powerpc_macros): Map old SPE instructions have new names
 248         with the same opcodes. Add SPE2 instructions which just are
 249         mapped to SPE2.
 250         (spe2_opcodes): Add SPE2 opcodes.
 251
 252 2017-08-23  Alan Modra  <amodra@gmail.com>
 253
 254         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 255         extract functions earlier, deleting forward declarations.
 256         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 257         RA_MASK.
 258
 259 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 260
 261         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 262
 263 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 264             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 265
 266         * ppc-opc.c (insert_evuimm2_ex0): New function.
 267         (extract_evuimm2_ex0): Likewise.
 268         (insert_evuimm4_ex0): Likewise.
 269         (extract_evuimm4_ex0): Likewise.
 270         (insert_evuimm8_ex0): Likewise.
 271         (extract_evuimm8_ex0): Likewise.
 272         (insert_evuimm_lt16): Likewise.
 273         (extract_evuimm_lt16): Likewise.
 274         (insert_rD_rS_even): Likewise.
 275         (extract_rD_rS_even): Likewise.
 276         (insert_off_lsp): Likewise.
 277         (extract_off_lsp): Likewise.
 278         (RD_EVEN): New operand.
 279         (RS_EVEN): Likewise.
 280         (RSQ): Adjust.
 281         (EVUIMM_LT16): New operand.
 282         (HTM_SI): Adjust.
 283         (EVUIMM_2_EX0): New operand.
 284         (EVUIMM_4): Adjust.
 285         (EVUIMM_4_EX0): New operand.
 286         (EVUIMM_8): Adjust.
 287         (EVUIMM_8_EX0): New operand.
 288         (WS): Adjust.
 289         (VX_OFF): New operand.
 290         (VX_LSP): New macro.
 291         (VX_LSP_MASK): Likewise.
 292         (VX_LSP_OFF_MASK): Likewise.
 293         (PPC_OPCODE_LSP): Likewise.
 294         (vle_opcodes): Add LSP opcodes.
 295         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 296
 297 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 298
 299         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 300         register operands in CRC instructions.
 301         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 302         comments.
 303
 304 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 305
 306         * disassemble.c (disassembler): Mark big and mach with
 307         ATTRIBUTE_UNUSED.
 308
 309 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 310
 311         * disassemble.c (disassembler): Remove arch/mach/endian
 312         assertions.
 313
 314 2017-07-25  Nick Clifton  <nickc@redhat.com>
 315
 316         PR 21739
 317         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 318         message.
 319         (insert_r0): Likewise.
 320         (insert_r1): Likewise.
 321         (insert_r2): Likewise.
 322         (insert_r3): Likewise.
 323         (insert_sp): Likewise.
 324         (insert_gp): Likewise.
 325         (insert_pcl): Likewise.
 326         (insert_blink): Likewise.
 327         (insert_ilink1): Likewise.
 328         (insert_ilink2): Likewise.
 329         (insert_ras): Likewise.
 330         (insert_rbs): Likewise.
 331         (insert_rcs): Likewise.
 332         (insert_simm3s): Likewise.
 333         (insert_rrange): Likewise.
 334         (insert_r13el): Likewise.
 335         (insert_fpel): Likewise.
 336         (insert_blinkel): Likewise.
 337         (insert_pclel): Likewise.
 338         (insert_nps_bitop_size_2b): Likewise.
 339         (insert_nps_imm_offset): Likewise.
 340         (insert_nps_imm_entry): Likewise.
 341         (insert_nps_size_16bit): Likewise.
 342         (insert_nps_##NAME##_pos): Likewise.
 343         (insert_nps_##NAME): Likewise.
 344         (insert_nps_bitop_ins_ext): Likewise.
 345         (insert_nps_##NAME): Likewise.
 346         (insert_nps_min_hofs): Likewise.
 347         (insert_nps_##NAME): Likewise.
 348         (insert_nps_rbdouble_64): Likewise.
 349         (insert_nps_misc_imm_offset): Likewise.
 350         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 351         option description.
 352
 353 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 354             Jiong Wang  <jiong.wang@arm.com>
 355
 356         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 357         correct the print.
 358         * aarch64-dis-2.c: Regenerated.
 359
 360 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 361
 362         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 363         table.
 364
 365 2017-07-20  Nick Clifton  <nickc@redhat.com>
 366
 367         * po/de.po: Updated German translation.
 368
 369 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 370
 371         * arc-regs.h (sec_stat): New aux register.
 372         (aux_kernel_sp): Likewise.
 373         (aux_sec_u_sp): Likewise.
 374         (aux_sec_k_sp): Likewise.
 375         (sec_vecbase_build): Likewise.
 376         (nsc_table_top): Likewise.
 377         (nsc_table_base): Likewise.
 378         (ersec_stat): Likewise.
 379         (aux_sec_except): Likewise.
 380
 381 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 382
 383         * arc-opc.c (extract_uimm12_20): New function.
 384         (UIMM12_20): New operand.
 385         (SIMM3_5_S): Adjust.
 386         * arc-tbl.h (sjli): Add new instruction.
 387
 388 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 389             John Eric Martin  <John.Martin@emmicro-us.com>
 390
 391         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 392         (UIMM3_23): Adjust accordingly.
 393         * arc-regs.h: Add/correct jli_base register.
 394         * arc-tbl.h (jli_s): Likewise.
 395
 396 2017-07-18  Nick Clifton  <nickc@redhat.com>
 397
 398         PR 21775
 399         * aarch64-opc.c: Fix spelling typos.
 400         * i386-dis.c: Likewise.
 401
 402 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 403
 404         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 405         max_addr_offset and octets variables to size_t.
 406
 407 2017-07-12  Alan Modra  <amodra@gmail.com>
 408
 409         * po/da.po: Update from translationproject.org/latest/opcodes/.
 410         * po/de.po: Likewise.
 411         * po/es.po: Likewise.
 412         * po/fi.po: Likewise.
 413         * po/fr.po: Likewise.
 414         * po/id.po: Likewise.
 415         * po/it.po: Likewise.
 416         * po/nl.po: Likewise.
 417         * po/pt_BR.po: Likewise.
 418         * po/ro.po: Likewise.
 419         * po/sv.po: Likewise.
 420         * po/tr.po: Likewise.
 421         * po/uk.po: Likewise.
 422         * po/vi.po: Likewise.
 423         * po/zh_CN.po: Likewise.
 424
 425 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 426             Alan Modra  <amodra@gmail.com>
 427
 428         * cgen.sh: Mark generated files read-only.
 429         * epiphany-asm.c: Regenerate.
 430         * epiphany-desc.c: Regenerate.
 431         * epiphany-desc.h: Regenerate.
 432         * epiphany-dis.c: Regenerate.
 433         * epiphany-ibld.c: Regenerate.
 434         * epiphany-opc.c: Regenerate.
 435         * epiphany-opc.h: Regenerate.
 436         * fr30-asm.c: Regenerate.
 437         * fr30-desc.c: Regenerate.
 438         * fr30-desc.h: Regenerate.
 439         * fr30-dis.c: Regenerate.
 440         * fr30-ibld.c: Regenerate.
 441         * fr30-opc.c: Regenerate.
 442         * fr30-opc.h: Regenerate.
 443         * frv-asm.c: Regenerate.
 444         * frv-desc.c: Regenerate.
 445         * frv-desc.h: Regenerate.
 446         * frv-dis.c: Regenerate.
 447         * frv-ibld.c: Regenerate.
 448         * frv-opc.c: Regenerate.
 449         * frv-opc.h: Regenerate.
 450         * ip2k-asm.c: Regenerate.
 451         * ip2k-desc.c: Regenerate.
 452         * ip2k-desc.h: Regenerate.
 453         * ip2k-dis.c: Regenerate.
 454         * ip2k-ibld.c: Regenerate.
 455         * ip2k-opc.c: Regenerate.
 456         * ip2k-opc.h: Regenerate.
 457         * iq2000-asm.c: Regenerate.
 458         * iq2000-desc.c: Regenerate.
 459         * iq2000-desc.h: Regenerate.
 460         * iq2000-dis.c: Regenerate.
 461         * iq2000-ibld.c: Regenerate.
 462         * iq2000-opc.c: Regenerate.
 463         * iq2000-opc.h: Regenerate.
 464         * lm32-asm.c: Regenerate.
 465         * lm32-desc.c: Regenerate.
 466         * lm32-desc.h: Regenerate.
 467         * lm32-dis.c: Regenerate.
 468         * lm32-ibld.c: Regenerate.
 469         * lm32-opc.c: Regenerate.
 470         * lm32-opc.h: Regenerate.
 471         * lm32-opinst.c: Regenerate.
 472         * m32c-asm.c: Regenerate.
 473         * m32c-desc.c: Regenerate.
 474         * m32c-desc.h: Regenerate.
 475         * m32c-dis.c: Regenerate.
 476         * m32c-ibld.c: Regenerate.
 477         * m32c-opc.c: Regenerate.
 478         * m32c-opc.h: Regenerate.
 479         * m32r-asm.c: Regenerate.
 480         * m32r-desc.c: Regenerate.
 481         * m32r-desc.h: Regenerate.
 482         * m32r-dis.c: Regenerate.
 483         * m32r-ibld.c: Regenerate.
 484         * m32r-opc.c: Regenerate.
 485         * m32r-opc.h: Regenerate.
 486         * m32r-opinst.c: Regenerate.
 487         * mep-asm.c: Regenerate.
 488         * mep-desc.c: Regenerate.
 489         * mep-desc.h: Regenerate.
 490         * mep-dis.c: Regenerate.
 491         * mep-ibld.c: Regenerate.
 492         * mep-opc.c: Regenerate.
 493         * mep-opc.h: Regenerate.
 494         * mt-asm.c: Regenerate.
 495         * mt-desc.c: Regenerate.
 496         * mt-desc.h: Regenerate.
 497         * mt-dis.c: Regenerate.
 498         * mt-ibld.c: Regenerate.
 499         * mt-opc.c: Regenerate.
 500         * mt-opc.h: Regenerate.
 501         * or1k-asm.c: Regenerate.
 502         * or1k-desc.c: Regenerate.
 503         * or1k-desc.h: Regenerate.
 504         * or1k-dis.c: Regenerate.
 505         * or1k-ibld.c: Regenerate.
 506         * or1k-opc.c: Regenerate.
 507         * or1k-opc.h: Regenerate.
 508         * or1k-opinst.c: Regenerate.
 509         * xc16x-asm.c: Regenerate.
 510         * xc16x-desc.c: Regenerate.
 511         * xc16x-desc.h: Regenerate.
 512         * xc16x-dis.c: Regenerate.
 513         * xc16x-ibld.c: Regenerate.
 514         * xc16x-opc.c: Regenerate.
 515         * xc16x-opc.h: Regenerate.
 516         * xstormy16-asm.c: Regenerate.
 517         * xstormy16-desc.c: Regenerate.
 518         * xstormy16-desc.h: Regenerate.
 519         * xstormy16-dis.c: Regenerate.
 520         * xstormy16-ibld.c: Regenerate.
 521         * xstormy16-opc.c: Regenerate.
 522         * xstormy16-opc.h: Regenerate.
 523
 524 2017-07-07  Alan Modra  <amodra@gmail.com>
 525
 526         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 527         * m32c-dis.c: Regenerate.
 528         * mep-dis.c: Regenerate.
 529
 530 2017-07-05  Borislav Petkov  <bp@suse.de>
 531
 532         * i386-dis.c: Enable ModRM.reg /6 aliases.
 533
 534 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 535
 536         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 537         with vmrs and vmsr.
 538
 539 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 540
 541         * configure: Regenerate.
 542
 543 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 544
 545         * po/opcodes.pot: Regenerate.
 546
 547 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 548
 549         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 550         entries to the MSA ASE instruction block.
 551
 552 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 553             Maciej W. Rozycki  <macro@imgtec.com>
 554
 555         * micromips-opc.c (XPA, XPAVZ): New macros.
 556         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 557         "mthgc0".
 558
 559 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 560             Maciej W. Rozycki  <macro@imgtec.com>
 561
 562         * micromips-opc.c (I36): New macro.
 563         (micromips_opcodes): Add "eretnc".
 564
 565 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 566             Andrew Bennett  <andrew.bennett@imgtec.com>
 567
 568         * mips-dis.c (mips_calculate_combination_ases): Handle the
 569         ASE_XPA_VIRT flag.
 570         (parse_mips_ase_option): New function.
 571         (parse_mips_dis_option): Factor out ASE option handling to the
 572         new function.  Call `mips_calculate_combination_ases'.
 573         * mips-opc.c (XPAVZ): New macro.
 574         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 575         "mfhgc0", "mthc0" and "mthgc0".
 576
 577 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 578
 579         * mips-dis.c (mips_calculate_combination_ases): New function.
 580         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 581         calculation to the new function.
 582         (set_default_mips_dis_options): Call the new function.
 583
 584 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 585
 586         * arc-dis.c (parse_disassembler_options): Use
 587         FOR_EACH_DISASSEMBLER_OPTION.
 588
 589 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 590
 591         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 592         disassembler option strings.
 593         (parse_cpu_option): Likewise.
 594
 595 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 596
 597         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 598         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 599         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 600         (aarch64_feature_dotprod, DOT_INSN): New.
 601         (udot, sdot): New.
 602         * aarch64-dis-2.c: Regenerated.
 603
 604 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 605
 606         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 607
 608 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 609             Matthew Fortune  <matthew.fortune@imgtec.com>
 610             Andrew Bennett  <andrew.bennett@imgtec.com>
 611
 612         * mips-formats.h (INT_BIAS): New macro.
 613         (INT_ADJ): Redefine in INT_BIAS terms.
 614         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 615         (mips_print_save_restore): New function.
 616         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 617         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 618         call.
 619         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 620         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 621         OP_SAVE_RESTORE_LIST handling, factored out from here.
 622         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 623         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 624         (mips_builtin_opcodes): Add "restore" and "save" entries.
 625         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 626         (IAMR2): New macro.
 627         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 628
 629 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 630
 631         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 632         alias; do not mark SLTI instruction as an alias.
 633
 634 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 635
 636         * i386-dis.c (RM_0FAE_REG_5): Removed.
 637         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 638         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 639         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 640         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 641         PREFIX_MOD_3_0F01_REG_5_RM_0.
 642         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 643         PREFIX_MOD_3_0FAE_REG_5.
 644         (mod_table): Update MOD_0FAE_REG_5.
 645         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 646         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 647         * i386-tbl.h: Regenerated.
 648
 649 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 650
 651         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 652         * i386-opc.tbl: Likewise.
 653         * i386-tbl.h: Regenerated.
 654
 655 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 656
 657         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 658         and "jmp{&|}".
 659         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 660         prefix.
 661
 662 2017-06-19  Nick Clifton  <nickc@redhat.com>
 663
 664         PR binutils/21614
 665         * score-dis.c (score_opcodes): Add sentinel.
 666
 667 2017-06-16  Alan Modra  <amodra@gmail.com>
 668
 669         * rx-decode.c: Regenerate.
 670
 671 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 672
 673         PR binutils/21594
 674         * i386-dis.c (OP_E_register): Check valid bnd register.
 675         (OP_G): Likewise.
 676
 677 2017-06-15  Nick Clifton  <nickc@redhat.com>
 678
 679         PR binutils/21595
 680         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 681         range value.
 682
 683 2017-06-15  Nick Clifton  <nickc@redhat.com>
 684
 685         PR binutils/21588
 686         * rl78-decode.opc (OP_BUF_LEN): Define.
 687         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 688         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 689         array.
 690         * rl78-decode.c: Regenerate.
 691
 692 2017-06-15  Nick Clifton  <nickc@redhat.com>
 693
 694         PR binutils/21586
 695         * bfin-dis.c (gregs): Clip index to prevent overflow.
 696         (regs): Likewise.
 697         (regs_lo): Likewise.
 698         (regs_hi): Likewise.
 699
 700 2017-06-14  Nick Clifton  <nickc@redhat.com>
 701
 702         PR binutils/21576
 703         * score7-dis.c (score_opcodes): Add sentinel.
 704
 705 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 706
 707         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 708         * arm-dis.c: Likewise.
 709         * ia64-dis.c: Likewise.
 710         * mips-dis.c: Likewise.
 711         * spu-dis.c: Likewise.
 712         * disassemble.h (print_insn_aarch64): New declaration, moved from
 713         include/dis-asm.h.
 714         (print_insn_big_arm, print_insn_big_mips): Likewise.
 715         (print_insn_i386, print_insn_ia64): Likewise.
 716         (print_insn_little_arm, print_insn_little_mips): Likewise.
 717
 718 2017-06-14  Nick Clifton  <nickc@redhat.com>
 719
 720         PR binutils/21587
 721         * rx-decode.opc: Include libiberty.h
 722         (GET_SCALE): New macro - validates access to SCALE array.
 723         (GET_PSCALE): New macro - validates access to PSCALE array.
 724         (DIs, SIs, S2Is, rx_disp): Use new macros.
 725         * rx-decode.c: Regenerate.
 726
 727 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 728
 729         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 730
 731 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 732
 733         * arc-dis.c (enforced_isa_mask): Declare.
 734         (cpu_types): Likewise.
 735         (parse_cpu_option): New function.
 736         (parse_disassembler_options): Use it.
 737         (print_insn_arc): Use enforced_isa_mask.
 738         (print_arc_disassembler_options): Document new options.
 739
 740 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 741
 742         * alpha-dis.c: Include disassemble.h, don't include
 743         dis-asm.h.
 744         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 745         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 746         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 747         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 748         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 749         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 750         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 751         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 752         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 753         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 754         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 755         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 756         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 757         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 758         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 759         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 760         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 761         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 762         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 763         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 764         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 765         * z80-dis.c, z8k-dis.c: Likewise.
 766         * disassemble.h: New file.
 767
 768 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 769
 770         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 771         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 772
 773 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 774
 775         * disassemble.c (disassembler): Add arguments a, big and mach.
 776         Use them.
 777
 778 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 779
 780         * i386-dis.c (NOTRACK_Fixup): New.
 781         (NOTRACK): Likewise.
 782         (NOTRACK_PREFIX): Likewise.
 783         (last_active_prefix): Likewise.
 784         (reg_table): Use NOTRACK on indirect call and jmp.
 785         (ckprefix): Set last_active_prefix.
 786         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 787         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 788         * i386-opc.h (NoTrackPrefixOk): New.
 789         (i386_opcode_modifier): Add notrackprefixok.
 790         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 791         Add notrack.
 792         * i386-tbl.h: Regenerated.
 793
 794 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 795
 796         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 797         (X_IMM2): Define.
 798         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 799         bfd_mach_sparc_v9m8.
 800         (print_insn_sparc): Handle new operand types.
 801         * sparc-opc.c (MASK_M8): Define.
 802         (v6): Add MASK_M8.
 803         (v6notlet): Likewise.
 804         (v7): Likewise.
 805         (v8): Likewise.
 806         (v9): Likewise.
 807         (v9a): Likewise.
 808         (v9b): Likewise.
 809         (v9c): Likewise.
 810         (v9d): Likewise.
 811         (v9e): Likewise.
 812         (v9v): Likewise.
 813         (v9m): Likewise.
 814         (v9andleon): Likewise.
 815         (m8): Define.
 816         (HWS_VM8): Define.
 817         (HWS2_VM8): Likewise.
 818         (sparc_opcode_archs): Add entry for "m8".
 819         (sparc_opcodes): Add OSA2017 and M8 instructions
 820         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 821         fpx{ll,ra,rl}64x,
 822         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 823         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 824         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 825         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 826         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 827         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 828         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 829         ASI_CORE_SELECT_COMMIT_NHT.
 830
 831 2017-05-18  Alan Modra  <amodra@gmail.com>
 832
 833         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 834         * aarch64-dis.c: Likewise.
 835         * aarch64-gen.c: Likewise.
 836         * aarch64-opc.c: Likewise.
 837
 838 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 839             Matthew Fortune  <matthew.fortune@imgtec.com>
 840
 841         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 842         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 843         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 844         (print_insn_arg) <OP_REG28>: Add handler.
 845         (validate_insn_args) <OP_REG28>: Handle.
 846         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 847         32-bit encoding and 9-bit immediates.
 848         (print_insn_mips16): Handle MIPS16 instructions that require
 849         32-bit encoding and MFC0/MTC0 operand decoding.
 850         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 851         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 852         (RD_C0, WR_C0, E2, E2MT): New macros.
 853         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 854         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 855         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 856         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 857         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 858         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 859         instructions, "swl", "swr", "sync" and its "sync_acquire",
 860         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 861         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 862         regular/extended entries for original MIPS16 ISA revision
 863         instructions whose extended forms are subdecoded in the MIPS16e2
 864         ISA revision: "li", "sll" and "srl".
 865
 866 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 867
 868         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 869         reference in CP0 move operand decoding.
 870
 871 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 872
 873         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 874         type to hexadecimal.
 875         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 876
 877 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 878
 879         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 880         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 881         "sync_rmb" and "sync_wmb" as aliases.
 882         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 883         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 884
 885 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 886
 887         * arc-dis.c (parse_option): Update quarkse_em option..
 888         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 889         QUARKSE1.
 890         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 891
 892 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 893
 894         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 895
 896 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 897
 898         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 899         register.
 900
 901 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 902
 903         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 904         and branches and not synthetic data instructions.
 905
 906 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 907
 908         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 909
 910 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 911
 912         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 913         * arc-opc.c (insert_r13el): New function.
 914         (R13_EL): Define.
 915         * arc-tbl.h: Add new enter/leave variants.
 916
 917 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 918
 919         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 920
 921 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 922
 923         * mips-dis.c (print_mips_disassembler_options): Add
 924         `no-aliases'.
 925
 926 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 927
 928         * mips16-opc.c (AL): New macro.
 929         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 930         of "ld" and "lw" as aliases.
 931
 932 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 933
 934         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 935         arguments.
 936
 937 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 938             Alan Modra  <amodra@gmail.com>
 939
 940         * ppc-opc.c (ELEV): Define.
 941         (vle_opcodes): Add se_rfgi and e_sc.
 942         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 943         for E200Z4.
 944
 945 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 946
 947         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 948
 949 2017-04-21  Nick Clifton  <nickc@redhat.com>
 950
 951         PR binutils/21380
 952         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 953         LD3R and LD4R.
 954
 955 2017-04-13  Alan Modra  <amodra@gmail.com>
 956
 957         * epiphany-desc.c: Regenerate.
 958         * fr30-desc.c: Regenerate.
 959         * frv-desc.c: Regenerate.
 960         * ip2k-desc.c: Regenerate.
 961         * iq2000-desc.c: Regenerate.
 962         * lm32-desc.c: Regenerate.
 963         * m32c-desc.c: Regenerate.
 964         * m32r-desc.c: Regenerate.
 965         * mep-desc.c: Regenerate.
 966         * mt-desc.c: Regenerate.
 967         * or1k-desc.c: Regenerate.
 968         * xc16x-desc.c: Regenerate.
 969         * xstormy16-desc.c: Regenerate.
 970
 971 2017-04-11  Alan Modra  <amodra@gmail.com>
 972
 973         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 974         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 975         PPC_OPCODE_TMR for e6500.
 976         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 977         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 978         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 979         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 980         (PPCHTM): Define as PPC_OPCODE_POWER8.
 981         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 982
 983 2017-04-10  Alan Modra  <amodra@gmail.com>
 984
 985         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 986         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 987         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 988         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 989
 990 2017-04-09  Pip Cet  <pipcet@gmail.com>
 991
 992         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 993         appropriate floating-point precision directly.
 994
 995 2017-04-07  Alan Modra  <amodra@gmail.com>
 996
 997         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 998         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 999         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1000         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1001         vector instructions with E6500 not PPCVEC2.
1002
1003 2017-04-06  Pip Cet  <pipcet@gmail.com>
1004
1005         * Makefile.am: Add wasm32-dis.c.
1006         * configure.ac: Add wasm32-dis.c to wasm32 target.
1007         * disassemble.c: Add wasm32 disassembler code.
1008         * wasm32-dis.c: New file.
1009         * Makefile.in: Regenerate.
1010         * configure: Regenerate.
1011         * po/POTFILES.in: Regenerate.
1012         * po/opcodes.pot: Regenerate.
1013
1014 2017-04-05  Pedro Alves  <palves@redhat.com>
1015
1016         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1017         * arm-dis.c (parse_arm_disassembler_options): Constify.
1018         * ppc-dis.c (powerpc_init_dialect): Constify local.
1019         * vax-dis.c (parse_disassembler_options): Constify.
1020
1021 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1022
1023         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1024         RISCV_GP_SYMBOL.
1025
1026 2017-03-30  Pip Cet  <pipcet@gmail.com>
1027
1028         * configure.ac: Add (empty) bfd_wasm32_arch target.
1029         * configure: Regenerate
1030         * po/opcodes.pot: Regenerate.
1031
1032 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1033
1034         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1035         OSA2015.
1036         * opcodes/sparc-opc.c (asi_table): New ASIs.
1037
1038 2017-03-29  Alan Modra  <amodra@gmail.com>
1039
1040         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1041         "raw" option.
1042         (lookup_powerpc): Don't special case -1 dialect.  Handle
1043         PPC_OPCODE_RAW.
1044         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1045         lookup_powerpc call, pass it on second.
1046
1047 2017-03-27  Alan Modra  <amodra@gmail.com>
1048
1049         PR 21303
1050         * ppc-dis.c (struct ppc_mopt): Comment.
1051         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1052
1053 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1054
1055         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1056         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1057         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1058         (insert_nps_misc_imm_offset): New function.
1059         (extract_nps_misc imm_offset): New function.
1060         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1061         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1062
1063 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1064
1065         * s390-mkopc.c (main): Remove vx2 check.
1066         * s390-opc.txt: Remove vx2 instruction flags.
1067
1068 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1069
1070         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1071         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1072         (insert_nps_imm_offset): New function.
1073         (extract_nps_imm_offset): New function.
1074         (insert_nps_imm_entry): New function.
1075         (extract_nps_imm_entry): New function.
1076
1077 2017-03-17  Alan Modra  <amodra@gmail.com>
1078
1079         PR 21248
1080         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1081         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1082         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1083
1084 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1085
1086         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1087         <c.andi>: Likewise.
1088         <c.addiw> Likewise.
1089
1090 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1091
1092         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1093
1094 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1095
1096         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1097         <srl> Likewise.
1098         <srai> Likewise.
1099         <sra> Likewise.
1100
1101 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1102
1103         * i386-gen.c (opcode_modifiers): Replace S with Load.
1104         * i386-opc.h (S): Removed.
1105         (Load): New.
1106         (i386_opcode_modifier): Replace s with load.
1107         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1108         and {evex}.  Replace S with Load.
1109         * i386-tbl.h: Regenerated.
1110
1111 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1112
1113         * i386-opc.tbl: Use CpuCET on rdsspq.
1114         * i386-tbl.h: Regenerated.
1115
1116 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1117
1118         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1119         <vsx>: Do not use PPC_OPCODE_VSX3;
1120
1121 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1122
1123         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1124
1125 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1126
1127         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1128         (MOD_0F1E_PREFIX_1): Likewise.
1129         (MOD_0F38F5_PREFIX_2): Likewise.
1130         (MOD_0F38F6_PREFIX_0): Likewise.
1131         (RM_0F1E_MOD_3_REG_7): Likewise.
1132         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1133         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1134         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1135         (PREFIX_0F1E): Likewise.
1136         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1137         (PREFIX_0F38F5): Likewise.
1138         (dis386_twobyte): Use PREFIX_0F1E.
1139         (reg_table): Add REG_0F1E_MOD_3.
1140         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1141         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1142         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1143         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1144         (three_byte_table): Use PREFIX_0F38F5.
1145         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1146         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1147         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1148         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1149         PREFIX_MOD_3_0F01_REG_5_RM_2.
1150         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1151         (cpu_flags): Add CpuCET.
1152         * i386-opc.h (CpuCET): New enum.
1153         (CpuUnused): Commented out.
1154         (i386_cpu_flags): Add cpucet.
1155         * i386-opc.tbl: Add Intel CET instructions.
1156         * i386-init.h: Regenerated.
1157         * i386-tbl.h: Likewise.
1158
1159 2017-03-06  Alan Modra  <amodra@gmail.com>
1160
1161         PR 21124
1162         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1163         (extract_raq, extract_ras, extract_rbx): New functions.
1164         (powerpc_operands): Use opposite corresponding insert function.
1165         (Q_MASK): Define.
1166         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1167         register restriction.
1168
1169 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1170
1171         * disassemble.c Include "safe-ctype.h".
1172         (disassemble_init_for_target): Handle s390 init.
1173         (remove_whitespace_and_extra_commas): New function.
1174         (disassembler_options_cmp): Likewise.
1175         * arm-dis.c: Include "libiberty.h".
1176         (NUM_ELEM): Delete.
1177         (regnames): Use long disassembler style names.
1178         Add force-thumb and no-force-thumb options.
1179         (NUM_ARM_REGNAMES): Rename from this...
1180         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1181         (get_arm_regname_num_options): Delete.
1182         (set_arm_regname_option): Likewise.
1183         (get_arm_regnames): Likewise.
1184         (parse_disassembler_options): Likewise.
1185         (parse_arm_disassembler_option): Rename from this...
1186         (parse_arm_disassembler_options): ...to this.  Make static.
1187         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1188         (print_insn): Use parse_arm_disassembler_options.
1189         (disassembler_options_arm): New function.
1190         (print_arm_disassembler_options): Handle updated regnames.
1191         * ppc-dis.c: Include "libiberty.h".
1192         (ppc_opts): Add "32" and "64" entries.
1193         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1194         (powerpc_init_dialect): Add break to switch statement.
1195         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1196         (disassembler_options_powerpc): New function.
1197         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1198         Remove printing of "32" and "64".
1199         * s390-dis.c: Include "libiberty.h".
1200         (init_flag): Remove unneeded variable.
1201         (struct s390_options_t): New structure type.
1202         (options): New structure.
1203         (init_disasm): Rename from this...
1204         (disassemble_init_s390): ...to this.  Add initializations for
1205         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1206         (print_insn_s390): Delete call to init_disasm.
1207         (disassembler_options_s390): New function.
1208         (print_s390_disassembler_options): Print using information from
1209         struct 'options'.
1210         * po/opcodes.pot: Regenerate.
1211
1212 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1213
1214         * i386-dis.c (PCMPESTR_Fixup): New.
1215         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1216         (prefix_table): Use PCMPESTR_Fixup.
1217         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1218         PCMPESTR_Fixup.
1219         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1220         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1221         Split 64-bit and non-64-bit variants.
1222         * opcodes/i386-tbl.h: Re-generate.
1223
1224 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1225
1226         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1227         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1228         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1229         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1230         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1231         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1232         (OP_SVE_V_HSD): New macros.
1233         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1234         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1235         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1236         (aarch64_opcode_table): Add new SVE instructions.
1237         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1238         for rotation operands.  Add new SVE operands.
1239         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1240         (ins_sve_quad_index): Likewise.
1241         (ins_imm_rotate): Split into...
1242         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1243         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1244         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1245         functions.
1246         (aarch64_ins_sve_addr_ri_s4): New function.
1247         (aarch64_ins_sve_quad_index): Likewise.
1248         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1249         * aarch64-asm-2.c: Regenerate.
1250         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1251         (ext_sve_quad_index): Likewise.
1252         (ext_imm_rotate): Split into...
1253         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1254         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1255         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1256         functions.
1257         (aarch64_ext_sve_addr_ri_s4): New function.
1258         (aarch64_ext_sve_quad_index): Likewise.
1259         (aarch64_ext_sve_index): Allow quad indices.
1260         (do_misc_decoding): Likewise.
1261         * aarch64-dis-2.c: Regenerate.
1262         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1263         aarch64_field_kinds.
1264         (OPD_F_OD_MASK): Widen by one bit.
1265         (OPD_F_NO_ZR): Bump accordingly.
1266         (get_operand_field_width): New function.
1267         * aarch64-opc.c (fields): Add new SVE fields.
1268         (operand_general_constraint_met_p): Handle new SVE operands.
1269         (aarch64_print_operand): Likewise.
1270         * aarch64-opc-2.c: Regenerate.
1271
1272 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1273
1274         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1275         (aarch64_feature_compnum): ...this.
1276         (SIMD_V8_3): Replace with...
1277         (COMPNUM): ...this.
1278         (CNUM_INSN): New macro.
1279         (aarch64_opcode_table): Use it for the complex number instructions.
1280
1281 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1282
1283         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1284
1285 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1286
1287         Add support for associating SPARC ASIs with an architecture level.
1288         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1289         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1290         decoding of SPARC ASIs.
1291
1292 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1293
1294         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1295         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1296
1297 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1298
1299         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1300         1 (instead of to itself). Correct typo.
1301
1302 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1303
1304         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1305         pseudoinstructions.
1306
1307 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1308
1309         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1310         (aarch64_sys_reg_supported_p): Handle them.
1311
1312 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1313
1314         * arc-opc.c (UIMM6_20R): Define.
1315         (SIMM12_20): Use above.
1316         (SIMM12_20R): Define.
1317         (SIMM3_5_S): Use above.
1318         (UIMM7_A32_11R_S): Define.
1319         (UIMM7_9_S): Use above.
1320         (UIMM3_13R_S): Define.
1321         (SIMM11_A32_7_S): Use above.
1322         (SIMM9_8R): Define.
1323         (UIMM10_A32_8_S): Use above.
1324         (UIMM8_8R_S): Define.
1325         (W6): Use above.
1326         (arc_relax_opcodes): Use all above defines.
1327
1328 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1329
1330         * arc-regs.h: Distinguish some of the registers different on
1331         ARC700 and HS38 cpus.
1332
1333 2017-02-14  Alan Modra  <amodra@gmail.com>
1334
1335         PR 21118
1336         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1337         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1338
1339 2017-02-11  Stafford Horne  <shorne@gmail.com>
1340             Alan Modra  <amodra@gmail.com>
1341
1342         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1343         Use insn_bytes_value and insn_int_value directly instead.  Don't
1344         free allocated memory until function exit.
1345
1346 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1347
1348         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1349
1350 2017-02-03  Nick Clifton  <nickc@redhat.com>
1351
1352         PR 21096
1353         * aarch64-opc.c (print_register_list): Ensure that the register
1354         list index will fir into the tb buffer.
1355         (print_register_offset_address): Likewise.
1356         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1357
1358 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1359
1360         PR 21056
1361         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1362         instructions when the previous fetch packet ends with a 32-bit
1363         instruction.
1364
1365 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1366
1367         * pru-opc.c: Remove vague reference to a future GDB port.
1368
1369 2017-01-20  Nick Clifton  <nickc@redhat.com>
1370
1371         * po/ga.po: Updated Irish translation.
1372
1373 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1374
1375         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1376
1377 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1378
1379         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1380         if FETCH_DATA returns 0.
1381         (m68k_scan_mask): Likewise.
1382         (print_insn_m68k): Update code to handle -1 return value.
1383
1384 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1385
1386         * m68k-dis.c (enum print_insn_arg_error): New.
1387         (NEXTBYTE): Replace -3 with
1388         PRINT_INSN_ARG_MEMORY_ERROR.
1389         (NEXTULONG): Likewise.
1390         (NEXTSINGLE): Likewise.
1391         (NEXTDOUBLE): Likewise.
1392         (NEXTDOUBLE): Likewise.
1393         (NEXTPACKED): Likewise.
1394         (FETCH_ARG): Likewise.
1395         (FETCH_DATA): Update comments.
1396         (print_insn_arg): Update comments. Replace magic numbers with
1397         enum.
1398         (match_insn_m68k): Likewise.
1399
1400 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1401
1402         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1403         * i386-dis-evex.h (evex_table): Updated.
1404         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1405         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1406         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1407         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1408         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1409         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1410         * i386-init.h: Regenerate.
1411         * i386-tbl.h: Ditto.
1412
1413 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1414
1415         * msp430-dis.c (msp430_singleoperand): Return -1 if
1416         msp430dis_opcode_signed returns false.
1417         (msp430_doubleoperand): Likewise.
1418         (msp430_branchinstr): Return -1 if
1419         msp430dis_opcode_unsigned returns false.
1420         (msp430x_calla_instr): Likewise.
1421         (print_insn_msp430): Likewise.
1422
1423 2017-01-05  Nick Clifton  <nickc@redhat.com>
1424
1425         PR 20946
1426         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1427         could not be matched.
1428         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1429         NULL.
1430
1431 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1432
1433         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1434         (aarch64_opcode_table): Use RCPC_INSN.
1435
1436 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1437
1438         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1439         extension.
1440         * riscv-opcodes/all-opcodes: Likewise.
1441
1442 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1443
1444         * riscv-dis.c (print_insn_args): Add fall through comment.
1445
1446 2017-01-03  Nick Clifton  <nickc@redhat.com>
1447
1448         * po/sr.po: New Serbian translation.
1449         * configure.ac (ALL_LINGUAS): Add sr.
1450         * configure: Regenerate.
1451
1452 2017-01-02  Alan Modra  <amodra@gmail.com>
1453
1454         * epiphany-desc.h: Regenerate.
1455         * epiphany-opc.h: Regenerate.
1456         * fr30-desc.h: Regenerate.
1457         * fr30-opc.h: Regenerate.
1458         * frv-desc.h: Regenerate.
1459         * frv-opc.h: Regenerate.
1460         * ip2k-desc.h: Regenerate.
1461         * ip2k-opc.h: Regenerate.
1462         * iq2000-desc.h: Regenerate.
1463         * iq2000-opc.h: Regenerate.
1464         * lm32-desc.h: Regenerate.
1465         * lm32-opc.h: Regenerate.
1466         * m32c-desc.h: Regenerate.
1467         * m32c-opc.h: Regenerate.
1468         * m32r-desc.h: Regenerate.
1469         * m32r-opc.h: Regenerate.
1470         * mep-desc.h: Regenerate.
1471         * mep-opc.h: Regenerate.
1472         * mt-desc.h: Regenerate.
1473         * mt-opc.h: Regenerate.
1474         * or1k-desc.h: Regenerate.
1475         * or1k-opc.h: Regenerate.
1476         * xc16x-desc.h: Regenerate.
1477         * xc16x-opc.h: Regenerate.
1478         * xstormy16-desc.h: Regenerate.
1479         * xstormy16-opc.h: Regenerate.
1480
1481 2017-01-02  Alan Modra  <amodra@gmail.com>
1482
1483         Update year range in copyright notice of all files.
1484
1485 For older changes see ChangeLog-2016
1486 \f
1487 Copyright (C) 2017 Free Software Foundation, Inc.
1488
1489 Copying and distribution of this file, with or without modification,
1490 are permitted in any medium without royalty provided the copyright
1491 notice and this notice are preserved.
1492
1493 Local Variables:
1494 mode: change-log
1495 left-margin: 8
1496 fill-column: 74
1497 version-control: never
1498 End: