opcodes/ChangeLog

   1 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/24626
   4         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
   5         EVEX.vvvv when disassembling VEX and EVEX instructions.
   6         (OP_VEX): Set vex.register_specifier to 0 after readding
   7         vex.register_specifier.
   8         (OP_Vex_2src_1): Likewise.
   9         (OP_Vex_2src_2): Likewise.
  10         (OP_LWP_E): Likewise.
  11         (OP_EX_Vex): Don't check vex.register_specifier.
  12         (OP_XMM_Vex): Likewise.
  13
  14 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  15             Lili Cui  <lili.cui@intel.com>
  16
  17         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
  18         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
  19         instructions.
  20         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
  21         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
  22         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
  23         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
  24         (i386_cpu_flags): Add cpuavx512_vp2intersect.
  25         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
  26         * i386-init.h: Regenerated.
  27         * i386-tbl.h: Likewise.
  28
  29 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
  30             Lili Cui  <lili.cui@intel.com>
  31
  32         * doc/c-i386.texi: Document enqcmd.
  33         * testsuite/gas/i386/enqcmd-intel.d: New file.
  34         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
  35         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
  36         * testsuite/gas/i386/enqcmd.d: Likewise.
  37         * testsuite/gas/i386/enqcmd.s: Likewise.
  38         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
  39         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
  40         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
  41         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
  42         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
  43         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
  44         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
  45         and x86-64-enqcmd.
  46
  47 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
  48
  49         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
  50
  51 2019-06-03  Alan Modra  <amodra@gmail.com>
  52
  53         * ppc-dis.c (prefix_opcd_indices): Correct size.
  54
  55 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
  56
  57         PR gas/24625
  58         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
  59         Disp8ShiftVL.
  60         * i386-tbl.h: Regenerated.
  61
  62 2019-05-24  Alan Modra  <amodra@gmail.com>
  63
  64         * po/POTFILES.in: Regenerate.
  65
  66 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  67             Alan Modra  <amodra@gmail.com>
  68
  69         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
  70         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
  71         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
  72         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
  73         XTOP>): Define and add entries.
  74         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
  75         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
  76         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
  77         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
  78
  79 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  80             Alan Modra  <amodra@gmail.com>
  81
  82         * ppc-dis.c (ppc_opts): Add "future" entry.
  83         (PREFIX_OPCD_SEGS): Define.
  84         (prefix_opcd_indices): New array.
  85         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
  86         (lookup_prefix): New function.
  87         (print_insn_powerpc): Handle 64-bit prefix instructions.
  88         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
  89         (PMRR, POWERXX): Define.
  90         (prefix_opcodes): New instruction table.
  91         (prefix_num_opcodes): New constant.
  92
  93 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  94
  95         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
  96         * configure: Regenerated.
  97         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
  98         and cpu/bpf.opc.
  99         (HFILES): Add bpf-desc.h and bpf-opc.h.
 100         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 101         bpf-ibld.c and bpf-opc.c.
 102         (BPF_DEPS): Define.
 103         * Makefile.in: Regenerated.
 104         * disassemble.c (ARCH_bpf): Define.
 105         (disassembler): Add case for bfd_arch_bpf.
 106         (disassemble_init_for_target): Likewise.
 107         (enum epbf_isa_attr): Define.
 108         * disassemble.h: extern print_insn_bpf.
 109         * bpf-asm.c: Generated.
 110         * bpf-opc.h: Likewise.
 111         * bpf-opc.c: Likewise.
 112         * bpf-ibld.c: Likewise.
 113         * bpf-dis.c: Likewise.
 114         * bpf-desc.h: Likewise.
 115         * bpf-desc.c: Likewise.
 116
 117 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 118
 119         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 120         and VMSR with the new operands.
 121
 122 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 123
 124         * arm-dis.c (enum mve_instructions): New enum
 125         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 126         and cneg.
 127         (mve_opcodes): New instructions as above.
 128         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 129         csneg and csel.
 130         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 131
 132 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 133
 134         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 135         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 136         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 137         uqshl, urshrl and urshr.
 138         (is_mve_okay_in_it): Add new instructions to TRUE list.
 139         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 140         (print_insn_mve): Updated to accept new %j,
 141         %<bitfield>m and %<bitfield>n patterns.
 142
 143 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 144
 145         * mips-opc.c (mips_builtin_opcodes): Change source register
 146         constraint for DAUI.
 147
 148 2019-05-20  Nick Clifton  <nickc@redhat.com>
 149
 150         * po/fr.po: Updated French translation.
 151
 152 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 153             Michael Collison <michael.collison@arm.com>
 154
 155         * arm-dis.c (thumb32_opcodes): Add new instructions.
 156         (enum mve_instructions): Likewise.
 157         (enum mve_undefined): Add new reasons.
 158         (is_mve_encoding_conflict): Handle new instructions.
 159         (is_mve_undefined): Likewise.
 160         (is_mve_unpredictable): Likewise.
 161         (print_mve_undefined): Likewise.
 162         (print_mve_size): Likewise.
 163
 164 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 165             Michael Collison <michael.collison@arm.com>
 166
 167         * arm-dis.c (thumb32_opcodes): Add new instructions.
 168         (enum mve_instructions): Likewise.
 169         (is_mve_encoding_conflict): Handle new instructions.
 170         (is_mve_undefined): Likewise.
 171         (is_mve_unpredictable): Likewise.
 172         (print_mve_size): Likewise.
 173
 174 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 175             Michael Collison <michael.collison@arm.com>
 176
 177         * arm-dis.c (thumb32_opcodes): Add new instructions.
 178         (enum mve_instructions): Likewise.
 179         (is_mve_encoding_conflict): Likewise.
 180         (is_mve_unpredictable): Likewise.
 181         (print_mve_size): Likewise.
 182
 183 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 184             Michael Collison <michael.collison@arm.com>
 185
 186         * arm-dis.c (thumb32_opcodes): Add new instructions.
 187         (enum mve_instructions): Likewise.
 188         (is_mve_encoding_conflict): Handle new instructions.
 189         (is_mve_undefined): Likewise.
 190         (is_mve_unpredictable): Likewise.
 191         (print_mve_size): Likewise.
 192
 193 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 194             Michael Collison <michael.collison@arm.com>
 195
 196         * arm-dis.c (thumb32_opcodes): Add new instructions.
 197         (enum mve_instructions): Likewise.
 198         (is_mve_encoding_conflict): Handle new instructions.
 199         (is_mve_undefined): Likewise.
 200         (is_mve_unpredictable): Likewise.
 201         (print_mve_size): Likewise.
 202         (print_insn_mve): Likewise.
 203
 204 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 205             Michael Collison <michael.collison@arm.com>
 206
 207         * arm-dis.c (thumb32_opcodes): Add new instructions.
 208         (print_insn_thumb32): Handle new instructions.
 209
 210 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 211             Michael Collison <michael.collison@arm.com>
 212
 213         * arm-dis.c (enum mve_instructions): Add new instructions.
 214         (enum mve_undefined): Add new reasons.
 215         (is_mve_encoding_conflict): Handle new instructions.
 216         (is_mve_undefined): Likewise.
 217         (is_mve_unpredictable): Likewise.
 218         (print_mve_undefined): Likewise.
 219         (print_mve_size): Likewise.
 220         (print_mve_shift_n): Likewise.
 221         (print_insn_mve): Likewise.
 222
 223 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 224             Michael Collison <michael.collison@arm.com>
 225
 226         * arm-dis.c (enum mve_instructions): Add new instructions.
 227         (is_mve_encoding_conflict): Handle new instructions.
 228         (is_mve_unpredictable): Likewise.
 229         (print_mve_rotate): Likewise.
 230         (print_mve_size): Likewise.
 231         (print_insn_mve): Likewise.
 232
 233 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 234             Michael Collison <michael.collison@arm.com>
 235
 236         * arm-dis.c (enum mve_instructions): Add new instructions.
 237         (is_mve_encoding_conflict): Handle new instructions.
 238         (is_mve_unpredictable): Likewise.
 239         (print_mve_size): Likewise.
 240         (print_insn_mve): Likewise.
 241
 242 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 243             Michael Collison <michael.collison@arm.com>
 244
 245         * arm-dis.c (enum mve_instructions): Add new instructions.
 246         (enum mve_undefined): Add new reasons.
 247         (is_mve_encoding_conflict): Handle new instructions.
 248         (is_mve_undefined): Likewise.
 249         (is_mve_unpredictable): Likewise.
 250         (print_mve_undefined): Likewise.
 251         (print_mve_size): Likewise.
 252         (print_insn_mve): Likewise.
 253
 254 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 255             Michael Collison <michael.collison@arm.com>
 256
 257         * arm-dis.c (enum mve_instructions): Add new instructions.
 258         (is_mve_encoding_conflict): Handle new instructions.
 259         (is_mve_undefined): Likewise.
 260         (is_mve_unpredictable): Likewise.
 261         (print_mve_size): Likewise.
 262         (print_insn_mve): Likewise.
 263
 264 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 265             Michael Collison <michael.collison@arm.com>
 266
 267         * arm-dis.c (enum mve_instructions): Add new instructions.
 268         (enum mve_unpredictable): Add new reasons.
 269         (enum mve_undefined): Likewise.
 270         (is_mve_okay_in_it): Handle new isntructions.
 271         (is_mve_encoding_conflict): Likewise.
 272         (is_mve_undefined): Likewise.
 273         (is_mve_unpredictable): Likewise.
 274         (print_mve_vmov_index): Likewise.
 275         (print_simd_imm8): Likewise.
 276         (print_mve_undefined): Likewise.
 277         (print_mve_unpredictable): Likewise.
 278         (print_mve_size): Likewise.
 279         (print_insn_mve): Likewise.
 280
 281 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 282             Michael Collison <michael.collison@arm.com>
 283
 284         * arm-dis.c (enum mve_instructions): Add new instructions.
 285         (enum mve_unpredictable): Add new reasons.
 286         (enum mve_undefined): Likewise.
 287         (is_mve_encoding_conflict): Handle new instructions.
 288         (is_mve_undefined): Likewise.
 289         (is_mve_unpredictable): Likewise.
 290         (print_mve_undefined): Likewise.
 291         (print_mve_unpredictable): Likewise.
 292         (print_mve_rounding_mode): Likewise.
 293         (print_mve_vcvt_size): Likewise.
 294         (print_mve_size): Likewise.
 295         (print_insn_mve): Likewise.
 296
 297 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 298             Michael Collison <michael.collison@arm.com>
 299
 300         * arm-dis.c (enum mve_instructions): Add new instructions.
 301         (enum mve_unpredictable): Add new reasons.
 302         (enum mve_undefined): Likewise.
 303         (is_mve_undefined): Handle new instructions.
 304         (is_mve_unpredictable): Likewise.
 305         (print_mve_undefined): Likewise.
 306         (print_mve_unpredictable): Likewise.
 307         (print_mve_size): Likewise.
 308         (print_insn_mve): Likewise.
 309
 310 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 311             Michael Collison <michael.collison@arm.com>
 312
 313         * arm-dis.c (enum mve_instructions): Add new instructions.
 314         (enum mve_undefined): Add new reasons.
 315         (insns): Add new instructions.
 316         (is_mve_encoding_conflict):
 317         (print_mve_vld_str_addr): New print function.
 318         (is_mve_undefined): Handle new instructions.
 319         (is_mve_unpredictable): Likewise.
 320         (print_mve_undefined): Likewise.
 321         (print_mve_size): Likewise.
 322         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 323         (print_insn_mve):  Handle new operands.
 324
 325 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 326             Michael Collison <michael.collison@arm.com>
 327
 328         * arm-dis.c (enum mve_instructions): Add new instructions.
 329         (enum mve_unpredictable): Add new reasons.
 330         (is_mve_encoding_conflict): Handle new instructions.
 331         (is_mve_unpredictable): Likewise.
 332         (mve_opcodes): Add new instructions.
 333         (print_mve_unpredictable): Handle new reasons.
 334         (print_mve_register_blocks): New print function.
 335         (print_mve_size): Handle new instructions.
 336         (print_insn_mve): Likewise.
 337
 338 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 339             Michael Collison <michael.collison@arm.com>
 340
 341         * arm-dis.c (enum mve_instructions): Add new instructions.
 342         (enum mve_unpredictable): Add new reasons.
 343         (enum mve_undefined): Likewise.
 344         (is_mve_encoding_conflict): Handle new instructions.
 345         (is_mve_undefined): Likewise.
 346         (is_mve_unpredictable): Likewise.
 347         (coprocessor_opcodes): Move NEON VDUP from here...
 348         (neon_opcodes): ... to here.
 349         (mve_opcodes): Add new instructions.
 350         (print_mve_undefined):  Handle new reasons.
 351         (print_mve_unpredictable): Likewise.
 352         (print_mve_size): Handle new instructions.
 353         (print_insn_neon): Handle vdup.
 354         (print_insn_mve): Handle new operands.
 355
 356 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 357             Michael Collison <michael.collison@arm.com>
 358
 359         * arm-dis.c (enum mve_instructions): Add new instructions.
 360         (enum mve_unpredictable): Add new values.
 361         (mve_opcodes): Add new instructions.
 362         (vec_condnames): New array with vector conditions.
 363         (mve_predicatenames): New array with predicate suffixes.
 364         (mve_vec_sizename): New array with vector sizes.
 365         (enum vpt_pred_state): New enum with vector predication states.
 366         (struct vpt_block): New struct type for vpt blocks.
 367         (vpt_block_state): Global struct to keep track of state.
 368         (mve_extract_pred_mask): New helper function.
 369         (num_instructions_vpt_block): Likewise.
 370         (mark_outside_vpt_block): Likewise.
 371         (mark_inside_vpt_block): Likewise.
 372         (invert_next_predicate_state): Likewise.
 373         (update_next_predicate_state): Likewise.
 374         (update_vpt_block_state): Likewise.
 375         (is_vpt_instruction): Likewise.
 376         (is_mve_encoding_conflict): Add entries for new instructions.
 377         (is_mve_unpredictable): Likewise.
 378         (print_mve_unpredictable): Handle new cases.
 379         (print_instruction_predicate): Likewise.
 380         (print_mve_size): New function.
 381         (print_vec_condition): New function.
 382         (print_insn_mve): Handle vpt blocks and new print operands.
 383
 384 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 385
 386         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 387         8, 14 and 15 for Armv8.1-M Mainline.
 388
 389 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 390             Michael Collison <michael.collison@arm.com>
 391
 392         * arm-dis.c (enum mve_instructions): New enum.
 393         (enum mve_unpredictable): Likewise.
 394         (enum mve_undefined): Likewise.
 395         (struct mopcode32): New struct.
 396         (is_mve_okay_in_it): New function.
 397         (is_mve_architecture): Likewise.
 398         (arm_decode_field): Likewise.
 399         (arm_decode_field_multiple): Likewise.
 400         (is_mve_encoding_conflict): Likewise.
 401         (is_mve_undefined): Likewise.
 402         (is_mve_unpredictable): Likewise.
 403         (print_mve_undefined): Likewise.
 404         (print_mve_unpredictable): Likewise.
 405         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 406         (print_insn_mve): New function.
 407         (print_insn_thumb32): Handle MVE architecture.
 408         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 409
 410 2019-05-10  Nick Clifton  <nickc@redhat.com>
 411
 412         PR 24538
 413         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 414         end of the table prematurely.
 415
 416 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 417
 418         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 419         macros for R6.
 420
 421 2019-05-11  Alan Modra  <amodra@gmail.com>
 422
 423         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 424         when -Mraw is in effect.
 425
 426 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 427
 428         * aarch64-dis-2.c: Regenerate.
 429         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 430         (OP_SVE_BBB): New variant set.
 431         (OP_SVE_DDDD): New variant set.
 432         (OP_SVE_HHH): New variant set.
 433         (OP_SVE_HHHU): New variant set.
 434         (OP_SVE_SSS): New variant set.
 435         (OP_SVE_SSSU): New variant set.
 436         (OP_SVE_SHH): New variant set.
 437         (OP_SVE_SBBU): New variant set.
 438         (OP_SVE_DSS): New variant set.
 439         (OP_SVE_DHHU): New variant set.
 440         (OP_SVE_VMV_HSD_BHS): New variant set.
 441         (OP_SVE_VVU_HSD_BHS): New variant set.
 442         (OP_SVE_VVVU_SD_BH): New variant set.
 443         (OP_SVE_VVVU_BHSD): New variant set.
 444         (OP_SVE_VVV_QHD_DBS): New variant set.
 445         (OP_SVE_VVV_HSD_BHS): New variant set.
 446         (OP_SVE_VVV_HSD_BHS2): New variant set.
 447         (OP_SVE_VVV_BHS_HSD): New variant set.
 448         (OP_SVE_VV_BHS_HSD): New variant set.
 449         (OP_SVE_VVV_SD): New variant set.
 450         (OP_SVE_VVU_BHS_HSD): New variant set.
 451         (OP_SVE_VZVV_SD): New variant set.
 452         (OP_SVE_VZVV_BH): New variant set.
 453         (OP_SVE_VZV_SD): New variant set.
 454         (aarch64_opcode_table): Add sve2 instructions.
 455
 456 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 457
 458         * aarch64-asm-2.c: Regenerated.
 459         * aarch64-dis-2.c: Regenerated.
 460         * aarch64-opc-2.c: Regenerated.
 461         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 462         for SVE_SHLIMM_UNPRED_22.
 463         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 464         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 465         operand.
 466
 467 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 468
 469         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 470         sve_size_tsz_bhs iclass encode.
 471         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 472         sve_size_tsz_bhs iclass decode.
 473
 474 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 475
 476         * aarch64-asm-2.c: Regenerated.
 477         * aarch64-dis-2.c: Regenerated.
 478         * aarch64-opc-2.c: Regenerated.
 479         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 480         for SVE_Zm4_11_INDEX.
 481         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 482         (fields): Handle SVE_i2h field.
 483         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 484         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 485
 486 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 487
 488         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 489         sve_shift_tsz_bhsd iclass encode.
 490         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 491         sve_shift_tsz_bhsd iclass decode.
 492
 493 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 494
 495         * aarch64-asm-2.c: Regenerated.
 496         * aarch64-dis-2.c: Regenerated.
 497         * aarch64-opc-2.c: Regenerated.
 498         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 499         (aarch64_encode_variant_using_iclass): Handle
 500         sve_shift_tsz_hsd iclass encode.
 501         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 502         sve_shift_tsz_hsd iclass decode.
 503         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 504         for SVE_SHRIMM_UNPRED_22.
 505         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 506         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 507         operand.
 508
 509 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 510
 511         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 512         sve_size_013 iclass encode.
 513         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 514         sve_size_013 iclass decode.
 515
 516 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 517
 518         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 519         sve_size_bh iclass encode.
 520         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 521         sve_size_bh iclass decode.
 522
 523 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 524
 525         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 526         sve_size_sd2 iclass encode.
 527         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 528         sve_size_sd2 iclass decode.
 529         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 530         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 531
 532 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 533
 534         * aarch64-asm-2.c: Regenerated.
 535         * aarch64-dis-2.c: Regenerated.
 536         * aarch64-opc-2.c: Regenerated.
 537         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 538         for SVE_ADDR_ZX.
 539         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 540         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 541
 542 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 543
 544         * aarch64-asm-2.c: Regenerated.
 545         * aarch64-dis-2.c: Regenerated.
 546         * aarch64-opc-2.c: Regenerated.
 547         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 548         for SVE_Zm3_11_INDEX.
 549         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 550         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 551         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 552         fields.
 553         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 554
 555 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 556
 557         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 558         sve_size_hsd2 iclass encode.
 559         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 560         sve_size_hsd2 iclass decode.
 561         * aarch64-opc.c (fields): Handle SVE_size field.
 562         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 563
 564 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 565
 566         * aarch64-asm-2.c: Regenerated.
 567         * aarch64-dis-2.c: Regenerated.
 568         * aarch64-opc-2.c: Regenerated.
 569         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 570         for SVE_IMM_ROT3.
 571         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 572         (fields): Handle SVE_rot3 field.
 573         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 574         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 575
 576 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 577
 578         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 579         instructions.
 580
 581 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 582
 583         * aarch64-tbl.h
 584         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 585         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 586         aarch64_feature_sve2bitperm): New feature sets.
 587         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 588         for feature set addresses.
 589         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 590         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 591
 592 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 593             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 594
 595         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 596         argument and set ASE_EVA_R6 appropriately.
 597         (set_default_mips_dis_options): Pass ISA to above.
 598         (parse_mips_dis_option): Likewise.
 599         * mips-opc.c (EVAR6): New macro.
 600         (mips_builtin_opcodes): Add llwpe, scwpe.
 601
 602 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 603
 604         * aarch64-asm-2.c: Regenerated.
 605         * aarch64-dis-2.c: Regenerated.
 606         * aarch64-opc-2.c: Regenerated.
 607         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 608         AARCH64_OPND_TME_UIMM16.
 609         (aarch64_print_operand): Likewise.
 610         * aarch64-tbl.h (QL_IMM_NIL): New.
 611         (TME): New.
 612         (_TME_INSN): New.
 613         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 614
 615 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 616
 617         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 618
 619 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 620             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 621
 622         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 623
 624 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 625
 626         * s12z-opc.h: Add extern "C" bracketing to help
 627         users who wish to use this interface in c++ code.
 628
 629 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 630
 631         * s12z-opc.c (bm_decode): Handle bit map operations with the
 632         "reserved0" mode.
 633
 634 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 635
 636         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 637         specifier.  Add entries for VLDR and VSTR of system registers.
 638         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 639         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 640         of %J and %K format specifier.
 641
 642 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 643
 644         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 645         Add new entries for VSCCLRM instruction.
 646         (print_insn_coprocessor): Handle new %C format control code.
 647
 648 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 649
 650         * arm-dis.c (enum isa): New enum.
 651         (struct sopcode32): New structure.
 652         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 653         set isa field of all current entries to ANY.
 654         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 655         Only match an entry if its isa field allows the current mode.
 656
 657 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 658
 659         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 660         CLRM.
 661         (print_insn_thumb32): Add logic to print %n CLRM register list.
 662
 663 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 664
 665         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 666         and %Q patterns.
 667
 668 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 669
 670         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 671         (print_insn_thumb32): Edit the switch case for %Z.
 672
 673 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 674
 675         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 676
 677 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 678
 679         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 680
 681 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 682
 683         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 684
 685 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 686
 687         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 688         Arm register with r13 and r15 unpredictable.
 689         (thumb32_opcodes): New instructions for bfx and bflx.
 690
 691 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 692
 693         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 694
 695 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 696
 697         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 698
 699 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 700
 701         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 702
 703 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 704
 705         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 706
 707 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 708
 709         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 710         "optr". ("operator" is a reserved word in c++).
 711
 712 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 713
 714         * aarch64-opc.c (aarch64_print_operand): Add case for
 715         AARCH64_OPND_Rt_SP.
 716         (verify_constraints): Likewise.
 717         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 718         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 719         to accept Rt|SP as first operand.
 720         (AARCH64_OPERANDS): Add new Rt_SP.
 721         * aarch64-asm-2.c: Regenerated.
 722         * aarch64-dis-2.c: Regenerated.
 723         * aarch64-opc-2.c: Regenerated.
 724
 725 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 726
 727         * aarch64-asm-2.c: Regenerated.
 728         * aarch64-dis-2.c: Likewise.
 729         * aarch64-opc-2.c: Likewise.
 730         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 731
 732 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 733
 734         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 735
 736 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 737
 738         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 739         * i386-init.h: Regenerated.
 740
 741 2019-04-07  Alan Modra  <amodra@gmail.com>
 742
 743         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 744         op_separator to control printing of spaces, comma and parens
 745         rather than need_comma, need_paren and spaces vars.
 746
 747 2019-04-07  Alan Modra  <amodra@gmail.com>
 748
 749         PR 24421
 750         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 751         (print_insn_neon, print_insn_arm): Likewise.
 752
 753 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 754
 755         * i386-dis-evex.h (evex_table): Updated to support BF16
 756         instructions.
 757         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 758         and EVEX_W_0F3872_P_3.
 759         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 760         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 761         * i386-opc.h (enum): Add CpuAVX512_BF16.
 762         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 763         * i386-opc.tbl: Add AVX512 BF16 instructions.
 764         * i386-init.h: Regenerated.
 765         * i386-tbl.h: Likewise.
 766
 767 2019-04-05  Alan Modra  <amodra@gmail.com>
 768
 769         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 770         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 771         to favour printing of "-" branch hint when using the "y" bit.
 772         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 773
 774 2019-04-05  Alan Modra  <amodra@gmail.com>
 775
 776         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 777         opcode until first operand is output.
 778
 779 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 780
 781         PR gas/24349
 782         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 783         (valid_bo_post_v2): Add support for 'at' branch hints.
 784         (insert_bo): Only error on branch on ctr.
 785         (get_bo_hint_mask): New function.
 786         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 787         for inserting 'at' branch hints.
 788         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 789         for extracting 'at' branch hints.
 790         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 791         (BOE): Delete operand.
 792         (BOM, BOP): New operands.
 793         (RM): Update value.
 794         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 795         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 796         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 797         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 798         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 799         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 800         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 801         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 802         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 803         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 804         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 805         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 806         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 807         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 808         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 809         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 810         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 811         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 812         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 813         bttarl+>: New extended mnemonics.
 814
 815 2019-03-28  Alan Modra  <amodra@gmail.com>
 816
 817         PR 24390
 818         * ppc-opc.c (BTF): Define.
 819         (powerpc_opcodes): Use for mtfsb*.
 820         * ppc-dis.c (print_insn_powerpc): Print fields with both
 821         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 822
 823 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 824
 825         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 826         (mapping_symbol_for_insn): Implement new algorithm.
 827         (print_insn): Remove duplicate code.
 828
 829 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 830
 831         * aarch64-dis.c (print_insn_aarch64):
 832         Implement override.
 833
 834 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 835
 836         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 837         order.
 838
 839 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 840
 841         * aarch64-dis.c (last_stop_offset): New.
 842         (print_insn_aarch64): Use stop_offset.
 843
 844 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 845
 846         PR gas/24359
 847         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 848         CPU_ANY_AVX2_FLAGS.
 849         * i386-init.h: Regenerated.
 850
 851 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 852
 853         PR gas/24348
 854         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 855         vmovdqu16, vmovdqu32 and vmovdqu64.
 856         * i386-tbl.h: Regenerated.
 857
 858 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 859
 860         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 861         from vstrszb, vstrszh, and vstrszf.
 862
 863 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 864
 865         * s390-opc.txt: Add instruction descriptions.
 866
 867 2019-02-08  Jim Wilson  <jimw@sifive.com>
 868
 869         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 870         <bne>: Likewise.
 871
 872 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 873
 874         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 875
 876 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 877
 878         PR binutils/23212
 879         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 880         * aarch64-opc.c (verify_elem_sd): New.
 881         (fields): Add FLD_sz entr.
 882         * aarch64-tbl.h (_SIMD_INSN): New.
 883         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 884         fmulx scalar and vector by element isns.
 885
 886 2019-02-07  Nick Clifton  <nickc@redhat.com>
 887
 888         * po/sv.po: Updated Swedish translation.
 889
 890 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 891
 892         * s390-mkopc.c (main): Accept arch13 as cpu string.
 893         * s390-opc.c: Add new instruction formats and instruction opcode
 894         masks.
 895         * s390-opc.txt: Add new arch13 instructions.
 896
 897 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 898
 899         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 900         (aarch64_opcode): Change encoding for stg, stzg
 901         st2g and st2zg.
 902         * aarch64-asm-2.c: Regenerated.
 903         * aarch64-dis-2.c: Regenerated.
 904         * aarch64-opc-2.c: Regenerated.
 905
 906 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 907
 908         * aarch64-asm-2.c: Regenerated.
 909         * aarch64-dis-2.c: Likewise.
 910         * aarch64-opc-2.c: Likewise.
 911         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 912
 913 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 914             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 915
 916         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 917         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 918         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 919         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 920         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 921         case for ldstgv_indexed.
 922         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 923         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 924         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 925         * aarch64-asm-2.c: Regenerated.
 926         * aarch64-dis-2.c: Regenerated.
 927         * aarch64-opc-2.c: Regenerated.
 928
 929 2019-01-23  Nick Clifton  <nickc@redhat.com>
 930
 931         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 932
 933 2019-01-21  Nick Clifton  <nickc@redhat.com>
 934
 935         * po/de.po: Updated German translation.
 936         * po/uk.po: Updated Ukranian translation.
 937
 938 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 939         * mips-dis.c (mips_arch_choices): Fix typo in
 940         gs464, gs464e and gs264e descriptors.
 941
 942 2019-01-19  Nick Clifton  <nickc@redhat.com>
 943
 944         * configure: Regenerate.
 945         * po/opcodes.pot: Regenerate.
 946
 947 2018-06-24  Nick Clifton  <nickc@redhat.com>
 948
 949         2.32 branch created.
 950
 951 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 952
 953         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 954         if it is null.
 955         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 956         zero.
 957
 958 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 959
 960         * configure: Regenerate.
 961
 962 2019-01-07  Alan Modra  <amodra@gmail.com>
 963
 964         * configure: Regenerate.
 965         * po/POTFILES.in: Regenerate.
 966
 967 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 968
 969         * s12z-opc.c: New file.
 970         * s12z-opc.h: New file.
 971         * s12z-dis.c: Removed all code not directly related to display
 972         of instructions.  Used the interface provided by the new files
 973         instead.
 974         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 975         * Makefile.in: Regenerate.
 976         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 977         * configure: Regenerate.
 978
 979 2019-01-01  Alan Modra  <amodra@gmail.com>
 980
 981         Update year range in copyright notice of all files.
 982
 983 For older changes see ChangeLog-2018
 984 \f
 985 Copyright (C) 2019 Free Software Foundation, Inc.
 986
 987 Copying and distribution of this file, with or without modification,
 988 are permitted in any medium without royalty provided the copyright
 989 notice and this notice are preserved.
 990
 991 Local Variables:
 992 mode: change-log
 993 left-margin: 8
 994 fill-column: 74
 995 version-control: never
 996 End: