1 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
3 * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
6 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
8 * mips-dis.c (set_default_mips_dis_options): Use
9 HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
10 call to `bfd_mips_elf_get_abiflags'.
11 * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
12 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
13 * aclocal.m4: Regenerate.
14 * configure: Regenerate.
15 * config.in: Regenerate.
16 * Makefile.in: Regenerate.
18 2016-12-23 Tristan Gingold <gingold@adacore.com>
20 * configure: Regenerate.
22 2016-12-23 Tristan Gingold <gingold@adacore.com>
24 * po/opcodes.pot: Regenerate.
26 2016-12-21 Andrew Waterman <andrew@sifive.com>
28 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
30 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
32 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
33 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
34 (print_insn_mips16): Check opcode entries for validity against
35 the ISA level and ASE set selected.
37 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
39 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
40 `insn' together, with `extend' as the high-order 16 bits.
41 (match_kind): New enum.
42 (print_insn_mips16): Rework for 32-bit instruction matching.
43 Do not dump EXTEND prefixes here.
44 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
45 Recode `match' and `mask' fields as 32-bit in absolute "jal" and
48 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
50 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
51 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
54 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
56 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
57 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
60 2016-12-20 Andrew Waterman <andrew@sifive.com>
62 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
65 2016-12-20 Andrew Waterman <andrew@sifive.com>
67 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
70 2016-12-20 Andrew Waterman <andrew@sifive.com>
72 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
75 2016-12-20 Andrew Waterman <andrew@sifive.com>
77 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
78 XLEN when none is provided.
80 2016-12-20 Andrew Waterman <andrew@sifive.com>
82 * riscv-opc.c: Formatting fixes.
84 2016-12-20 Alan Modra <amodra@gmail.com>
86 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
87 * Makefile.in: Regenerate.
88 * po/POTFILES.in: Regenerate.
90 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
92 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
93 Only examine ELF file structures here.
95 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
97 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
98 `bfd_mips_elf_get_abiflags' here.
100 2016-12-16 Nick Clifton <nickc@redhat.com>
102 * arm-dis.c (print_insn_thumb32): Fix compile time warning
103 computing value_in_comment.
105 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
107 * mips-dis.c (mips_convert_abiflags_ases): New function.
108 (set_default_mips_dis_options): Also infer ASE flags from ELF
111 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
113 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
114 header flag interpretation code.
116 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
118 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
119 `pinfo2' with SP-relative "sd" entries.
121 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
123 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
126 2016-12-13 Renlin Li <renlin.li@arm.com>
128 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
130 (operand_general_constraint_met_p): Remove case for CP_REG.
131 (aarch64_print_operand): Print CRn, CRm operand using imm field.
132 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
134 (aarch64_opcode_table): Change CRn, CRm operand class and type.
135 * aarch64-opc-2.c : Regenerate.
136 * aarch64-asm-2.c : Likewise.
137 * aarch64-dis-2.c : Likewise.
139 2016-12-12 Yao Qi <yao.qi@linaro.org>
141 * rx-dis.c: Include <setjmp.h>
142 (struct private): New.
143 (rx_get_byte): Check return value of read_memory_func, and
144 call memory_error_func and OPCODES_SIGLONGJMP on error.
145 (print_insn_rx): Call OPCODES_SIGSETJMP.
147 2016-12-12 Yao Qi <yao.qi@linaro.org>
149 * rl78-dis.c: Include <setjmp.h>.
150 (struct private): New.
151 (rl78_get_byte): Check return value of read_memory_func, and
152 call memory_error_func and OPCODES_SIGLONGJMP on error.
153 (print_insn_rl78_common): Call OPCODES_SIGJMP.
155 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
157 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
159 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
161 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
164 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
166 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
167 to separate `extend' and its uninterpreted argument output.
168 Separate hexadecimal halves of undecoded extended instructions
171 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
173 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
174 indentation space across.
176 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
178 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
179 adjustment for PC-relative operations following MIPS16e compact
180 jumps or undefined RR/J(AL)R(C) encodings.
182 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
184 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
185 variable to `reglane_index'.
187 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
189 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
191 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
193 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
195 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
197 * mips16-opc.c (mips16_opcodes): Update comment naming structure
200 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
202 * mips-dis.c (print_mips_disassembler_options): Reformat output.
204 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
206 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
207 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
209 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
211 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
213 2016-12-01 Nick Clifton <nickc@redhat.com>
216 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
219 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
221 * arc-opc.c (insert_ra_chk): New function.
222 (insert_rb_chk): Likewise.
223 (insert_rad): Update text error message.
224 (insert_rcd): Likewise.
225 (insert_rhv2): Likewise.
226 (insert_r0): Likewise.
227 (insert_r1): Likewise.
228 (insert_r2): Likewise.
229 (insert_r3): Likewise.
230 (insert_sp): Likewise.
231 (insert_gp): Likewise.
232 (insert_pcl): Likewise.
233 (insert_blink): Likewise.
234 (insert_ilink1): Likewise.
235 (insert_ilink2): Likewise.
236 (insert_ras): Likewise.
237 (insert_rbs): Likewise.
238 (insert_rcs): Likewise.
239 (insert_simm3s): Likewise.
240 (insert_rrange): Likewise.
241 (insert_fpel): Likewise.
242 (insert_blinkel): Likewise.
243 (insert_pcel): Likewise.
244 (insert_nps_3bit_dst): Likewise.
245 (insert_nps_3bit_dst_short): Likewise.
246 (insert_nps_3bit_src2_short): Likewise.
247 (insert_nps_bitop_size_2b): Likewise.
248 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
253 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
254 * arc-tbl.h (div, divu): All instructions are DIVREM class.
255 Change first insn argument to check for LP_COUNT usage.
257 (ld, ldd): All instructions are LOAD class. Change first insn
258 argument to check for LP_COUNT usage.
259 (st, std): All instructions are STORE class.
260 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
261 Change first insn argument to check for LP_COUNT usage.
262 (mov): All instructions are MOVE class. Change first insn
263 argument to check for LP_COUNT usage.
265 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
267 * arc-dis.c (is_compatible_p): Remove function.
268 (skip_this_opcode): Don't add any decoding class to decode list.
270 (find_format_from_table): Go through all opcodes, and warn if we
271 use a guessed mnemonic.
273 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
274 Amit Pawar <amit.pawar@amd.com>
277 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
280 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
282 * configure: Regenerate.
284 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
286 * sparc-opc.c (HWS_V8): Definition moved from
287 gas/config/tc-sparc.c.
297 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
300 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
302 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
305 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
307 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
308 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
309 (aarch64_opcode_table): Add fcmla and fcadd.
310 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
311 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
312 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
313 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
314 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
315 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
316 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
317 (operand_general_constraint_met_p): Rotate and index range check.
318 (aarch64_print_operand): Handle rotate operand.
319 * aarch64-asm-2.c: Regenerate.
320 * aarch64-dis-2.c: Likewise.
321 * aarch64-opc-2.c: Likewise.
323 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
325 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
326 * aarch64-asm-2.c: Regenerate.
327 * aarch64-dis-2.c: Regenerate.
328 * aarch64-opc-2.c: Regenerate.
330 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
332 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
333 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
334 * aarch64-asm-2.c: Regenerate.
335 * aarch64-dis-2.c: Regenerate.
336 * aarch64-opc-2.c: Regenerate.
338 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
340 * aarch64-tbl.h (QL_X1NIL): New.
341 (arch64_opcode_table): Add ldraa, ldrab.
342 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
343 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
344 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
345 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
346 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
347 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
348 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
349 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
350 (aarch64_print_operand): Likewise.
351 * aarch64-asm-2.c: Regenerate.
352 * aarch64-dis-2.c: Regenerate.
353 * aarch64-opc-2.c: Regenerate.
355 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
357 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
358 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
359 * aarch64-asm-2.c: Regenerate.
360 * aarch64-dis-2.c: Regenerate.
361 * aarch64-opc-2.c: Regenerate.
363 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
365 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
366 (AARCH64_OPERANDS): Add Rm_SP.
367 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
368 * aarch64-asm-2.c: Regenerate.
369 * aarch64-dis-2.c: Regenerate.
370 * aarch64-opc-2.c: Regenerate.
372 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
374 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
375 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
376 autdzb, xpaci, xpacd.
377 * aarch64-asm-2.c: Regenerate.
378 * aarch64-dis-2.c: Regenerate.
379 * aarch64-opc-2.c: Regenerate.
381 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
383 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
384 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
385 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
386 (aarch64_sys_reg_supported_p): Add feature test for new registers.
388 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
390 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
391 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
392 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
394 * aarch64-asm-2.c: Regenerate.
395 * aarch64-dis-2.c: Regenerate.
397 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
399 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
401 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
404 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
405 * i386-dis.c (EdqwS): Removed.
406 (dqw_swap_mode): Likewise.
407 (intel_operand_size): Don't check dqw_swap_mode.
408 (OP_E_register): Likewise.
409 (OP_E_memory): Likewise.
412 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
413 * i386-tbl.h: Regerated.
415 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
417 * i386-opc.tbl: Merge AVX512F vmovq.
418 * i386-tbl.h: Regerated.
420 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
423 * i386-dis.c (THREE_BYTE_0F7A): Removed.
424 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
425 (three_byte_table): Remove THREE_BYTE_0F7A.
427 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
430 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
431 (FGRPd9_4): Replace 1 with 2.
432 (FGRPd9_5): Replace 2 with 3.
433 (FGRPd9_6): Replace 3 with 4.
434 (FGRPd9_7): Replace 4 with 5.
435 (FGRPda_5): Replace 5 with 6.
436 (FGRPdb_4): Replace 6 with 7.
437 (FGRPde_3): Replace 7 with 8.
438 (FGRPdf_4): Replace 8 with 9.
439 (fgrps): Add an entry for Bad_Opcode.
441 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
443 * arc-opc.c (arc_flag_operands): Add F_DI14.
444 (arc_flag_classes): Add C_DI14.
445 * arc-nps400-tbl.h: Add new exc instructions.
447 2016-11-03 Graham Markall <graham.markall@embecosm.com>
449 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
451 * arc-nps-400-tbl.h: Add dcmac instruction.
452 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
453 (insert_nps_rbdouble_64): Added.
454 (extract_nps_rbdouble_64): Added.
455 (insert_nps_proto_size): Added.
456 (extract_nps_proto_size): Added.
458 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
460 * arc-dis.c (struct arc_operand_iterator): Remove all fields
461 relating to long instruction processing, add new limm field.
462 (OPCODE): Rename to...
463 (OPCODE_32BIT_INSN): ...this.
465 (skip_this_opcode): Handle different instruction lengths, update
467 (special_flag_p): Update parameter type.
468 (find_format_from_table): Update for more instruction lengths.
469 (find_format_long_instructions): Delete.
470 (find_format): Update for more instruction lengths.
471 (arc_insn_length): Likewise.
472 (extract_operand_value): Update for more instruction lengths.
473 (operand_iterator_next): Remove code relating to long
475 (arc_opcode_to_insn_type): New function.
476 (print_insn_arc):Update for more instructions lengths.
477 * arc-ext.c (extInstruction_t): Change argument type.
478 * arc-ext.h (extInstruction_t): Change argument type.
479 * arc-fxi.h: Change type unsigned to unsigned long long
480 extensively throughout.
481 * arc-nps400-tbl.h: Add long instructions taken from
482 arc_long_opcodes table in arc-opc.c.
483 * arc-opc.c: Update parameter types on insert/extract handlers.
484 (arc_long_opcodes): Delete.
485 (arc_num_long_opcodes): Delete.
486 (arc_opcode_len): Update for more instruction lengths.
488 2016-11-03 Graham Markall <graham.markall@embecosm.com>
490 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
492 2016-11-03 Graham Markall <graham.markall@embecosm.com>
494 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
496 (find_format_long_instructions): Likewise.
497 * arc-opc.c (arc_opcode_len): New function.
499 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
501 * arc-nps400-tbl.h: Fix some instruction masks.
503 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
505 * i386-dis.c (REG_82): Removed.
506 (X86_64_82_REG_0): Likewise.
507 (X86_64_82_REG_1): Likewise.
508 (X86_64_82_REG_2): Likewise.
509 (X86_64_82_REG_3): Likewise.
510 (X86_64_82_REG_4): Likewise.
511 (X86_64_82_REG_5): Likewise.
512 (X86_64_82_REG_6): Likewise.
513 (X86_64_82_REG_7): Likewise.
515 (dis386): Use X86_64_82 instead of REG_82.
516 (reg_table): Remove REG_82.
517 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
518 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
519 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
522 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
525 * i386-dis.c (REG_82): New.
526 (X86_64_82_REG_0): Likewise.
527 (X86_64_82_REG_1): Likewise.
528 (X86_64_82_REG_2): Likewise.
529 (X86_64_82_REG_3): Likewise.
530 (X86_64_82_REG_4): Likewise.
531 (X86_64_82_REG_5): Likewise.
532 (X86_64_82_REG_6): Likewise.
533 (X86_64_82_REG_7): Likewise.
534 (dis386): Use REG_82.
535 (reg_table): Add REG_82.
536 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
537 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
538 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
540 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
542 * i386-dis.c (REG_82): Renamed to ...
545 (reg_table): Likewise.
547 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
549 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
550 * i386-dis-evex.h (evex_table): Updated.
551 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
552 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
553 (cpu_flags): Add CpuAVX512_4VNNIW.
554 * i386-opc.h (enum): (AVX512_4VNNIW): New.
555 (i386_cpu_flags): Add cpuavx512_4vnniw.
556 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
557 * i386-init.h: Regenerate.
560 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
562 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
563 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
564 * i386-dis-evex.h (evex_table): Updated.
565 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
566 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
567 (cpu_flags): Add CpuAVX512_4FMAPS.
568 (opcode_modifiers): Add ImplicitQuadGroup modifier.
569 * i386-opc.h (AVX512_4FMAP): New.
570 (i386_cpu_flags): Add cpuavx512_4fmaps.
571 (ImplicitQuadGroup): New.
572 (i386_opcode_modifier): Add implicitquadgroup.
573 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
574 * i386-init.h: Regenerate.
577 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
578 Andrew Waterman <andrew@sifive.com>
580 Add support for RISC-V architecture.
581 * configure.ac: Add entry for bfd_riscv_arch.
582 * configure: Regenerate.
583 * disassemble.c (disassembler): Add support for riscv.
584 (disassembler_usage): Likewise.
585 * riscv-dis.c: New file.
586 * riscv-opc.c: New file.
588 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
590 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
591 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
592 (rm_table): Update the RM_0FAE_REG_7 entry.
593 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
594 (cpu_flags): Remove CpuPCOMMIT.
595 * i386-opc.h (CpuPCOMMIT): Removed.
596 (i386_cpu_flags): Remove cpupcommit.
597 * i386-opc.tbl: Remove pcommit.
598 * i386-init.h: Regenerated.
599 * i386-tbl.h: Likewise.
601 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
604 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
605 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
606 32-bit mode. Don't check vex.register_specifier in 32-bit
608 (OP_VEX): Check for invalid mask registers.
610 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
613 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
616 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
619 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
621 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
623 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
624 local variable to `index_regno'.
626 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
628 * arc-tbl.h: Removed any "inv.+" instructions from the table.
630 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
632 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
635 2016-10-11 Jiong Wang <jiong.wang@arm.com>
638 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
640 2016-10-07 Jiong Wang <jiong.wang@arm.com>
643 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
646 2016-10-07 Alan Modra <amodra@gmail.com>
648 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
650 2016-10-06 Alan Modra <amodra@gmail.com>
652 * aarch64-opc.c: Spell fall through comments consistently.
653 * i386-dis.c: Likewise.
654 * aarch64-dis.c: Add missing fall through comments.
655 * aarch64-opc.c: Likewise.
656 * arc-dis.c: Likewise.
657 * arm-dis.c: Likewise.
658 * i386-dis.c: Likewise.
659 * m68k-dis.c: Likewise.
660 * mep-asm.c: Likewise.
661 * ns32k-dis.c: Likewise.
662 * sh-dis.c: Likewise.
663 * tic4x-dis.c: Likewise.
664 * tic6x-dis.c: Likewise.
665 * vax-dis.c: Likewise.
667 2016-10-06 Alan Modra <amodra@gmail.com>
669 * arc-ext.c (create_map): Add missing break.
670 * msp430-decode.opc (encode_as): Likewise.
671 * msp430-decode.c: Regenerate.
673 2016-10-06 Alan Modra <amodra@gmail.com>
675 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
676 * crx-dis.c (print_insn_crx): Likewise.
678 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
681 * i386-dis.c (putop): Don't assign alt twice.
683 2016-09-29 Jiong Wang <jiong.wang@arm.com>
686 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
688 2016-09-29 Alan Modra <amodra@gmail.com>
690 * ppc-opc.c (L): Make compulsory.
691 (LOPT): New, optional form of L.
692 (HTM_R): Define as LOPT.
694 (L32OPT): New, optional for 32-bit L.
695 (L2OPT): New, 2-bit L for dcbf.
698 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
699 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
701 <tlbiel, tlbie>: Use LOPT.
702 <wclr, wclrall>: Use L2.
704 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
706 * Makefile.in: Regenerate.
707 * configure: Likewise.
709 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
711 * arc-ext-tbl.h (EXTINSN2OPF): Define.
712 (EXTINSN2OP): Use EXTINSN2OPF.
713 (bspeekm, bspop, modapp): New extension instructions.
714 * arc-opc.c (F_DNZ_ND): Define.
719 * arc-tbl.h (dbnz): New instruction.
720 (prealloc): Allow it for ARC EM.
723 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
725 * aarch64-opc.c (print_immediate_offset_address): Print spaces
726 after commas in addresses.
727 (aarch64_print_operand): Likewise.
729 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
731 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
732 rather than "should be" or "expected to be" in error messages.
734 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
736 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
737 (print_mnemonic_name): ...here.
738 (print_comment): New function.
739 (print_aarch64_insn): Call it.
740 * aarch64-opc.c (aarch64_conds): Add SVE names.
741 (aarch64_print_operand): Print alternative condition names in
744 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
746 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
747 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
748 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
749 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
750 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
751 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
752 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
753 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
754 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
755 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
756 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
757 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
758 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
759 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
760 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
761 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
762 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
763 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
764 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
765 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
766 (OP_SVE_XWU, OP_SVE_XXU): New macros.
767 (aarch64_feature_sve): New variable.
769 (_SVE_INSN): Likewise.
770 (aarch64_opcode_table): Add SVE instructions.
771 * aarch64-opc.h (extract_fields): Declare.
772 * aarch64-opc-2.c: Regenerate.
773 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
774 * aarch64-asm-2.c: Regenerate.
775 * aarch64-dis.c (extract_fields): Make global.
776 (do_misc_decoding): Handle the new SVE aarch64_ops.
777 * aarch64-dis-2.c: Regenerate.
779 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
781 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
782 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
784 * aarch64-opc.c (fields): Add corresponding entries.
785 * aarch64-asm.c (aarch64_get_variant): New function.
786 (aarch64_encode_variant_using_iclass): Likewise.
787 (aarch64_opcode_encode): Call it.
788 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
789 (aarch64_opcode_decode): Call it.
791 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
793 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
794 and FP register operands.
795 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
796 (FLD_SVE_Vn): New aarch64_field_kinds.
797 * aarch64-opc.c (fields): Add corresponding entries.
798 (aarch64_print_operand): Handle the new SVE core and FP register
800 * aarch64-opc-2.c: Regenerate.
801 * aarch64-asm-2.c: Likewise.
802 * aarch64-dis-2.c: Likewise.
804 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
806 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
808 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
809 * aarch64-opc.c (fields): Add corresponding entry.
810 (operand_general_constraint_met_p): Handle the new SVE FP immediate
812 (aarch64_print_operand): Likewise.
813 * aarch64-opc-2.c: Regenerate.
814 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
815 (ins_sve_float_zero_one): New inserters.
816 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
817 (aarch64_ins_sve_float_half_two): Likewise.
818 (aarch64_ins_sve_float_zero_one): Likewise.
819 * aarch64-asm-2.c: Regenerate.
820 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
821 (ext_sve_float_zero_one): New extractors.
822 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
823 (aarch64_ext_sve_float_half_two): Likewise.
824 (aarch64_ext_sve_float_zero_one): Likewise.
825 * aarch64-dis-2.c: Regenerate.
827 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
829 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
830 integer immediate operands.
831 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
832 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
833 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
834 * aarch64-opc.c (fields): Add corresponding entries.
835 (operand_general_constraint_met_p): Handle the new SVE integer
837 (aarch64_print_operand): Likewise.
838 (aarch64_sve_dupm_mov_immediate_p): New function.
839 * aarch64-opc-2.c: Regenerate.
840 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
841 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
842 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
843 (aarch64_ins_limm): ...here.
844 (aarch64_ins_inv_limm): New function.
845 (aarch64_ins_sve_aimm): Likewise.
846 (aarch64_ins_sve_asimm): Likewise.
847 (aarch64_ins_sve_limm_mov): Likewise.
848 (aarch64_ins_sve_shlimm): Likewise.
849 (aarch64_ins_sve_shrimm): Likewise.
850 * aarch64-asm-2.c: Regenerate.
851 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
852 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
853 * aarch64-dis.c (decode_limm): New function, split out from...
854 (aarch64_ext_limm): ...here.
855 (aarch64_ext_inv_limm): New function.
856 (decode_sve_aimm): Likewise.
857 (aarch64_ext_sve_aimm): Likewise.
858 (aarch64_ext_sve_asimm): Likewise.
859 (aarch64_ext_sve_limm_mov): Likewise.
860 (aarch64_top_bit): Likewise.
861 (aarch64_ext_sve_shlimm): Likewise.
862 (aarch64_ext_sve_shrimm): Likewise.
863 * aarch64-dis-2.c: Regenerate.
865 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
867 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
869 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
870 the AARCH64_MOD_MUL_VL entry.
871 (value_aligned_p): Cope with non-power-of-two alignments.
872 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
873 (print_immediate_offset_address): Likewise.
874 (aarch64_print_operand): Likewise.
875 * aarch64-opc-2.c: Regenerate.
876 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
877 (ins_sve_addr_ri_s9xvl): New inserters.
878 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
879 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
880 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
881 * aarch64-asm-2.c: Regenerate.
882 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
883 (ext_sve_addr_ri_s9xvl): New extractors.
884 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
885 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
886 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
887 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
888 * aarch64-dis-2.c: Regenerate.
890 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
892 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
894 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
895 (FLD_SVE_xs_22): New aarch64_field_kinds.
896 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
897 (get_operand_specific_data): New function.
898 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
899 FLD_SVE_xs_14 and FLD_SVE_xs_22.
900 (operand_general_constraint_met_p): Handle the new SVE address
902 (sve_reg): New array.
903 (get_addr_sve_reg_name): New function.
904 (aarch64_print_operand): Handle the new SVE address operands.
905 * aarch64-opc-2.c: Regenerate.
906 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
907 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
908 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
909 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
910 (aarch64_ins_sve_addr_rr_lsl): Likewise.
911 (aarch64_ins_sve_addr_rz_xtw): Likewise.
912 (aarch64_ins_sve_addr_zi_u5): Likewise.
913 (aarch64_ins_sve_addr_zz): Likewise.
914 (aarch64_ins_sve_addr_zz_lsl): Likewise.
915 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
916 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
917 * aarch64-asm-2.c: Regenerate.
918 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
919 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
920 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
921 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
922 (aarch64_ext_sve_addr_ri_u6): Likewise.
923 (aarch64_ext_sve_addr_rr_lsl): Likewise.
924 (aarch64_ext_sve_addr_rz_xtw): Likewise.
925 (aarch64_ext_sve_addr_zi_u5): Likewise.
926 (aarch64_ext_sve_addr_zz): Likewise.
927 (aarch64_ext_sve_addr_zz_lsl): Likewise.
928 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
929 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
930 * aarch64-dis-2.c: Regenerate.
932 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
934 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
935 AARCH64_OPND_SVE_PATTERN_SCALED.
936 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
937 * aarch64-opc.c (fields): Add a corresponding entry.
938 (set_multiplier_out_of_range_error): New function.
939 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
940 (operand_general_constraint_met_p): Handle
941 AARCH64_OPND_SVE_PATTERN_SCALED.
942 (print_register_offset_address): Use PRIi64 to print the
944 (aarch64_print_operand): Likewise. Handle
945 AARCH64_OPND_SVE_PATTERN_SCALED.
946 * aarch64-opc-2.c: Regenerate.
947 * aarch64-asm.h (ins_sve_scale): New inserter.
948 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
949 * aarch64-asm-2.c: Regenerate.
950 * aarch64-dis.h (ext_sve_scale): New inserter.
951 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
952 * aarch64-dis-2.c: Regenerate.
954 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
956 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
957 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
958 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
959 (FLD_SVE_prfop): Likewise.
960 * aarch64-opc.c: Include libiberty.h.
961 (aarch64_sve_pattern_array): New variable.
962 (aarch64_sve_prfop_array): Likewise.
963 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
964 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
965 AARCH64_OPND_SVE_PRFOP.
966 * aarch64-asm-2.c: Regenerate.
967 * aarch64-dis-2.c: Likewise.
968 * aarch64-opc-2.c: Likewise.
970 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
972 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
973 AARCH64_OPND_QLF_P_[ZM].
974 (aarch64_print_operand): Print /z and /m where appropriate.
976 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
978 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
979 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
980 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
981 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
982 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
983 * aarch64-opc.c (fields): Add corresponding entries here.
984 (operand_general_constraint_met_p): Check that SVE register lists
985 have the correct length. Check the ranges of SVE index registers.
986 Check for cases where p8-p15 are used in 3-bit predicate fields.
987 (aarch64_print_operand): Handle the new SVE operands.
988 * aarch64-opc-2.c: Regenerate.
989 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
990 * aarch64-asm.c (aarch64_ins_sve_index): New function.
991 (aarch64_ins_sve_reglist): Likewise.
992 * aarch64-asm-2.c: Regenerate.
993 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
994 * aarch64-dis.c (aarch64_ext_sve_index): New function.
995 (aarch64_ext_sve_reglist): Likewise.
996 * aarch64-dis-2.c: Regenerate.
998 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1000 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
1001 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
1002 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
1003 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
1006 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1008 * aarch64-opc.c (get_offset_int_reg_name): New function.
1009 (print_immediate_offset_address): Likewise.
1010 (print_register_offset_address): Take the base and offset
1011 registers as parameters.
1012 (aarch64_print_operand): Update caller accordingly. Use
1013 print_immediate_offset_address.
1015 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1017 * aarch64-opc.c (BANK): New macro.
1018 (R32, R64): Take a register number as argument
1019 (int_reg): Use BANK.
1021 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1023 * aarch64-opc.c (print_register_list): Add a prefix parameter.
1024 (aarch64_print_operand): Update accordingly.
1026 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1028 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1030 * aarch64-asm.h (ins_fpimm): New inserter.
1031 * aarch64-asm.c (aarch64_ins_fpimm): New function.
1032 * aarch64-asm-2.c: Regenerate.
1033 * aarch64-dis.h (ext_fpimm): New extractor.
1034 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1035 (aarch64_ext_fpimm): New function.
1036 * aarch64-dis-2.c: Regenerate.
1038 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1040 * aarch64-asm.c: Include libiberty.h.
1041 (insert_fields): New function.
1042 (aarch64_ins_imm): Use it.
1043 * aarch64-dis.c (extract_fields): New function.
1044 (aarch64_ext_imm): Use it.
1046 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1048 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1049 with an esize parameter.
1050 (operand_general_constraint_met_p): Update accordingly.
1051 Fix misindented code.
1052 * aarch64-asm.c (aarch64_ins_limm): Update call to
1053 aarch64_logical_immediate_p.
1055 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1057 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1059 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1061 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1063 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1065 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1067 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1069 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1070 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1071 xor3>: Delete mnemonics.
1072 <cp_abort>: Rename mnemonic from ...
1073 <cpabort>: ...to this.
1074 <setb>: Change to a X form instruction.
1075 <sync>: Change to 1 operand form.
1076 <copy>: Delete mnemonic.
1077 <copy_first>: Rename mnemonic from ...
1079 <paste, paste.>: Delete mnemonics.
1080 <paste_last>: Rename mnemonic from ...
1081 <paste.>: ...to this.
1083 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1085 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1087 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1089 * s390-mkopc.c (main): Support alternate arch strings.
1091 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1093 * s390-opc.txt: Fix kmctr instruction type.
1095 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1097 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1098 * i386-init.h: Regenerated.
1100 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1102 * opcodes/arc-dis.c (print_insn_arc): Changed.
1104 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1106 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1109 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1111 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1112 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1113 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1115 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1117 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1118 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1119 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1120 PREFIX_MOD_3_0FAE_REG_4.
1121 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1122 PREFIX_MOD_3_0FAE_REG_4.
1123 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1124 (cpu_flags): Add CpuPTWRITE.
1125 * i386-opc.h (CpuPTWRITE): New.
1126 (i386_cpu_flags): Add cpuptwrite.
1127 * i386-opc.tbl: Add ptwrite instruction.
1128 * i386-init.h: Regenerated.
1129 * i386-tbl.h: Likewise.
1131 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1133 * arc-dis.h: Wrap around in extern "C".
1135 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1137 * aarch64-tbl.h (V8_2_INSN): New macro.
1138 (aarch64_opcode_table): Use it.
1140 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1142 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1143 CORE_INSN, __FP_INSN and SIMD_INSN.
1145 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1147 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1148 (aarch64_opcode_table): Update uses accordingly.
1150 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1151 Kwok Cheung Yeung <kcy@codesourcery.com>
1154 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1155 'e_cmplwi' to 'e_cmpli' instead.
1156 (OPVUPRT, OPVUPRT_MASK): Define.
1157 (powerpc_opcodes): Add E200Z4 insns.
1158 (vle_opcodes): Add context save/restore insns.
1160 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1162 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1163 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1166 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1168 * arc-nps400-tbl.h: Change block comments to GNU format.
1169 * arc-dis.c: Add new globals addrtypenames,
1170 addrtypenames_max, and addtypeunknown.
1171 (get_addrtype): New function.
1172 (print_insn_arc): Print colons and address types when
1174 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1175 define insert and extract functions for all address types.
1176 (arc_operands): Add operands for colon and all address
1178 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1179 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1180 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1181 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1182 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1183 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1185 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1187 * configure: Regenerated.
1189 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1191 * arc-dis.c (skipclass): New structure.
1192 (decodelist): New variable.
1193 (is_compatible_p): New function.
1194 (new_element): Likewise.
1195 (skip_class_p): Likewise.
1196 (find_format_from_table): Use skip_class_p function.
1197 (find_format): Decode first the extension instructions.
1198 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1200 (parse_option): New function.
1201 (parse_disassembler_options): Likewise.
1202 (print_arc_disassembler_options): Likewise.
1203 (print_insn_arc): Use parse_disassembler_options function. Proper
1204 select ARCv2 cpu variant.
1205 * disassemble.c (disassembler_usage): Add ARC disassembler
1208 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1210 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1211 annotation from the "nal" entry and reorder it beyond "bltzal".
1213 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1215 * sparc-opc.c (ldtxa): New macro.
1216 (sparc_opcodes): Use the macro defined above to add entries for
1217 the LDTXA instructions.
1218 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1221 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1223 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1226 2016-07-01 Jan Beulich <jbeulich@suse.com>
1228 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1229 (movzb): Adjust to cover all permitted suffixes.
1231 * i386-tbl.h: Re-generate.
1233 2016-07-01 Jan Beulich <jbeulich@suse.com>
1235 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1236 (lgdt): Remove Tbyte from non-64-bit variant.
1237 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1238 xsaves64, xsavec64): Remove Disp16.
1239 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1240 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1242 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1243 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1244 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1246 * i386-tbl.h: Re-generate.
1248 2016-07-01 Jan Beulich <jbeulich@suse.com>
1250 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1251 * i386-tbl.h: Re-generate.
1253 2016-06-30 Yao Qi <yao.qi@linaro.org>
1255 * arm-dis.c (print_insn): Fix typo in comment.
1257 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1259 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1260 range of ldst_elemlist operands.
1261 (print_register_list): Use PRIi64 to print the index.
1262 (aarch64_print_operand): Likewise.
1264 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1266 * mcore-opc.h: Remove sentinal.
1267 * mcore-dis.c (print_insn_mcore): Adjust.
1269 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1271 * arc-opc.c: Correct description of availability of NPS400
1274 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1276 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1277 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1278 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1279 xor3>: New mnemonics.
1280 <setb>: Change to a VX form instruction.
1281 (insert_sh6): Add support for rldixor.
1282 (extract_sh6): Likewise.
1284 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1286 * arc-ext.h: Wrap in extern C.
1288 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1290 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1291 Use same method for determining instruction length on ARC700 and
1293 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1294 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1295 with the NPS400 subclass.
1296 * arc-opc.c: Likewise.
1298 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1300 * sparc-opc.c (rdasr): New macro.
1306 (sparc_opcodes): Use the macros above to fix and expand the
1307 definition of read/write instructions from/to
1308 asr/privileged/hyperprivileged instructions.
1309 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1310 %hva_mask_nz. Prefer softint_set and softint_clear over
1311 set_softint and clear_softint.
1312 (print_insn_sparc): Support %ver in Rd.
1314 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1316 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1317 architecture according to the hardware capabilities they require.
1319 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1321 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1322 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1323 bfd_mach_sparc_v9{c,d,e,v,m}.
1324 * sparc-opc.c (MASK_V9C): Define.
1325 (MASK_V9D): Likewise.
1326 (MASK_V9E): Likewise.
1327 (MASK_V9V): Likewise.
1328 (MASK_V9M): Likewise.
1329 (v6): Add MASK_V9{C,D,E,V,M}.
1330 (v6notlet): Likewise.
1334 (v9andleon): Likewise.
1342 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1344 2016-06-15 Nick Clifton <nickc@redhat.com>
1346 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1347 constants to match expected behaviour.
1348 (nds32_parse_opcode): Likewise. Also for whitespace.
1350 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1352 * arc-opc.c (extract_rhv1): Extract value from insn.
1354 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1356 * arc-nps400-tbl.h: Add ldbit instruction.
1357 * arc-opc.c: Add flag classes required for ldbit.
1359 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1361 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1362 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1363 support the above instructions.
1365 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1367 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1368 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1369 csma, cbba, zncv, and hofs.
1370 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1371 support the above instructions.
1373 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1375 * arc-nps400-tbl.h: Add andab and orab instructions.
1377 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1379 * arc-nps400-tbl.h: Add addl-like instructions.
1381 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1383 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1385 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1387 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1390 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1392 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1394 (init_disasm): Handle new command line option "insnlength".
1395 (print_s390_disassembler_options): Mention new option in help
1397 (print_insn_s390): Use the encoded insn length when dumping
1398 unknown instructions.
1400 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1402 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1403 to the address and set as symbol address for LDS/ STS immediate operands.
1405 2016-06-07 Alan Modra <amodra@gmail.com>
1407 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1408 cpu for "vle" to e500.
1409 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1410 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1411 (PPCNONE): Delete, substitute throughout.
1412 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1413 except for major opcode 4 and 31.
1414 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1416 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1418 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1419 ARM_EXT_RAS in relevant entries.
1421 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1424 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1427 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1430 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1431 (indir_v_mode): New.
1432 Add comments for '&'.
1433 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1434 (putop): Handle '&'.
1435 (intel_operand_size): Handle indir_v_mode.
1436 (OP_E_register): Likewise.
1437 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1438 64-bit indirect call/jmp for AMD64.
1439 * i386-tbl.h: Regenerated
1441 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1443 * arc-dis.c (struct arc_operand_iterator): New structure.
1444 (find_format_from_table): All the old content from find_format,
1445 with some minor adjustments, and parameter renaming.
1446 (find_format_long_instructions): New function.
1447 (find_format): Rewritten.
1448 (arc_insn_length): Add LSB parameter.
1449 (extract_operand_value): New function.
1450 (operand_iterator_next): New function.
1451 (print_insn_arc): Use new functions to find opcode, and iterator
1453 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1454 (extract_nps_3bit_dst_short): New function.
1455 (insert_nps_3bit_src2_short): New function.
1456 (extract_nps_3bit_src2_short): New function.
1457 (insert_nps_bitop1_size): New function.
1458 (extract_nps_bitop1_size): New function.
1459 (insert_nps_bitop2_size): New function.
1460 (extract_nps_bitop2_size): New function.
1461 (insert_nps_bitop_mod4_msb): New function.
1462 (extract_nps_bitop_mod4_msb): New function.
1463 (insert_nps_bitop_mod4_lsb): New function.
1464 (extract_nps_bitop_mod4_lsb): New function.
1465 (insert_nps_bitop_dst_pos3_pos4): New function.
1466 (extract_nps_bitop_dst_pos3_pos4): New function.
1467 (insert_nps_bitop_ins_ext): New function.
1468 (extract_nps_bitop_ins_ext): New function.
1469 (arc_operands): Add new operands.
1470 (arc_long_opcodes): New global array.
1471 (arc_num_long_opcodes): New global.
1472 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1474 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1476 * nds32-asm.h: Add extern "C".
1477 * sh-opc.h: Likewise.
1479 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1481 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1482 0,b,limm to the rflt instruction.
1484 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1486 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1489 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1492 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1493 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1494 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1495 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1496 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1497 * i386-init.h: Regenerated.
1499 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1502 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1503 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1504 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1505 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1506 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1507 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1508 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1509 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1510 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1511 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1512 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1513 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1514 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1515 CpuRegMask for AVX512.
1516 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1518 (set_bitfield_from_cpu_flag_init): New function.
1519 (set_bitfield): Remove const on f. Call
1520 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1521 * i386-opc.h (CpuRegMMX): New.
1522 (CpuRegXMM): Likewise.
1523 (CpuRegYMM): Likewise.
1524 (CpuRegZMM): Likewise.
1525 (CpuRegMask): Likewise.
1526 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1528 * i386-init.h: Regenerated.
1529 * i386-tbl.h: Likewise.
1531 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1534 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1535 (opcode_modifiers): Add AMD64 and Intel64.
1536 (main): Properly verify CpuMax.
1537 * i386-opc.h (CpuAMD64): Removed.
1538 (CpuIntel64): Likewise.
1539 (CpuMax): Set to CpuNo64.
1540 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1542 (Intel64): Likewise.
1543 (i386_opcode_modifier): Add amd64 and intel64.
1544 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1546 * i386-init.h: Regenerated.
1547 * i386-tbl.h: Likewise.
1549 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1552 * i386-gen.c (main): Fail if CpuMax is incorrect.
1553 * i386-opc.h (CpuMax): Set to CpuIntel64.
1554 * i386-tbl.h: Regenerated.
1556 2016-05-27 Nick Clifton <nickc@redhat.com>
1559 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1560 (msp430dis_opcode_unsigned): New function.
1561 (msp430dis_opcode_signed): New function.
1562 (msp430_singleoperand): Use the new opcode reading functions.
1563 Only disassenmble bytes if they were successfully read.
1564 (msp430_doubleoperand): Likewise.
1565 (msp430_branchinstr): Likewise.
1566 (msp430x_callx_instr): Likewise.
1567 (print_insn_msp430): Check that it is safe to read bytes before
1568 attempting disassembly. Use the new opcode reading functions.
1570 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1572 * ppc-opc.c (CY): New define. Document it.
1573 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1575 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1577 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1578 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1579 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1580 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1582 * i386-init.h: Regenerated.
1584 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1587 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1588 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1589 * i386-init.h: Regenerated.
1591 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1593 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1594 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1595 * i386-init.h: Regenerated.
1597 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1599 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1601 (print_insn_arc): Set insn_type information.
1602 * arc-opc.c (C_CC): Add F_CLASS_COND.
1603 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1604 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1605 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1606 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1607 (brne, brne_s, jeq_s, jne_s): Likewise.
1609 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1611 * arc-tbl.h (neg): New instruction variant.
1613 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1615 * arc-dis.c (find_format, find_format, get_auxreg)
1616 (print_insn_arc): Changed.
1617 * arc-ext.h (INSERT_XOP): Likewise.
1619 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1621 * tic54x-dis.c (sprint_mmr): Adjust.
1622 * tic54x-opc.c: Likewise.
1624 2016-05-19 Alan Modra <amodra@gmail.com>
1626 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1628 2016-05-19 Alan Modra <amodra@gmail.com>
1630 * ppc-opc.c: Formatting.
1631 (NSISIGNOPT): Define.
1632 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1634 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1636 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1637 replacing references to `micromips_ase' throughout.
1638 (_print_insn_mips): Don't use file-level microMIPS annotation to
1639 determine the disassembly mode with the symbol table.
1641 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1643 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1645 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1647 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1649 * mips-opc.c (D34): New macro.
1650 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1652 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1654 * i386-dis.c (prefix_table): Add RDPID instruction.
1655 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1656 (cpu_flags): Add RDPID bitfield.
1657 * i386-opc.h (enum): Add RDPID element.
1658 (i386_cpu_flags): Add RDPID field.
1659 * i386-opc.tbl: Add RDPID instruction.
1660 * i386-init.h: Regenerate.
1661 * i386-tbl.h: Regenerate.
1663 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1665 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1666 branch type of a symbol.
1667 (print_insn): Likewise.
1669 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1671 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1672 Mainline Security Extensions instructions.
1673 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1674 Extensions instructions.
1675 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1677 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1680 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1682 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1684 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1686 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1687 (arcExtMap_genOpcode): Likewise.
1688 * arc-opc.c (arg_32bit_rc): Define new variable.
1689 (arg_32bit_u6): Likewise.
1690 (arg_32bit_limm): Likewise.
1692 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1694 * aarch64-gen.c (VERIFIER): Define.
1695 * aarch64-opc.c (VERIFIER): Define.
1696 (verify_ldpsw): Use static linkage.
1697 * aarch64-opc.h (verify_ldpsw): Remove.
1698 * aarch64-tbl.h: Use VERIFIER for verifiers.
1700 2016-04-28 Nick Clifton <nickc@redhat.com>
1703 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1704 * aarch64-opc.c (verify_ldpsw): New function.
1705 * aarch64-opc.h (verify_ldpsw): New prototype.
1706 * aarch64-tbl.h: Add initialiser for verifier field.
1707 (LDPSW): Set verifier to verify_ldpsw.
1709 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1713 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1714 smaller than address size.
1716 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1718 * alpha-dis.c: Regenerate.
1719 * crx-dis.c: Likewise.
1720 * disassemble.c: Likewise.
1721 * epiphany-opc.c: Likewise.
1722 * fr30-opc.c: Likewise.
1723 * frv-opc.c: Likewise.
1724 * ip2k-opc.c: Likewise.
1725 * iq2000-opc.c: Likewise.
1726 * lm32-opc.c: Likewise.
1727 * lm32-opinst.c: Likewise.
1728 * m32c-opc.c: Likewise.
1729 * m32r-opc.c: Likewise.
1730 * m32r-opinst.c: Likewise.
1731 * mep-opc.c: Likewise.
1732 * mt-opc.c: Likewise.
1733 * or1k-opc.c: Likewise.
1734 * or1k-opinst.c: Likewise.
1735 * tic80-opc.c: Likewise.
1736 * xc16x-opc.c: Likewise.
1737 * xstormy16-opc.c: Likewise.
1739 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1741 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1742 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1743 calcsd, and calcxd instructions.
1744 * arc-opc.c (insert_nps_bitop_size): Delete.
1745 (extract_nps_bitop_size): Delete.
1746 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1747 (extract_nps_qcmp_m3): Define.
1748 (extract_nps_qcmp_m2): Define.
1749 (extract_nps_qcmp_m1): Define.
1750 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1751 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1752 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1753 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1754 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1757 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1759 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1761 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1763 * Makefile.in: Regenerated with automake 1.11.6.
1764 * aclocal.m4: Likewise.
1766 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1768 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1770 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1771 (extract_nps_cmem_uimm16): New function.
1772 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1774 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1776 * arc-dis.c (arc_insn_length): New function.
1777 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1778 (find_format): Change insnLen parameter to unsigned.
1780 2016-04-13 Nick Clifton <nickc@redhat.com>
1783 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1784 the LD.B and LD.BU instructions.
1786 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1788 * arc-dis.c (find_format): Check for extension flags.
1789 (print_flags): New function.
1790 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1792 * arc-ext.c (arcExtMap_coreRegName): Use
1793 LAST_EXTENSION_CORE_REGISTER.
1794 (arcExtMap_coreReadWrite): Likewise.
1795 (dump_ARC_extmap): Update printing.
1796 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1797 (arc_aux_regs): Add cpu field.
1798 * arc-regs.h: Add cpu field, lower case name aux registers.
1800 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1802 * arc-tbl.h: Add rtsc, sleep with no arguments.
1804 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1806 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1808 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1809 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1810 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1811 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1812 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1813 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1814 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1815 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1816 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1817 (arc_opcode arc_opcodes): Null terminate the array.
1818 (arc_num_opcodes): Remove.
1819 * arc-ext.h (INSERT_XOP): Define.
1820 (extInstruction_t): Likewise.
1821 (arcExtMap_instName): Delete.
1822 (arcExtMap_insn): New function.
1823 (arcExtMap_genOpcode): Likewise.
1824 * arc-ext.c (ExtInstruction): Remove.
1825 (create_map): Zero initialize instruction fields.
1826 (arcExtMap_instName): Remove.
1827 (arcExtMap_insn): New function.
1828 (dump_ARC_extmap): More info while debuging.
1829 (arcExtMap_genOpcode): New function.
1830 * arc-dis.c (find_format): New function.
1831 (print_insn_arc): Use find_format.
1832 (arc_get_disassembler): Enable dump_ARC_extmap only when
1835 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1837 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1838 instruction bits out.
1840 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1842 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1843 * arc-opc.c (arc_flag_operands): Add new flags.
1844 (arc_flag_classes): Add new classes.
1846 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1848 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1850 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1852 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1853 encode1, rflt, crc16, and crc32 instructions.
1854 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1855 (arc_flag_classes): Add C_NPS_R.
1856 (insert_nps_bitop_size_2b): New function.
1857 (extract_nps_bitop_size_2b): Likewise.
1858 (insert_nps_bitop_uimm8): Likewise.
1859 (extract_nps_bitop_uimm8): Likewise.
1860 (arc_operands): Add new operand entries.
1862 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1864 * arc-regs.h: Add a new subclass field. Add double assist
1865 accumulator register values.
1866 * arc-tbl.h: Use DPA subclass to mark the double assist
1867 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1868 * arc-opc.c (RSP): Define instead of SP.
1869 (arc_aux_regs): Add the subclass field.
1871 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1873 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1875 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1877 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1880 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1882 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1883 issues. No functional changes.
1885 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1887 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1888 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1889 (RTT): Remove duplicate.
1890 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1891 (PCT_CONFIG*): Remove.
1892 (D1L, D1H, D2H, D2L): Define.
1894 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1896 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1898 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1900 * arc-tbl.h (invld07): Remove.
1901 * arc-ext-tbl.h: New file.
1902 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1903 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1905 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1907 Fix -Wstack-usage warnings.
1908 * aarch64-dis.c (print_operands): Substitute size.
1909 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1911 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1913 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1914 to get a proper diagnostic when an invalid ASR register is used.
1916 2016-03-22 Nick Clifton <nickc@redhat.com>
1918 * configure: Regenerate.
1920 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1922 * arc-nps400-tbl.h: New file.
1923 * arc-opc.c: Add top level comment.
1924 (insert_nps_3bit_dst): New function.
1925 (extract_nps_3bit_dst): New function.
1926 (insert_nps_3bit_src2): New function.
1927 (extract_nps_3bit_src2): New function.
1928 (insert_nps_bitop_size): New function.
1929 (extract_nps_bitop_size): New function.
1930 (arc_flag_operands): Add nps400 entries.
1931 (arc_flag_classes): Add nps400 entries.
1932 (arc_operands): Add nps400 entries.
1933 (arc_opcodes): Add nps400 include.
1935 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1937 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1938 the new class enum values.
1940 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1942 * arc-dis.c (print_insn_arc): Handle nps400.
1944 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1946 * arc-opc.c (BASE): Delete.
1948 2016-03-18 Nick Clifton <nickc@redhat.com>
1951 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1952 of MOV insn that aliases an ORR insn.
1954 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1956 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1958 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1960 * mcore-opc.h: Add const qualifiers.
1961 * microblaze-opc.h (struct op_code_struct): Likewise.
1962 * sh-opc.h: Likewise.
1963 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1964 (tic4x_print_op): Likewise.
1966 2016-03-02 Alan Modra <amodra@gmail.com>
1968 * or1k-desc.h: Regenerate.
1969 * fr30-ibld.c: Regenerate.
1970 * rl78-decode.c: Regenerate.
1972 2016-03-01 Nick Clifton <nickc@redhat.com>
1975 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1977 2016-02-24 Renlin Li <renlin.li@arm.com>
1979 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1980 (print_insn_coprocessor): Support fp16 instructions.
1982 2016-02-24 Renlin Li <renlin.li@arm.com>
1984 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1985 vminnm, vrint(mpna).
1987 2016-02-24 Renlin Li <renlin.li@arm.com>
1989 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1990 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1992 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1994 * i386-dis.c (print_insn): Parenthesize expression to prevent
1995 truncated addresses.
1998 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1999 Janek van Oirschot <jvanoirs@synopsys.com>
2001 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
2004 2016-02-04 Nick Clifton <nickc@redhat.com>
2007 * msp430-dis.c (print_insn_msp430): Add a special case for
2008 decoding an RRC instruction with the ZC bit set in the extension
2011 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2013 * cgen-ibld.in (insert_normal): Rework calculation of shift.
2014 * epiphany-ibld.c: Regenerate.
2015 * fr30-ibld.c: Regenerate.
2016 * frv-ibld.c: Regenerate.
2017 * ip2k-ibld.c: Regenerate.
2018 * iq2000-ibld.c: Regenerate.
2019 * lm32-ibld.c: Regenerate.
2020 * m32c-ibld.c: Regenerate.
2021 * m32r-ibld.c: Regenerate.
2022 * mep-ibld.c: Regenerate.
2023 * mt-ibld.c: Regenerate.
2024 * or1k-ibld.c: Regenerate.
2025 * xc16x-ibld.c: Regenerate.
2026 * xstormy16-ibld.c: Regenerate.
2028 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2030 * epiphany-dis.c: Regenerated from latest cpu files.
2032 2016-02-01 Michael McConville <mmcco@mykolab.com>
2034 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2037 2016-01-25 Renlin Li <renlin.li@arm.com>
2039 * arm-dis.c (mapping_symbol_for_insn): New function.
2040 (find_ifthen_state): Call mapping_symbol_for_insn().
2042 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
2044 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2045 of MSR UAO immediate operand.
2047 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2049 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2050 instruction support.
2052 2016-01-17 Alan Modra <amodra@gmail.com>
2054 * configure: Regenerate.
2056 2016-01-14 Nick Clifton <nickc@redhat.com>
2058 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2059 instructions that can support stack pointer operations.
2060 * rl78-decode.c: Regenerate.
2061 * rl78-dis.c: Fix display of stack pointer in MOVW based
2064 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2066 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2067 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2068 erxtatus_el1 and erxaddr_el1.
2070 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2072 * arm-dis.c (arm_opcodes): Add "esb".
2073 (thumb_opcodes): Likewise.
2075 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2077 * ppc-opc.c <xscmpnedp>: Delete.
2078 <xvcmpnedp>: Likewise.
2079 <xvcmpnedp.>: Likewise.
2080 <xvcmpnesp>: Likewise.
2081 <xvcmpnesp.>: Likewise.
2083 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2086 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2089 2016-01-01 Alan Modra <amodra@gmail.com>
2091 Update year range in copyright notice of all files.
2093 For older changes see ChangeLog-2015
2095 Copyright (C) 2016 Free Software Foundation, Inc.
2097 Copying and distribution of this file, with or without modification,
2098 are permitted in any medium without royalty provided the copyright
2099 notice and this notice are preserved.
2105 version-control: never