opcodes/ChangeLog

   1 2014-10-29  Nick Clifton  <nickc@redhat.com>
   2
   3         * po/de.po: Updated German translation.
   4
   5 2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
   6
   7         * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
   8         (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
   9         MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
  10         size and format initializers.  Merge 'b' arguments into 'j'.
  11         (NIOS2_NUM_OPCODES): Adjust definition.
  12         (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
  13         (nios2_opcodes): Adjust.
  14         (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
  15         * nios2-dis.c (INSNLEN): Update comment.
  16         (nios2_hash_init, nios2_hash): Delete.
  17         (OPCODE_HASH_SIZE): New.
  18         (nios2_r1_extract_opcode): New.
  19         (nios2_disassembler_state): New.
  20         (nios2_r1_disassembler_state): New.
  21         (nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
  22         (nios2_find_opcode_hash): Use state object.
  23         (bad_opcode): New.
  24         (nios2_print_insn_arg): Add op parameter.  Use it to access
  25         format.  Remove 'b' case.
  26         (nios2_disassemble): Remove special case for nop.  Remove
  27         hard-coded instruction size.
  28
  29 2014-10-21  Jan Beulich  <jbeulich@suse.com>
  30
  31         * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
  32
  33 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  34
  35         * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
  36         entries.
  37         Annotate several instructions with the HWCAP2_VIS3B hwcap.
  38
  39 2014-10-15  Tristan Gingold  <gingold@adacore.com>
  40
  41         * configure: Regenerate.
  42
  43 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
  44
  45         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
  46         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
  47         Annotate table with HWCAP2 bits.
  48         Add instructions xmontmul, xmontsqr, xmpmul.
  49         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
  50         r,i,%mwait' and `rd %mwait,r' instructions.
  51         Add rd/wr instructions for accessing the %mcdper ancillary state
  52         register.
  53         (sparc-opcodes): Add sparc5/vis4.0 instructions:
  54         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
  55         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
  56         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
  57         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
  58         fpsubus16, and faligndatai.
  59         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
  60         ancillary state register to the table.
  61         (print_insn_sparc): Handle the %mcdper ancillary state register.
  62         (print_insn_sparc): Handle new operand type '}'.
  63
  64 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
  65
  66         * i386-dis.c (MOD_0F20): Removed.
  67         (MOD_0F21): Likewise.
  68         (MOD_0F22): Likewise.
  69         (MOD_0F23): Likewise.
  70         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
  71         MOD_0F23 with "movZ".
  72         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
  73         (OP_R): Check mod/rm byte and call OP_E_register.
  74
  75 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
  76
  77         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
  78         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
  79         keyword_aridxi): Add audio ISA extension.
  80         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
  81         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
  82         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
  83         for nds32-dis.c using.
  84         (build_opcode_syntax): Remove dead code.
  85         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
  86         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
  87         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
  88         operand parser.
  89         * nds32-asm.h: Declare.
  90         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
  91         decoding by switch.
  92
  93 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
  94             Matthew Fortune  <matthew.fortune@imgtec.com>
  95
  96         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
  97         mips64r6.
  98         (parse_mips_dis_option): Allow MSA and virtualization support for
  99         mips64r6.
 100         (mips_print_arg_state): Add fields dest_regno and seen_dest.
 101         (mips_seen_register): New function.
 102         (print_insn_arg): Refactored code to use mips_seen_register
 103         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
 104         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
 105         the register rather than aborting.
 106         (print_insn_args): Add length argument.  Add code to correctly
 107         calculate the instruction address for pc relative instructions.
 108         (validate_insn_args): New static function.
 109         (print_insn_mips): Prevent jalx disassembling for r6.  Use
 110         validate_insn_args.
 111         (print_insn_micromips): Use validate_insn_args.
 112         all the arguments are valid.
 113         * mips-formats.h (PREV_CHECK): New define.
 114         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 115         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 116         (RD_pc): New define.
 117         (FS): New define.
 118         (I37): New define.
 119         (I69): New define.
 120         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 121         MIPS R6 instructions from MIPS R2 instructions.
 122
 123 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 124
 125         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
 126         (putop): Handle "%LP".
 127
 128 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 129
 130         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
 131         * aarch64-dis-2.c: Update auto-generated file.
 132
 133 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 134
 135         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
 136         (aarch64_feature_lse): New feature added.
 137         (LSE): New Added.
 138         (aarch64_opcode_table): New LSE instructions added.  Improve
 139         descriptions for ldarb/ldarh/ldar.
 140         (aarch64_opcode_table): Describe PAIRREG.
 141         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 142         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 143         (aarch64_print_operand): Recognize PAIRREG.
 144         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 145         instructions.
 146         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 147         (do_special_decoding): Recognize F_LSE_SZ.
 148         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 149
 150 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 151
 152         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 153         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 154         "sdbbp", "syscall" and "wait".
 155
 156 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 157             Maciej W. Rozycki  <macro@codesourcery.com>
 158
 159         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 160         returned if the U bit is set.
 161
 162 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 163
 164         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 165         48-bit "li" encoding.
 166
 167 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 168
 169         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 170         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 171         static functions, code was moved from...
 172         (print_insn_s390): ...here.
 173         (s390_extract_operand): Adjust comment.  Change type of first
 174         parameter from 'unsigned char *' to 'const bfd_byte *'.
 175         (union operand_value): New.
 176         (s390_extract_operand): Change return type to union operand_value.
 177         Also avoid integer overflow in sign-extension.
 178         (s390_print_insn_with_opcode): Adjust to changed return value from
 179         s390_extract_operand().  Change "%i" printf format to "%u" for
 180         unsigned values.
 181         (init_disasm): Simplify initialization of opc_index[].  This also
 182         fixes an access after the last element of s390_opcodes[].
 183         (print_insn_s390): Simplify the opcode search loop.
 184         Check architecture mask against all searched opcodes, not just the
 185         first matching one.
 186         (s390_print_insn_with_opcode): Drop function pointer dereferences
 187         without effect.
 188         (print_insn_s390): Likewise.
 189         (s390_insn_length): Simplify formula for return value.
 190         (s390_print_insn_with_opcode): Avoid special handling for the
 191         separator before the first operand.  Use new local variable
 192         'flags' in place of 'operand->flags'.
 193
 194 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 195
 196         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 197         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 198         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 199         Change assignment of 1 to priv->comment to TRUE.
 200         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 201         assignment of 0/1 with priv comment and parallel and legal
 202         to FALSE/TRUE.
 203
 204 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 205
 206         * bfin-dis.c (OUT): Define.
 207         (decode_CC2stat_0): Declare new op_names array.
 208         Replace multiple if statements with a single one.
 209
 210 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 211
 212         * bfin-dis.c (struct private): Add iw0.
 213         (_print_insn_bfin): Assign iw0 to priv.iw0.
 214         (print_insn_bfin): Drop ifetch and use priv.iw0.
 215
 216 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 217
 218         * bfin-dis.c (comment, parallel): Move from global scope ...
 219         (struct private): ... to this new struct.
 220         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 221         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 222         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 223         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 224         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 225         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 226         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 227         print_insn_bfin): Declare private struct.  Use priv's comment and
 228         parallel members.
 229
 230 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 231
 232         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 233         (_print_insn_bfin): Add check for unaligned pc.
 234
 235 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 236
 237         * bfin-dis.c (ifetch): New function.
 238         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 239         -1 when it errors.
 240
 241 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 242
 243         * micromips-opc.c (COD): Rename throughout to...
 244         (CM): New define, update to use INSN_COPROC_MOVE.
 245         (LCD): Rename throughout to...
 246         (LC): New define, update to use INSN_LOAD_COPROC.
 247         * mips-opc.c: Likewise.
 248
 249 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 250
 251         * micromips-opc.c (COD, LCD) New macros.
 252         (cfc1, ctc1): Remove FP_S attribute.
 253         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 254         (dmtc1, mtc1, mthc1): Add COD attribute.
 255         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 256
 257 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 258             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 259             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 260             Sergey Lega  <sergey.s.lega@intel.com>
 261             Anna Tikhonova  <anna.tikhonova@intel.com>
 262             Ilya Tocar  <ilya.tocar@intel.com>
 263             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 264             Ilya Verbin  <ilya.verbin@intel.com>
 265             Kirill Yukhin  <kirill.yukhin@intel.com>
 266             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 267
 268         * i386-dis-evex.h: Updated.
 269         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 270         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 271         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 272         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 273         PREFIX_EVEX_0F3A67.
 274         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 275         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 276         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 277         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 278         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 279         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 280         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 281         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 282         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 283         (prefix_table): Add entries for new instructions.
 284         (vex_len_table): Ditto.
 285         (vex_w_table): Ditto.
 286         (OP_E_memory): Update xmmq_mode handling.
 287         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 288         (cpu_flags): Add CpuAVX512DQ.
 289         * i386-init.h: Regenerared.
 290         * i386-opc.h (CpuAVX512DQ): New.
 291         (i386_cpu_flags): Add cpuavx512dq.
 292         * i386-opc.tbl: Add AVX512DQ instructions.
 293         * i386-tbl.h: Regenerate.
 294
 295 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 296             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 297             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 298             Sergey Lega  <sergey.s.lega@intel.com>
 299             Anna Tikhonova  <anna.tikhonova@intel.com>
 300             Ilya Tocar  <ilya.tocar@intel.com>
 301             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 302             Ilya Verbin  <ilya.verbin@intel.com>
 303             Kirill Yukhin  <kirill.yukhin@intel.com>
 304             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 305
 306         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 307         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 308         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 309         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 310         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 311         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 312         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 313         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 314         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 315         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 316         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 317         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 318         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 319         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 320         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 321         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 322         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 323         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 324         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 325         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 326         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 327         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 328         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 329         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 330         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 331         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 332         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 333         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 334         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 335         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 336         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 337         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 338         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 339         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 340         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 341         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 342         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 343         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 344         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 345         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 346         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 347         (prefix_table): Add entries for new instructions.
 348         (vex_table) : Ditto.
 349         (vex_len_table): Ditto.
 350         (vex_w_table): Ditto.
 351         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 352         mask_bd_mode handling.
 353         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 354         handling.
 355         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 356         handling.
 357         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 358         (OP_EX): Add dqw_swap_mode handling.
 359         (OP_VEX): Add mask_bd_mode handling.
 360         (OP_Mask): Add mask_bd_mode handling.
 361         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 362         (cpu_flags): Add CpuAVX512BW.
 363         * i386-init.h: Regenerated.
 364         * i386-opc.h (CpuAVX512BW): New.
 365         (i386_cpu_flags): Add cpuavx512bw.
 366         * i386-opc.tbl: Add AVX512BW instructions.
 367         * i386-tbl.h: Regenerate.
 368
 369 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 370             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 371             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 372             Sergey Lega  <sergey.s.lega@intel.com>
 373             Anna Tikhonova  <anna.tikhonova@intel.com>
 374             Ilya Tocar  <ilya.tocar@intel.com>
 375             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 376             Ilya Verbin  <ilya.verbin@intel.com>
 377             Kirill Yukhin  <kirill.yukhin@intel.com>
 378             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 379
 380         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 381         * i386-tbl.h: Regenerate.
 382
 383 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 384             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 385             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 386             Sergey Lega  <sergey.s.lega@intel.com>
 387             Anna Tikhonova  <anna.tikhonova@intel.com>
 388             Ilya Tocar  <ilya.tocar@intel.com>
 389             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 390             Ilya Verbin  <ilya.verbin@intel.com>
 391             Kirill Yukhin  <kirill.yukhin@intel.com>
 392             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 393
 394         * i386-dis.c (intel_operand_size): Support 128/256 length in
 395         vex_vsib_q_w_dq_mode.
 396         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 397         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 398         (cpu_flags): Add CpuAVX512VL.
 399         * i386-init.h: Regenerated.
 400         * i386-opc.h (CpuAVX512VL): New.
 401         (i386_cpu_flags): Add cpuavx512vl.
 402         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 403         * i386-opc.tbl: Add AVX512VL instructions.
 404         * i386-tbl.h: Regenerate.
 405
 406 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 407
 408         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 409         * or1k-opinst.c: Regenerate.
 410
 411 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 412
 413         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 414         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 415
 416 2014-07-04  Alan Modra  <amodra@gmail.com>
 417
 418         * configure.ac: Rename from configure.in.
 419         * Makefile.in: Regenerate.
 420         * config.in: Regenerate.
 421
 422 2014-07-04  Alan Modra  <amodra@gmail.com>
 423
 424         * configure.in: Include bfd/version.m4.
 425         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 426         (BFD_VERSION): Delete.
 427         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 428         * configure: Regenerate.
 429         * Makefile.in: Regenerate.
 430
 431 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 432             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 433             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 434             Soundararajan  <Sounderarajan.D@atmel.com>
 435
 436         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 437         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 438         machine is not avrtiny.
 439
 440 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 441
 442         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 443         constants.
 444
 445 2014-06-12  Alan Modra  <amodra@gmail.com>
 446
 447         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 448         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 449
 450 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         * i386-dis.c (fwait_prefix): New.
 453         (ckprefix): Set fwait_prefix.
 454         (print_insn): Properly print prefixes before fwait.
 455
 456 2014-06-07  Alan Modra  <amodra@gmail.com>
 457
 458         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 459
 460 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 461
 462         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 463         bfd's development.sh.
 464         * Makefile.in, configure: Regenerate.
 465
 466 2014-06-03  Nick Clifton  <nickc@redhat.com>
 467
 468         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 469         decide when extended addressing is being used.
 470
 471 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 472
 473         * sparc-opc.c (cas): Disable for LEON.
 474         (casl): Likewise.
 475
 476 2014-05-20  Alan Modra  <amodra@gmail.com>
 477
 478         * m68k-dis.c: Don't include setjmp.h.
 479
 480 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 481
 482         * i386-dis.c (ADDR16_PREFIX): Removed.
 483         (ADDR32_PREFIX): Likewise.
 484         (DATA16_PREFIX): Likewise.
 485         (DATA32_PREFIX): Likewise.
 486         (prefix_name): Updated.
 487         (print_insn): Simplify data and address size prefixes processing.
 488
 489 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 490
 491         * or1k-desc.c: Regenerated.
 492         * or1k-desc.h: Likewise.
 493         * or1k-opc.c: Likewise.
 494         * or1k-opc.h: Likewise.
 495         * or1k-opinst.c: Likewise.
 496
 497 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 498
 499         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 500         (I34): New define.
 501         (I36): New define.
 502         (I66): New define.
 503         (I68): New define.
 504         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 505         mips64r5.
 506         (parse_mips_dis_option): Update MSA and virtualization support to
 507         allow mips64r3 and mips64r5.
 508
 509 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 510
 511         * mips-opc.c (G3): Remove I4.
 512
 513 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 514
 515         PR binutils/16893
 516         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 517         (end_codep): Likewise.
 518         (mandatory_prefix): Likewise.
 519         (active_seg_prefix): Likewise.
 520         (ckprefix): Set active_seg_prefix to the active segment register
 521         prefix.
 522         (seg_prefix): Removed.
 523         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 524         for prefix index.  Ignore the index if it is invalid and the
 525         mandatory prefix isn't required.
 526         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 527         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 528         in used_prefixes here.  Don't print unused prefixes.  Check
 529         active_seg_prefix for the active segment register prefix.
 530         Restore the DFLAG bit in sizeflag if the data size prefix is
 531         unused.  Check the unused mandatory PREFIX_XXX prefixes
 532         (append_seg): Only print the segment register which gets used.
 533         (OP_E_memory): Check active_seg_prefix for the segment register
 534         prefix.
 535         (OP_OFF): Likewise.
 536         (OP_OFF64): Likewise.
 537         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 538
 539 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 540
 541         PR binutils/16886
 542         * config.in: Regenerated.
 543         * configure: Likewise.
 544         * configure.in: Check if sigsetjmp is available.
 545         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 546         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 547         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 548         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 549         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 550         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 551         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 552         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 553         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 554         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 555         (OPCODES_SIGSETJMP): Likewise.
 556         (OPCODES_SIGLONGJMP): Likewise.
 557         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 558         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 559         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 560         * xtensa-dis.c (dis_private): Replace jmp_buf with
 561         OPCODES_SIGJMP_BUF.
 562         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 563         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 564         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 565         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 566         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 567
 568 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 569
 570         PR binutils/16891
 571         * i386-dis.c (print_insn): Handle prefixes before fwait.
 572
 573 2014-04-26  Alan Modra  <amodra@gmail.com>
 574
 575         * po/POTFILES.in: Regenerate.
 576
 577 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 578
 579         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 580         to allow the MIPS XPA ASE.
 581         (parse_mips_dis_option): Process the -Mxpa option.
 582         * mips-opc.c (XPA): New define.
 583         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 584         locations of the ctc0 and cfc0 instructions.
 585
 586 2014-04-22  Christian Svensson  <blue@cmd.nu>
 587
 588         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 589         * configure.in: Likewise.
 590         * disassemble.c: Likewise.
 591         * or1k-asm.c: New file.
 592         * or1k-desc.c: New file.
 593         * or1k-desc.h: New file.
 594         * or1k-dis.c: New file.
 595         * or1k-ibld.c: New file.
 596         * or1k-opc.c: New file.
 597         * or1k-opc.h: New file.
 598         * or1k-opinst.c: New file.
 599         * Makefile.in: Regenerate.
 600         * configure: Regenerate.
 601         * openrisc-asm.c: Delete.
 602         * openrisc-desc.c: Delete.
 603         * openrisc-desc.h: Delete.
 604         * openrisc-dis.c: Delete.
 605         * openrisc-ibld.c: Delete.
 606         * openrisc-opc.c: Delete.
 607         * openrisc-opc.h: Delete.
 608         * or32-dis.c: Delete.
 609         * or32-opc.c: Delete.
 610
 611 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 612
 613         * i386-dis.c (rm_table): Add encls, enclu.
 614         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 615         (cpu_flags): Add CpuSE1.
 616         * i386-opc.h (enum): Add CpuSE1.
 617         (i386_cpu_flags): Add cpuse1.
 618         * i386-opc.tbl: Add encls, enclu.
 619         * i386-init.h: Regenerated.
 620         * i386-tbl.h: Likewise.
 621
 622 2014-04-02  Anthony Green  <green@moxielogic.com>
 623
 624         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 625         instructions, sex.b and sex.s.
 626
 627 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 628
 629         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 630         instructions.
 631
 632 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 633
 634         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 635         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 636         vscatterqps.
 637         * i386-tbl.h: Regenerate.
 638
 639 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 640
 641         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 642         %hstick_enable added.
 643
 644 2014-03-19  Nick Clifton  <nickc@redhat.com>
 645
 646         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 647         field of 3.
 648         (sbwl, ubwl, SCALE): Likewise.
 649         * rx-decode.c: Regenerate.
 650
 651 2014-03-12  Alan Modra  <amodra@gmail.com>
 652
 653         * Makefile.in: Regenerate.
 654
 655 2014-03-05  Alan Modra  <amodra@gmail.com>
 656
 657         Update copyright years.
 658
 659 2014-03-04  Heiher  <r@hev.cc>
 660
 661         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 662
 663 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 664
 665         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 666         so that they come after the Loongson extensions.
 667
 668 2014-03-03  Alan Modra  <amodra@gmail.com>
 669
 670         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 671
 672 2014-02-28  Alan Modra  <amodra@gmail.com>
 673
 674         * msp430-decode.c: Regenerate.
 675
 676 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 677
 678         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 679         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 680
 681 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 682
 683         * aarch64-opc.c (print_register_offset_address): Call
 684         get_int_reg_name to prepare the register name.
 685
 686 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 687
 688         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 689         * i386-tbl.h: Regenerate.
 690
 691 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 692
 693         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 694         (cpu_flags): Add CpuPREFETCHWT1.
 695         * i386-init.h: Regenerate.
 696         * i386-opc.h (CpuPREFETCHWT1): New.
 697         (i386_cpu_flags): Add cpuprefetchwt1.
 698         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 699         * i386-tbl.h: Regenerate.
 700
 701 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 702
 703         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 704         to CpuAVX512F.
 705         * i386-tbl.h: Regenerate.
 706
 707 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 708
 709         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 710         (output_opcode_modifier): Likewise.
 711         (output_operand_type): Likewise.
 712         * i386-init.h: Regenerated.
 713         * i386-tbl.h: Likewise.
 714
 715 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 716
 717         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 718         MOD_0FC7_REG_5.
 719         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 720         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 721         (prefix_table): Add clflusopt.
 722         (mod_table): Add xrstors, xsavec, xsaves.
 723         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 724         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 725         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 726         * i386-init.h: Regenerate.
 727         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 728         xsaves64, xsavec, xsavec64.
 729         * i386-tbl.h: Regenerate.
 730
 731 2014-02-10  Alan Modra  <amodra@gmail.com>
 732
 733         * po/POTFILES.in: Regenerate.
 734         * po/opcodes.pot: Regenerate.
 735
 736 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 737             Jan Beulich  <jbeulich@suse.com>
 738
 739         PR binutils/16490
 740         * i386-dis.c (OP_E_memory): Fix shift computation for
 741         vex_vsib_q_w_dq_mode.
 742
 743 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 744             Roland McGrath  <mcgrathr@google.com>
 745
 746         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 747         last_rex_prefix is -1.
 748
 749 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 750
 751         * i386-gen.c (process_copyright): Update copyright year to 2014.
 752
 753 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 754
 755         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 756
 757 For older changes see ChangeLog-2013
 758 \f
 759 Copyright (C) 2014 Free Software Foundation, Inc.
 760
 761 Copying and distribution of this file, with or without modification,
 762 are permitted in any medium without royalty provided the copyright
 763 notice and this notice are preserved.
 764
 765 Local Variables:
 766 mode: change-log
 767 left-margin: 8
 768 fill-column: 74
 769 version-control: never
 770 End: