1 2019-06-26 Jim Wilson <jimw@sifive.com>
4 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
5 Set info->display_endian to info->endian_code.
7 2019-06-25 Jan Beulich <jbeulich@suse.com>
9 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
10 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
11 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
12 OPERAND_TYPE_ACC64 entries.
13 * i386-init.h: Re-generate.
15 2019-06-25 Jan Beulich <jbeulich@suse.com>
17 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
19 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
21 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
23 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
24 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
26 2019-06-25 Jan Beulich <jbeulich@suse.com>
28 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
31 2019-06-25 Jan Beulich <jbeulich@suse.com>
33 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
34 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
36 * i386-opc.tbl (movnti): Add IgnoreSize.
37 * i386-tbl.h: Re-generate.
39 2019-06-25 Jan Beulich <jbeulich@suse.com>
41 * i386-opc.tbl (and): Mark Imm8S form for optimization.
42 * i386-tbl.h: Re-generate.
44 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
46 * i386-dis-evex.h: Break into ...
47 * i386-dis-evex-len.h: New file.
48 * i386-dis-evex-mod.h: Likewise.
49 * i386-dis-evex-prefix.h: Likewise.
50 * i386-dis-evex-reg.h: Likewise.
51 * i386-dis-evex-w.h: Likewise.
52 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
53 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
56 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
59 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
60 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
62 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
63 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
64 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
65 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
66 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
67 EVEX_LEN_0F385B_P_2_W_1.
68 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
69 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
70 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
71 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
72 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
73 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
74 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
75 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
76 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
77 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
79 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
82 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
83 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
84 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
85 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
86 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
87 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
88 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
89 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
90 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
91 EVEX_LEN_0F3A43_P_2_W_1.
92 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
93 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
94 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
95 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
96 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
97 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
98 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
99 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
100 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
101 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
102 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
103 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
105 2019-06-14 Nick Clifton <nickc@redhat.com>
107 * po/fr.po; Updated French translation.
109 2019-06-13 Stafford Horne <shorne@gmail.com>
111 * or1k-asm.c: Regenerated.
112 * or1k-desc.c: Regenerated.
113 * or1k-desc.h: Regenerated.
114 * or1k-dis.c: Regenerated.
115 * or1k-ibld.c: Regenerated.
116 * or1k-opc.c: Regenerated.
117 * or1k-opc.h: Regenerated.
118 * or1k-opinst.c: Regenerated.
120 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
122 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
124 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
127 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
128 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
129 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
130 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
131 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
132 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
133 EVEX_LEN_0F3A1B_P_2_W_1.
134 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
135 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
136 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
137 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
138 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
139 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
140 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
141 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
143 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
146 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
147 EVEX.vvvv when disassembling VEX and EVEX instructions.
148 (OP_VEX): Set vex.register_specifier to 0 after readding
149 vex.register_specifier.
150 (OP_Vex_2src_1): Likewise.
151 (OP_Vex_2src_2): Likewise.
152 (OP_LWP_E): Likewise.
153 (OP_EX_Vex): Don't check vex.register_specifier.
154 (OP_XMM_Vex): Likewise.
156 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
157 Lili Cui <lili.cui@intel.com>
159 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
160 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
162 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
163 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
164 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
165 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
166 (i386_cpu_flags): Add cpuavx512_vp2intersect.
167 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
168 * i386-init.h: Regenerated.
169 * i386-tbl.h: Likewise.
171 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
172 Lili Cui <lili.cui@intel.com>
174 * doc/c-i386.texi: Document enqcmd.
175 * testsuite/gas/i386/enqcmd-intel.d: New file.
176 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
177 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
178 * testsuite/gas/i386/enqcmd.d: Likewise.
179 * testsuite/gas/i386/enqcmd.s: Likewise.
180 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
181 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
182 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
183 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
184 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
185 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
186 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
189 2019-06-04 Alan Hayward <alan.hayward@arm.com>
191 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
193 2019-06-03 Alan Modra <amodra@gmail.com>
195 * ppc-dis.c (prefix_opcd_indices): Correct size.
197 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
200 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
202 * i386-tbl.h: Regenerated.
204 2019-05-24 Alan Modra <amodra@gmail.com>
206 * po/POTFILES.in: Regenerate.
208 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
209 Alan Modra <amodra@gmail.com>
211 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
212 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
213 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
214 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
215 XTOP>): Define and add entries.
216 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
217 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
218 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
219 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
221 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
222 Alan Modra <amodra@gmail.com>
224 * ppc-dis.c (ppc_opts): Add "future" entry.
225 (PREFIX_OPCD_SEGS): Define.
226 (prefix_opcd_indices): New array.
227 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
228 (lookup_prefix): New function.
229 (print_insn_powerpc): Handle 64-bit prefix instructions.
230 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
231 (PMRR, POWERXX): Define.
232 (prefix_opcodes): New instruction table.
233 (prefix_num_opcodes): New constant.
235 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
237 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
238 * configure: Regenerated.
239 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
241 (HFILES): Add bpf-desc.h and bpf-opc.h.
242 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
243 bpf-ibld.c and bpf-opc.c.
245 * Makefile.in: Regenerated.
246 * disassemble.c (ARCH_bpf): Define.
247 (disassembler): Add case for bfd_arch_bpf.
248 (disassemble_init_for_target): Likewise.
249 (enum epbf_isa_attr): Define.
250 * disassemble.h: extern print_insn_bpf.
251 * bpf-asm.c: Generated.
252 * bpf-opc.h: Likewise.
253 * bpf-opc.c: Likewise.
254 * bpf-ibld.c: Likewise.
255 * bpf-dis.c: Likewise.
256 * bpf-desc.h: Likewise.
257 * bpf-desc.c: Likewise.
259 2019-05-21 Sudakshina Das <sudi.das@arm.com>
261 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
262 and VMSR with the new operands.
264 2019-05-21 Sudakshina Das <sudi.das@arm.com>
266 * arm-dis.c (enum mve_instructions): New enum
267 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
269 (mve_opcodes): New instructions as above.
270 (is_mve_encoding_conflict): Add cases for csinc, csinv,
272 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
274 2019-05-21 Sudakshina Das <sudi.das@arm.com>
276 * arm-dis.c (emun mve_instructions): Updated for new instructions.
277 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
278 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
279 uqshl, urshrl and urshr.
280 (is_mve_okay_in_it): Add new instructions to TRUE list.
281 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
282 (print_insn_mve): Updated to accept new %j,
283 %<bitfield>m and %<bitfield>n patterns.
285 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
287 * mips-opc.c (mips_builtin_opcodes): Change source register
290 2019-05-20 Nick Clifton <nickc@redhat.com>
292 * po/fr.po: Updated French translation.
294 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
295 Michael Collison <michael.collison@arm.com>
297 * arm-dis.c (thumb32_opcodes): Add new instructions.
298 (enum mve_instructions): Likewise.
299 (enum mve_undefined): Add new reasons.
300 (is_mve_encoding_conflict): Handle new instructions.
301 (is_mve_undefined): Likewise.
302 (is_mve_unpredictable): Likewise.
303 (print_mve_undefined): Likewise.
304 (print_mve_size): Likewise.
306 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
307 Michael Collison <michael.collison@arm.com>
309 * arm-dis.c (thumb32_opcodes): Add new instructions.
310 (enum mve_instructions): Likewise.
311 (is_mve_encoding_conflict): Handle new instructions.
312 (is_mve_undefined): Likewise.
313 (is_mve_unpredictable): Likewise.
314 (print_mve_size): Likewise.
316 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
317 Michael Collison <michael.collison@arm.com>
319 * arm-dis.c (thumb32_opcodes): Add new instructions.
320 (enum mve_instructions): Likewise.
321 (is_mve_encoding_conflict): Likewise.
322 (is_mve_unpredictable): Likewise.
323 (print_mve_size): Likewise.
325 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
326 Michael Collison <michael.collison@arm.com>
328 * arm-dis.c (thumb32_opcodes): Add new instructions.
329 (enum mve_instructions): Likewise.
330 (is_mve_encoding_conflict): Handle new instructions.
331 (is_mve_undefined): Likewise.
332 (is_mve_unpredictable): Likewise.
333 (print_mve_size): Likewise.
335 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
336 Michael Collison <michael.collison@arm.com>
338 * arm-dis.c (thumb32_opcodes): Add new instructions.
339 (enum mve_instructions): Likewise.
340 (is_mve_encoding_conflict): Handle new instructions.
341 (is_mve_undefined): Likewise.
342 (is_mve_unpredictable): Likewise.
343 (print_mve_size): Likewise.
344 (print_insn_mve): Likewise.
346 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
347 Michael Collison <michael.collison@arm.com>
349 * arm-dis.c (thumb32_opcodes): Add new instructions.
350 (print_insn_thumb32): Handle new instructions.
352 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
353 Michael Collison <michael.collison@arm.com>
355 * arm-dis.c (enum mve_instructions): Add new instructions.
356 (enum mve_undefined): Add new reasons.
357 (is_mve_encoding_conflict): Handle new instructions.
358 (is_mve_undefined): Likewise.
359 (is_mve_unpredictable): Likewise.
360 (print_mve_undefined): Likewise.
361 (print_mve_size): Likewise.
362 (print_mve_shift_n): Likewise.
363 (print_insn_mve): Likewise.
365 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
366 Michael Collison <michael.collison@arm.com>
368 * arm-dis.c (enum mve_instructions): Add new instructions.
369 (is_mve_encoding_conflict): Handle new instructions.
370 (is_mve_unpredictable): Likewise.
371 (print_mve_rotate): Likewise.
372 (print_mve_size): Likewise.
373 (print_insn_mve): Likewise.
375 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
376 Michael Collison <michael.collison@arm.com>
378 * arm-dis.c (enum mve_instructions): Add new instructions.
379 (is_mve_encoding_conflict): Handle new instructions.
380 (is_mve_unpredictable): Likewise.
381 (print_mve_size): Likewise.
382 (print_insn_mve): Likewise.
384 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
385 Michael Collison <michael.collison@arm.com>
387 * arm-dis.c (enum mve_instructions): Add new instructions.
388 (enum mve_undefined): Add new reasons.
389 (is_mve_encoding_conflict): Handle new instructions.
390 (is_mve_undefined): Likewise.
391 (is_mve_unpredictable): Likewise.
392 (print_mve_undefined): Likewise.
393 (print_mve_size): Likewise.
394 (print_insn_mve): Likewise.
396 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
397 Michael Collison <michael.collison@arm.com>
399 * arm-dis.c (enum mve_instructions): Add new instructions.
400 (is_mve_encoding_conflict): Handle new instructions.
401 (is_mve_undefined): Likewise.
402 (is_mve_unpredictable): Likewise.
403 (print_mve_size): Likewise.
404 (print_insn_mve): Likewise.
406 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
407 Michael Collison <michael.collison@arm.com>
409 * arm-dis.c (enum mve_instructions): Add new instructions.
410 (enum mve_unpredictable): Add new reasons.
411 (enum mve_undefined): Likewise.
412 (is_mve_okay_in_it): Handle new isntructions.
413 (is_mve_encoding_conflict): Likewise.
414 (is_mve_undefined): Likewise.
415 (is_mve_unpredictable): Likewise.
416 (print_mve_vmov_index): Likewise.
417 (print_simd_imm8): Likewise.
418 (print_mve_undefined): Likewise.
419 (print_mve_unpredictable): Likewise.
420 (print_mve_size): Likewise.
421 (print_insn_mve): Likewise.
423 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
424 Michael Collison <michael.collison@arm.com>
426 * arm-dis.c (enum mve_instructions): Add new instructions.
427 (enum mve_unpredictable): Add new reasons.
428 (enum mve_undefined): Likewise.
429 (is_mve_encoding_conflict): Handle new instructions.
430 (is_mve_undefined): Likewise.
431 (is_mve_unpredictable): Likewise.
432 (print_mve_undefined): Likewise.
433 (print_mve_unpredictable): Likewise.
434 (print_mve_rounding_mode): Likewise.
435 (print_mve_vcvt_size): Likewise.
436 (print_mve_size): Likewise.
437 (print_insn_mve): Likewise.
439 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
440 Michael Collison <michael.collison@arm.com>
442 * arm-dis.c (enum mve_instructions): Add new instructions.
443 (enum mve_unpredictable): Add new reasons.
444 (enum mve_undefined): Likewise.
445 (is_mve_undefined): Handle new instructions.
446 (is_mve_unpredictable): Likewise.
447 (print_mve_undefined): Likewise.
448 (print_mve_unpredictable): Likewise.
449 (print_mve_size): Likewise.
450 (print_insn_mve): Likewise.
452 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
453 Michael Collison <michael.collison@arm.com>
455 * arm-dis.c (enum mve_instructions): Add new instructions.
456 (enum mve_undefined): Add new reasons.
457 (insns): Add new instructions.
458 (is_mve_encoding_conflict):
459 (print_mve_vld_str_addr): New print function.
460 (is_mve_undefined): Handle new instructions.
461 (is_mve_unpredictable): Likewise.
462 (print_mve_undefined): Likewise.
463 (print_mve_size): Likewise.
464 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
465 (print_insn_mve): Handle new operands.
467 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
468 Michael Collison <michael.collison@arm.com>
470 * arm-dis.c (enum mve_instructions): Add new instructions.
471 (enum mve_unpredictable): Add new reasons.
472 (is_mve_encoding_conflict): Handle new instructions.
473 (is_mve_unpredictable): Likewise.
474 (mve_opcodes): Add new instructions.
475 (print_mve_unpredictable): Handle new reasons.
476 (print_mve_register_blocks): New print function.
477 (print_mve_size): Handle new instructions.
478 (print_insn_mve): Likewise.
480 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
481 Michael Collison <michael.collison@arm.com>
483 * arm-dis.c (enum mve_instructions): Add new instructions.
484 (enum mve_unpredictable): Add new reasons.
485 (enum mve_undefined): Likewise.
486 (is_mve_encoding_conflict): Handle new instructions.
487 (is_mve_undefined): Likewise.
488 (is_mve_unpredictable): Likewise.
489 (coprocessor_opcodes): Move NEON VDUP from here...
490 (neon_opcodes): ... to here.
491 (mve_opcodes): Add new instructions.
492 (print_mve_undefined): Handle new reasons.
493 (print_mve_unpredictable): Likewise.
494 (print_mve_size): Handle new instructions.
495 (print_insn_neon): Handle vdup.
496 (print_insn_mve): Handle new operands.
498 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
499 Michael Collison <michael.collison@arm.com>
501 * arm-dis.c (enum mve_instructions): Add new instructions.
502 (enum mve_unpredictable): Add new values.
503 (mve_opcodes): Add new instructions.
504 (vec_condnames): New array with vector conditions.
505 (mve_predicatenames): New array with predicate suffixes.
506 (mve_vec_sizename): New array with vector sizes.
507 (enum vpt_pred_state): New enum with vector predication states.
508 (struct vpt_block): New struct type for vpt blocks.
509 (vpt_block_state): Global struct to keep track of state.
510 (mve_extract_pred_mask): New helper function.
511 (num_instructions_vpt_block): Likewise.
512 (mark_outside_vpt_block): Likewise.
513 (mark_inside_vpt_block): Likewise.
514 (invert_next_predicate_state): Likewise.
515 (update_next_predicate_state): Likewise.
516 (update_vpt_block_state): Likewise.
517 (is_vpt_instruction): Likewise.
518 (is_mve_encoding_conflict): Add entries for new instructions.
519 (is_mve_unpredictable): Likewise.
520 (print_mve_unpredictable): Handle new cases.
521 (print_instruction_predicate): Likewise.
522 (print_mve_size): New function.
523 (print_vec_condition): New function.
524 (print_insn_mve): Handle vpt blocks and new print operands.
526 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
528 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
529 8, 14 and 15 for Armv8.1-M Mainline.
531 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
532 Michael Collison <michael.collison@arm.com>
534 * arm-dis.c (enum mve_instructions): New enum.
535 (enum mve_unpredictable): Likewise.
536 (enum mve_undefined): Likewise.
537 (struct mopcode32): New struct.
538 (is_mve_okay_in_it): New function.
539 (is_mve_architecture): Likewise.
540 (arm_decode_field): Likewise.
541 (arm_decode_field_multiple): Likewise.
542 (is_mve_encoding_conflict): Likewise.
543 (is_mve_undefined): Likewise.
544 (is_mve_unpredictable): Likewise.
545 (print_mve_undefined): Likewise.
546 (print_mve_unpredictable): Likewise.
547 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
548 (print_insn_mve): New function.
549 (print_insn_thumb32): Handle MVE architecture.
550 (select_arm_features): Force thumb for Armv8.1-m Mainline.
552 2019-05-10 Nick Clifton <nickc@redhat.com>
555 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
556 end of the table prematurely.
558 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
560 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
563 2019-05-11 Alan Modra <amodra@gmail.com>
565 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
566 when -Mraw is in effect.
568 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
570 * aarch64-dis-2.c: Regenerate.
571 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
572 (OP_SVE_BBB): New variant set.
573 (OP_SVE_DDDD): New variant set.
574 (OP_SVE_HHH): New variant set.
575 (OP_SVE_HHHU): New variant set.
576 (OP_SVE_SSS): New variant set.
577 (OP_SVE_SSSU): New variant set.
578 (OP_SVE_SHH): New variant set.
579 (OP_SVE_SBBU): New variant set.
580 (OP_SVE_DSS): New variant set.
581 (OP_SVE_DHHU): New variant set.
582 (OP_SVE_VMV_HSD_BHS): New variant set.
583 (OP_SVE_VVU_HSD_BHS): New variant set.
584 (OP_SVE_VVVU_SD_BH): New variant set.
585 (OP_SVE_VVVU_BHSD): New variant set.
586 (OP_SVE_VVV_QHD_DBS): New variant set.
587 (OP_SVE_VVV_HSD_BHS): New variant set.
588 (OP_SVE_VVV_HSD_BHS2): New variant set.
589 (OP_SVE_VVV_BHS_HSD): New variant set.
590 (OP_SVE_VV_BHS_HSD): New variant set.
591 (OP_SVE_VVV_SD): New variant set.
592 (OP_SVE_VVU_BHS_HSD): New variant set.
593 (OP_SVE_VZVV_SD): New variant set.
594 (OP_SVE_VZVV_BH): New variant set.
595 (OP_SVE_VZV_SD): New variant set.
596 (aarch64_opcode_table): Add sve2 instructions.
598 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
600 * aarch64-asm-2.c: Regenerated.
601 * aarch64-dis-2.c: Regenerated.
602 * aarch64-opc-2.c: Regenerated.
603 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
604 for SVE_SHLIMM_UNPRED_22.
605 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
606 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
609 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
611 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
612 sve_size_tsz_bhs iclass encode.
613 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
614 sve_size_tsz_bhs iclass decode.
616 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
618 * aarch64-asm-2.c: Regenerated.
619 * aarch64-dis-2.c: Regenerated.
620 * aarch64-opc-2.c: Regenerated.
621 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
622 for SVE_Zm4_11_INDEX.
623 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
624 (fields): Handle SVE_i2h field.
625 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
626 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
628 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
630 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
631 sve_shift_tsz_bhsd iclass encode.
632 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
633 sve_shift_tsz_bhsd iclass decode.
635 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
637 * aarch64-asm-2.c: Regenerated.
638 * aarch64-dis-2.c: Regenerated.
639 * aarch64-opc-2.c: Regenerated.
640 * aarch64-asm.c (aarch64_ins_sve_shrimm):
641 (aarch64_encode_variant_using_iclass): Handle
642 sve_shift_tsz_hsd iclass encode.
643 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
644 sve_shift_tsz_hsd iclass decode.
645 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
646 for SVE_SHRIMM_UNPRED_22.
647 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
648 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
651 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
653 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
654 sve_size_013 iclass encode.
655 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
656 sve_size_013 iclass decode.
658 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
660 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
661 sve_size_bh iclass encode.
662 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
663 sve_size_bh iclass decode.
665 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
667 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
668 sve_size_sd2 iclass encode.
669 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
670 sve_size_sd2 iclass decode.
671 * aarch64-opc.c (fields): Handle SVE_sz2 field.
672 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
674 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
676 * aarch64-asm-2.c: Regenerated.
677 * aarch64-dis-2.c: Regenerated.
678 * aarch64-opc-2.c: Regenerated.
679 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
681 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
682 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
684 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
686 * aarch64-asm-2.c: Regenerated.
687 * aarch64-dis-2.c: Regenerated.
688 * aarch64-opc-2.c: Regenerated.
689 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
690 for SVE_Zm3_11_INDEX.
691 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
692 (fields): Handle SVE_i3l and SVE_i3h2 fields.
693 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
695 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
697 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
699 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
700 sve_size_hsd2 iclass encode.
701 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
702 sve_size_hsd2 iclass decode.
703 * aarch64-opc.c (fields): Handle SVE_size field.
704 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
706 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
708 * aarch64-asm-2.c: Regenerated.
709 * aarch64-dis-2.c: Regenerated.
710 * aarch64-opc-2.c: Regenerated.
711 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
713 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
714 (fields): Handle SVE_rot3 field.
715 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
716 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
718 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
720 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
723 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
726 (aarch64_feature_sve2, aarch64_feature_sve2aes,
727 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
728 aarch64_feature_sve2bitperm): New feature sets.
729 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
730 for feature set addresses.
731 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
732 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
734 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
735 Faraz Shahbazker <fshahbazker@wavecomp.com>
737 * mips-dis.c (mips_calculate_combination_ases): Add ISA
738 argument and set ASE_EVA_R6 appropriately.
739 (set_default_mips_dis_options): Pass ISA to above.
740 (parse_mips_dis_option): Likewise.
741 * mips-opc.c (EVAR6): New macro.
742 (mips_builtin_opcodes): Add llwpe, scwpe.
744 2019-05-01 Sudakshina Das <sudi.das@arm.com>
746 * aarch64-asm-2.c: Regenerated.
747 * aarch64-dis-2.c: Regenerated.
748 * aarch64-opc-2.c: Regenerated.
749 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
750 AARCH64_OPND_TME_UIMM16.
751 (aarch64_print_operand): Likewise.
752 * aarch64-tbl.h (QL_IMM_NIL): New.
755 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
757 2019-04-29 John Darrington <john@darrington.wattle.id.au>
759 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
761 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
762 Faraz Shahbazker <fshahbazker@wavecomp.com>
764 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
766 2019-04-24 John Darrington <john@darrington.wattle.id.au>
768 * s12z-opc.h: Add extern "C" bracketing to help
769 users who wish to use this interface in c++ code.
771 2019-04-24 John Darrington <john@darrington.wattle.id.au>
773 * s12z-opc.c (bm_decode): Handle bit map operations with the
776 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
778 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
779 specifier. Add entries for VLDR and VSTR of system registers.
780 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
781 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
782 of %J and %K format specifier.
784 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
786 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
787 Add new entries for VSCCLRM instruction.
788 (print_insn_coprocessor): Handle new %C format control code.
790 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
792 * arm-dis.c (enum isa): New enum.
793 (struct sopcode32): New structure.
794 (coprocessor_opcodes): change type of entries to struct sopcode32 and
795 set isa field of all current entries to ANY.
796 (print_insn_coprocessor): Change type of insn to struct sopcode32.
797 Only match an entry if its isa field allows the current mode.
799 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
801 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
803 (print_insn_thumb32): Add logic to print %n CLRM register list.
805 2019-04-15 Sudakshina Das <sudi.das@arm.com>
807 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
810 2019-04-15 Sudakshina Das <sudi.das@arm.com>
812 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
813 (print_insn_thumb32): Edit the switch case for %Z.
815 2019-04-15 Sudakshina Das <sudi.das@arm.com>
817 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
819 2019-04-15 Sudakshina Das <sudi.das@arm.com>
821 * arm-dis.c (thumb32_opcodes): New instruction bfl.
823 2019-04-15 Sudakshina Das <sudi.das@arm.com>
825 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
827 2019-04-15 Sudakshina Das <sudi.das@arm.com>
829 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
830 Arm register with r13 and r15 unpredictable.
831 (thumb32_opcodes): New instructions for bfx and bflx.
833 2019-04-15 Sudakshina Das <sudi.das@arm.com>
835 * arm-dis.c (thumb32_opcodes): New instructions for bf.
837 2019-04-15 Sudakshina Das <sudi.das@arm.com>
839 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
841 2019-04-15 Sudakshina Das <sudi.das@arm.com>
843 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
845 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
847 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
849 2019-04-12 John Darrington <john@darrington.wattle.id.au>
851 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
852 "optr". ("operator" is a reserved word in c++).
854 2019-04-11 Sudakshina Das <sudi.das@arm.com>
856 * aarch64-opc.c (aarch64_print_operand): Add case for
858 (verify_constraints): Likewise.
859 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
860 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
861 to accept Rt|SP as first operand.
862 (AARCH64_OPERANDS): Add new Rt_SP.
863 * aarch64-asm-2.c: Regenerated.
864 * aarch64-dis-2.c: Regenerated.
865 * aarch64-opc-2.c: Regenerated.
867 2019-04-11 Sudakshina Das <sudi.das@arm.com>
869 * aarch64-asm-2.c: Regenerated.
870 * aarch64-dis-2.c: Likewise.
871 * aarch64-opc-2.c: Likewise.
872 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
874 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
876 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
878 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
880 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
881 * i386-init.h: Regenerated.
883 2019-04-07 Alan Modra <amodra@gmail.com>
885 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
886 op_separator to control printing of spaces, comma and parens
887 rather than need_comma, need_paren and spaces vars.
889 2019-04-07 Alan Modra <amodra@gmail.com>
892 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
893 (print_insn_neon, print_insn_arm): Likewise.
895 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
897 * i386-dis-evex.h (evex_table): Updated to support BF16
899 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
900 and EVEX_W_0F3872_P_3.
901 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
902 (cpu_flags): Add bitfield for CpuAVX512_BF16.
903 * i386-opc.h (enum): Add CpuAVX512_BF16.
904 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
905 * i386-opc.tbl: Add AVX512 BF16 instructions.
906 * i386-init.h: Regenerated.
907 * i386-tbl.h: Likewise.
909 2019-04-05 Alan Modra <amodra@gmail.com>
911 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
912 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
913 to favour printing of "-" branch hint when using the "y" bit.
914 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
916 2019-04-05 Alan Modra <amodra@gmail.com>
918 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
919 opcode until first operand is output.
921 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
924 * ppc-opc.c (valid_bo_pre_v2): Add comments.
925 (valid_bo_post_v2): Add support for 'at' branch hints.
926 (insert_bo): Only error on branch on ctr.
927 (get_bo_hint_mask): New function.
928 (insert_boe): Add new 'branch_taken' formal argument. Add support
929 for inserting 'at' branch hints.
930 (extract_boe): Add new 'branch_taken' formal argument. Add support
931 for extracting 'at' branch hints.
932 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
933 (BOE): Delete operand.
934 (BOM, BOP): New operands.
936 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
937 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
938 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
939 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
940 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
941 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
942 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
943 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
944 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
945 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
946 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
947 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
948 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
949 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
950 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
951 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
952 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
953 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
954 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
955 bttarl+>: New extended mnemonics.
957 2019-03-28 Alan Modra <amodra@gmail.com>
960 * ppc-opc.c (BTF): Define.
961 (powerpc_opcodes): Use for mtfsb*.
962 * ppc-dis.c (print_insn_powerpc): Print fields with both
963 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
965 2019-03-25 Tamar Christina <tamar.christina@arm.com>
967 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
968 (mapping_symbol_for_insn): Implement new algorithm.
969 (print_insn): Remove duplicate code.
971 2019-03-25 Tamar Christina <tamar.christina@arm.com>
973 * aarch64-dis.c (print_insn_aarch64):
976 2019-03-25 Tamar Christina <tamar.christina@arm.com>
978 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
981 2019-03-25 Tamar Christina <tamar.christina@arm.com>
983 * aarch64-dis.c (last_stop_offset): New.
984 (print_insn_aarch64): Use stop_offset.
986 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
989 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
991 * i386-init.h: Regenerated.
993 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
996 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
997 vmovdqu16, vmovdqu32 and vmovdqu64.
998 * i386-tbl.h: Regenerated.
1000 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1002 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1003 from vstrszb, vstrszh, and vstrszf.
1005 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1007 * s390-opc.txt: Add instruction descriptions.
1009 2019-02-08 Jim Wilson <jimw@sifive.com>
1011 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1014 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1016 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1018 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1021 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1022 * aarch64-opc.c (verify_elem_sd): New.
1023 (fields): Add FLD_sz entr.
1024 * aarch64-tbl.h (_SIMD_INSN): New.
1025 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1026 fmulx scalar and vector by element isns.
1028 2019-02-07 Nick Clifton <nickc@redhat.com>
1030 * po/sv.po: Updated Swedish translation.
1032 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1034 * s390-mkopc.c (main): Accept arch13 as cpu string.
1035 * s390-opc.c: Add new instruction formats and instruction opcode
1037 * s390-opc.txt: Add new arch13 instructions.
1039 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1041 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1042 (aarch64_opcode): Change encoding for stg, stzg
1044 * aarch64-asm-2.c: Regenerated.
1045 * aarch64-dis-2.c: Regenerated.
1046 * aarch64-opc-2.c: Regenerated.
1048 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1050 * aarch64-asm-2.c: Regenerated.
1051 * aarch64-dis-2.c: Likewise.
1052 * aarch64-opc-2.c: Likewise.
1053 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1055 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1056 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1058 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1059 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1060 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1061 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1062 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1063 case for ldstgv_indexed.
1064 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1065 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1066 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1067 * aarch64-asm-2.c: Regenerated.
1068 * aarch64-dis-2.c: Regenerated.
1069 * aarch64-opc-2.c: Regenerated.
1071 2019-01-23 Nick Clifton <nickc@redhat.com>
1073 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1075 2019-01-21 Nick Clifton <nickc@redhat.com>
1077 * po/de.po: Updated German translation.
1078 * po/uk.po: Updated Ukranian translation.
1080 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1081 * mips-dis.c (mips_arch_choices): Fix typo in
1082 gs464, gs464e and gs264e descriptors.
1084 2019-01-19 Nick Clifton <nickc@redhat.com>
1086 * configure: Regenerate.
1087 * po/opcodes.pot: Regenerate.
1089 2018-06-24 Nick Clifton <nickc@redhat.com>
1091 2.32 branch created.
1093 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1095 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1097 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1100 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1102 * configure: Regenerate.
1104 2019-01-07 Alan Modra <amodra@gmail.com>
1106 * configure: Regenerate.
1107 * po/POTFILES.in: Regenerate.
1109 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1111 * s12z-opc.c: New file.
1112 * s12z-opc.h: New file.
1113 * s12z-dis.c: Removed all code not directly related to display
1114 of instructions. Used the interface provided by the new files
1116 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1117 * Makefile.in: Regenerate.
1118 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1119 * configure: Regenerate.
1121 2019-01-01 Alan Modra <amodra@gmail.com>
1123 Update year range in copyright notice of all files.
1125 For older changes see ChangeLog-2018
1127 Copyright (C) 2019 Free Software Foundation, Inc.
1129 Copying and distribution of this file, with or without modification,
1130 are permitted in any medium without royalty provided the copyright
1131 notice and this notice are preserved.
1137 version-control: never