opcodes/ChangeLog

   1 2017-11-23  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
   4         the 16-bit addressing case.
   5
   6 2017-11-23  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
   9         (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
  10         * i386-opc.tbl (ud1, ud2b): Add operands.
  11         (ud0): New.
  12         * i386-tbl.h: Re-generate.
  13
  14 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  15
  16         * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
  17         * i386-tbl.h: Regenerate.
  18
  19 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  20
  21         * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
  22         * i386-tbl.h: Regenerate.
  23
  24 2017-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
  25
  26         *arc-opc (insert_rhv2): Check h-regs range.
  27
  28 2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
  29
  30         * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
  31         * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
  32
  33 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  34
  35         * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
  36         and AARCH64_FEATURE_F16.
  37
  38 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  39
  40         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
  41         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
  42         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
  43         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
  44         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
  45         (ldapur, ldapursw, stlur): New.
  46         * aarch64-dis-2.c: Regenerate.
  47
  48 2017-11-16  Jan Beulich  <jbeulich@suse.com>
  49
  50         (get_valid_dis386): Never flag bad opcode when
  51         vex.register_specifier is beyond 7. Always store all four
  52         bits of it. Move 16-/32-bit override in EVEX handling after
  53         all to be overridden bits have been set.
  54         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
  55         Use rex to determine GPR register set.
  56         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
  57         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
  58
  59 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
  62         determine GPR register set.
  63
  64 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
  67         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
  68         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
  69         pass.
  70         (OP_REG_VexI4): Drop low 4 bits check.
  71
  72 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-reg.tbl (axl): Remove Acc and Byte.
  75         * i386-tbl.h: Re-generate.
  76
  77 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  78
  79         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
  80         (vex_len_table): Use VPCOM.
  81
  82 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
  85         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
  86         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
  87         vpcmpw): Move up.
  88         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
  89         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
  90         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
  91         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
  92         vpcmpnltuw): New.
  93         * i386-tbl.h: Re-generate.
  94
  95 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
  98         smov, ssca, stos, ssto, xlat): Drop Disp*.
  99         * i386-tbl.h: Re-generate.
 100
 101 2017-11-13  Jan Beulich  <jbeulich@suse.com>
 102
 103         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
 104         xsaveopt64): Add No_qSuf.
 105         * i386-tbl.h: Re-generate.
 106
 107 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 108
 109         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
 110         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
 111         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
 112         sder32_el2, vncr_el2.
 113         (aarch64_sys_reg_supported_p): Likewise.
 114         (aarch64_pstatefields): Add dit register.
 115         (aarch64_pstatefield_supported_p): Likewise.
 116         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
 117         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
 118         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
 119         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
 120         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
 121         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
 122         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
 123
 124 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 125
 126         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
 127         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
 128         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
 129         (QL_STLW, QL_STLX): New.
 130
 131 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 132
 133         * aarch64-asm.h (ins_addr_offset): New.
 134         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
 135         (aarch64_ins_addr_offset): New.
 136         * aarch64-asm-2.c: Regenerate.
 137         * aarch64-dis.h (ext_addr_offset): New.
 138         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 139         (aarch64_ext_addr_offset): New.
 140         * aarch64-dis-2.c: Regenerate.
 141         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 142         FLD_imm4_2 and FLD_SM3_imm2.
 143         * aarch64-opc.c (fields): Add FLD_imm6_2,
 144         FLD_imm4_2 and FLD_SM3_imm2.
 145         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 146         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 147         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 148         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 149         * aarch64-tbl.h
 150         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 151
 152 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 153
 154         * aarch64-tbl.h
 155         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 156         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 157         (aarch64_feature_fp_16_v8_2): New.
 158         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 159         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 160         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 161
 162 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 163
 164         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 165         (aarch64_feature_sha2, aarch64_feature_aes): New.
 166         (SHA2, AES): New.
 167         (AES_INSN, SHA2_INSN): New.
 168         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 169         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 170          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 171         Change to SHA2_INS.
 172
 173 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 174             Tamar Christina <tamar.christina@arm.com>
 175
 176         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 177         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 178
 179 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 180
 181         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 182
 183 2017-11-07  Alan Modra  <amodra@gmail.com>
 184
 185         * opintl.h: Formatting, comment fixes.
 186         (gettext, ngettext): Redefine when ENABLE_NLS.
 187         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 188         (_): Define using gettext.
 189         (textdomain, bindtextdomain): Use safer "do nothing".
 190
 191 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 192
 193         * arc-dis.c (print_hex): New variable.
 194         (parse_option): Check for hex option.
 195         (print_insn_arc): Use hexadecimal representation for short
 196         immediate values when requested.
 197         (print_arc_disassembler_options): Add hex option to the list.
 198
 199 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 200
 201         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 202         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 203         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 204         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 205         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 206         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 207         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 208         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 209         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 210         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 211         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 212         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 213         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 214         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 215         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 216         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 217         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 218         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 219         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 220         Changed opcodes.
 221         (prealloc, prefetch*): Place them before ld instruction.
 222         * arc-opc.c (skip_this_opcode): Add ARITH class.
 223
 224 2017-10-25  Alan Modra  <amodra@gmail.com>
 225
 226         PR 22348
 227         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 228         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 229         (imm4flag, size_changed): Likewise.
 230         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 231         (words, allWords, processing_argument_number): Likewise.
 232         (cst4flag, size_changed): Likewise.
 233         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 234         (crx_cst4_maps): Rename from cst4_maps.
 235         (crx_no_op_insn): Rename from no_op_insn.
 236
 237 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 238
 239         * riscv-opc.c (match_c_addi16sp) : New function.
 240         (match_c_addi4spn): New function.
 241         (match_c_lui): Don't allow 0-immediate encodings.
 242         (riscv_opcodes) <addi>: Use the above functions.
 243         <add>: Likewise.
 244         <c.addi4spn>: Likewise.
 245         <c.addi16sp>: Likewise.
 246
 247 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 248
 249         * i386-init.h: Regenerate
 250         * i386-tbl.h: Likewise
 251
 252 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 253
 254         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 255         (enum): Add EVEX_W_0F3854_P_2.
 256         * i386-dis-evex.h (evex_table): Updated.
 257         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 258         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 259         (cpu_flags): Add CpuAVX512_BITALG.
 260         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 261         (i386_cpu_flags): Add cpuavx512_bitalg..
 262         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 263         * i386-init.h: Regenerate.
 264         * i386-tbl.h: Likewise.
 265
 266 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 267
 268         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 269         * i386-dis-evex.h (evex_table): Updated.
 270         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 271         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 272         (cpu_flags): Add CpuAVX512_VNNI.
 273         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 274         (i386_cpu_flags): Add cpuavx512_vnni.
 275         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 276         * i386-init.h: Regenerate.
 277         * i386-tbl.h: Likewise.
 278
 279 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 280
 281         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 282         (enum): Remove VEX_LEN_0F3A44_P_2.
 283         (vex_len_table): Ditto.
 284         (enum): Remove VEX_W_0F3A44_P_2.
 285         (vew_w_table): Ditto.
 286         (prefix_table): Adjust instructions (see prefixes above).
 287         * i386-dis-evex.h (evex_table):
 288         Add new instructions (see prefixes above).
 289         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 290         (bitfield_cpu_flags): Ditto.
 291         * i386-opc.h (enum): Ditto.
 292         (i386_cpu_flags): Ditto.
 293         (CpuUnused): Comment out to avoid zero-width field problem.
 294         * i386-opc.tbl (vpclmulqdq): New instruction.
 295         * i386-init.h: Regenerate.
 296         * i386-tbl.h: Ditto.
 297
 298 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 299
 300         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 301         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 302         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 303         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 304         (vex_len_table): Ditto.
 305         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 306         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 307         (vew_w_table): Ditto.
 308         (prefix_table): Adjust instructions (see prefixes above).
 309         * i386-dis-evex.h (evex_table):
 310         Add new instructions (see prefixes above).
 311         * i386-gen.c (cpu_flag_init): Add VAES.
 312         (bitfield_cpu_flags): Ditto.
 313         * i386-opc.h (enum): Ditto.
 314         (i386_cpu_flags): Ditto.
 315         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 316         * i386-init.h: Regenerate.
 317         * i386-tbl.h: Ditto.
 318
 319 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 320
 321         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 322         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 323         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 324         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 325         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 326         (prefix_table): Updated (see prefixes above).
 327         (three_byte_table): Likewise.
 328         (vex_w_table): Likewise.
 329         * i386-dis-evex.h: Likewise.
 330         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 331         (cpu_flags): Add CpuGFNI.
 332         * i386-opc.h (enum): Add CpuGFNI.
 333         (i386_cpu_flags): Add cpugfni.
 334         * i386-opc.tbl: Add Intel GFNI instructions.
 335         * i386-init.h: Regenerate.
 336         * i386-tbl.h: Likewise.
 337
 338 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 339
 340         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 341         Define EXbScalar and EXwScalar for OP_EX.
 342         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 343         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 344         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 345         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 346         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 347         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 348         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 349         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 350         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 351         (OP_E_memory): Likewise.
 352         * i386-dis-evex.h: Updated.
 353         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 354         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 355         (cpu_flags): Add CpuAVX512_VBMI2.
 356         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 357         (i386_cpu_flags): Add cpuavx512_vbmi2.
 358         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 359         * i386-init.h: Regenerate.
 360         * i386-tbl.h: Likewise.
 361
 362 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 363
 364         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 365
 366 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 367
 368         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 369         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 370         K15. Add jmpix pattern.
 371
 372 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 373
 374         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 375
 376 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 377
 378         * s390-opc.c (INSTR_SI_RD): New macro.
 379         (INSTR_S_RD): Adjust example instruction.
 380         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 381         SI_RD.
 382
 383 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 384
 385         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 386         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 387         VLE multimple load/store instructions. Old e_ldm* variants are
 388         kept as aliases.
 389         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 390
 391 2017-09-27  Nick Clifton  <nickc@redhat.com>
 392
 393         PR 22179
 394         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 395         names for the fmv.x.s and fmv.s.x instructions respectively.
 396
 397 2017-09-26  do  <do@nerilex.org>
 398
 399         PR 22123
 400         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 401         be used on CPUs that have emacs support.
 402
 403 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 404
 405         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 406
 407 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 408
 409         * nds32-asm.c: Rename __BIT() to N32_BIT().
 410         * nds32-asm.h: Likewise.
 411         * nds32-dis.c: Likewise.
 412
 413 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         * i386-dis.c (last_active_prefix): Removed.
 416         (ckprefix): Don't set last_active_prefix.
 417         (NOTRACK_Fixup): Don't check last_active_prefix.
 418
 419 2017-08-31  Nick Clifton  <nickc@redhat.com>
 420
 421         * po/fr.po: Updated French translation.
 422
 423 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 424
 425         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 426         fields.
 427
 428 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 429             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 430
 431         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 432         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 433         New entries efs2 and spe2.
 434         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 435         (SPE2_OPCD_SEGS): New macro.
 436         (spe2_opcd_indices): New.
 437         (disassemble_init_powerpc): Handle SPE2 opcodes.
 438         (lookup_spe2): New function.
 439         (print_insn_powerpc): call lookup_spe2.
 440         * ppc-opc.c (insert_evuimm1_ex0): New function.
 441         (extract_evuimm1_ex0): Likewise.
 442         (insert_evuimm_lt8): Likewise.
 443         (extract_evuimm_lt8): Likewise.
 444         (insert_off_spe2): Likewise.
 445         (extract_off_spe2): Likewise.
 446         (insert_Ddd): Likewise.
 447         (extract_Ddd): Likewise.
 448         (DD): New operand.
 449         (EVUIMM_LT8): Likewise.
 450         (EVUIMM_LT16): Adjust.
 451         (MMMM): New operand.
 452         (EVUIMM_1): Likewise.
 453         (EVUIMM_1_EX0): Likewise.
 454         (EVUIMM_2): Adjust.
 455         (NNN): New operand.
 456         (VX_OFF_SPE2): Likewise.
 457         (BBB): Likewise.
 458         (DDD): Likewise.
 459         (VX_MASK_DDD): New mask.
 460         (HH): New operand.
 461         (VX_RA_CONST): New macro.
 462         (VX_RA_CONST_MASK): Likewise.
 463         (VX_RB_CONST): Likewise.
 464         (VX_RB_CONST_MASK): Likewise.
 465         (VX_OFF_SPE2_MASK): Likewise.
 466         (VX_SPE_CRFD): Likewise.
 467         (VX_SPE_CRFD_MASK VX): Likewise.
 468         (VX_SPE2_CLR): Likewise.
 469         (VX_SPE2_CLR_MASK): Likewise.
 470         (VX_SPE2_SPLATB): Likewise.
 471         (VX_SPE2_SPLATB_MASK): Likewise.
 472         (VX_SPE2_OCTET): Likewise.
 473         (VX_SPE2_OCTET_MASK): Likewise.
 474         (VX_SPE2_DDHH): Likewise.
 475         (VX_SPE2_DDHH_MASK): Likewise.
 476         (VX_SPE2_HH): Likewise.
 477         (VX_SPE2_HH_MASK): Likewise.
 478         (VX_SPE2_EVMAR): Likewise.
 479         (VX_SPE2_EVMAR_MASK): Likewise.
 480         (PPCSPE2): Likewise.
 481         (PPCEFS2): Likewise.
 482         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 483         (powerpc_macros): Map old SPE instructions have new names
 484         with the same opcodes. Add SPE2 instructions which just are
 485         mapped to SPE2.
 486         (spe2_opcodes): Add SPE2 opcodes.
 487
 488 2017-08-23  Alan Modra  <amodra@gmail.com>
 489
 490         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 491         extract functions earlier, deleting forward declarations.
 492         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 493         RA_MASK.
 494
 495 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 496
 497         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 498
 499 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 500             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 501
 502         * ppc-opc.c (insert_evuimm2_ex0): New function.
 503         (extract_evuimm2_ex0): Likewise.
 504         (insert_evuimm4_ex0): Likewise.
 505         (extract_evuimm4_ex0): Likewise.
 506         (insert_evuimm8_ex0): Likewise.
 507         (extract_evuimm8_ex0): Likewise.
 508         (insert_evuimm_lt16): Likewise.
 509         (extract_evuimm_lt16): Likewise.
 510         (insert_rD_rS_even): Likewise.
 511         (extract_rD_rS_even): Likewise.
 512         (insert_off_lsp): Likewise.
 513         (extract_off_lsp): Likewise.
 514         (RD_EVEN): New operand.
 515         (RS_EVEN): Likewise.
 516         (RSQ): Adjust.
 517         (EVUIMM_LT16): New operand.
 518         (HTM_SI): Adjust.
 519         (EVUIMM_2_EX0): New operand.
 520         (EVUIMM_4): Adjust.
 521         (EVUIMM_4_EX0): New operand.
 522         (EVUIMM_8): Adjust.
 523         (EVUIMM_8_EX0): New operand.
 524         (WS): Adjust.
 525         (VX_OFF): New operand.
 526         (VX_LSP): New macro.
 527         (VX_LSP_MASK): Likewise.
 528         (VX_LSP_OFF_MASK): Likewise.
 529         (PPC_OPCODE_LSP): Likewise.
 530         (vle_opcodes): Add LSP opcodes.
 531         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 532
 533 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 534
 535         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 536         register operands in CRC instructions.
 537         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 538         comments.
 539
 540 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 541
 542         * disassemble.c (disassembler): Mark big and mach with
 543         ATTRIBUTE_UNUSED.
 544
 545 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 546
 547         * disassemble.c (disassembler): Remove arch/mach/endian
 548         assertions.
 549
 550 2017-07-25  Nick Clifton  <nickc@redhat.com>
 551
 552         PR 21739
 553         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 554         message.
 555         (insert_r0): Likewise.
 556         (insert_r1): Likewise.
 557         (insert_r2): Likewise.
 558         (insert_r3): Likewise.
 559         (insert_sp): Likewise.
 560         (insert_gp): Likewise.
 561         (insert_pcl): Likewise.
 562         (insert_blink): Likewise.
 563         (insert_ilink1): Likewise.
 564         (insert_ilink2): Likewise.
 565         (insert_ras): Likewise.
 566         (insert_rbs): Likewise.
 567         (insert_rcs): Likewise.
 568         (insert_simm3s): Likewise.
 569         (insert_rrange): Likewise.
 570         (insert_r13el): Likewise.
 571         (insert_fpel): Likewise.
 572         (insert_blinkel): Likewise.
 573         (insert_pclel): Likewise.
 574         (insert_nps_bitop_size_2b): Likewise.
 575         (insert_nps_imm_offset): Likewise.
 576         (insert_nps_imm_entry): Likewise.
 577         (insert_nps_size_16bit): Likewise.
 578         (insert_nps_##NAME##_pos): Likewise.
 579         (insert_nps_##NAME): Likewise.
 580         (insert_nps_bitop_ins_ext): Likewise.
 581         (insert_nps_##NAME): Likewise.
 582         (insert_nps_min_hofs): Likewise.
 583         (insert_nps_##NAME): Likewise.
 584         (insert_nps_rbdouble_64): Likewise.
 585         (insert_nps_misc_imm_offset): Likewise.
 586         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 587         option description.
 588
 589 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 590             Jiong Wang  <jiong.wang@arm.com>
 591
 592         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 593         correct the print.
 594         * aarch64-dis-2.c: Regenerated.
 595
 596 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 597
 598         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 599         table.
 600
 601 2017-07-20  Nick Clifton  <nickc@redhat.com>
 602
 603         * po/de.po: Updated German translation.
 604
 605 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 606
 607         * arc-regs.h (sec_stat): New aux register.
 608         (aux_kernel_sp): Likewise.
 609         (aux_sec_u_sp): Likewise.
 610         (aux_sec_k_sp): Likewise.
 611         (sec_vecbase_build): Likewise.
 612         (nsc_table_top): Likewise.
 613         (nsc_table_base): Likewise.
 614         (ersec_stat): Likewise.
 615         (aux_sec_except): Likewise.
 616
 617 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 618
 619         * arc-opc.c (extract_uimm12_20): New function.
 620         (UIMM12_20): New operand.
 621         (SIMM3_5_S): Adjust.
 622         * arc-tbl.h (sjli): Add new instruction.
 623
 624 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 625             John Eric Martin  <John.Martin@emmicro-us.com>
 626
 627         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 628         (UIMM3_23): Adjust accordingly.
 629         * arc-regs.h: Add/correct jli_base register.
 630         * arc-tbl.h (jli_s): Likewise.
 631
 632 2017-07-18  Nick Clifton  <nickc@redhat.com>
 633
 634         PR 21775
 635         * aarch64-opc.c: Fix spelling typos.
 636         * i386-dis.c: Likewise.
 637
 638 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 639
 640         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 641         max_addr_offset and octets variables to size_t.
 642
 643 2017-07-12  Alan Modra  <amodra@gmail.com>
 644
 645         * po/da.po: Update from translationproject.org/latest/opcodes/.
 646         * po/de.po: Likewise.
 647         * po/es.po: Likewise.
 648         * po/fi.po: Likewise.
 649         * po/fr.po: Likewise.
 650         * po/id.po: Likewise.
 651         * po/it.po: Likewise.
 652         * po/nl.po: Likewise.
 653         * po/pt_BR.po: Likewise.
 654         * po/ro.po: Likewise.
 655         * po/sv.po: Likewise.
 656         * po/tr.po: Likewise.
 657         * po/uk.po: Likewise.
 658         * po/vi.po: Likewise.
 659         * po/zh_CN.po: Likewise.
 660
 661 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 662             Alan Modra  <amodra@gmail.com>
 663
 664         * cgen.sh: Mark generated files read-only.
 665         * epiphany-asm.c: Regenerate.
 666         * epiphany-desc.c: Regenerate.
 667         * epiphany-desc.h: Regenerate.
 668         * epiphany-dis.c: Regenerate.
 669         * epiphany-ibld.c: Regenerate.
 670         * epiphany-opc.c: Regenerate.
 671         * epiphany-opc.h: Regenerate.
 672         * fr30-asm.c: Regenerate.
 673         * fr30-desc.c: Regenerate.
 674         * fr30-desc.h: Regenerate.
 675         * fr30-dis.c: Regenerate.
 676         * fr30-ibld.c: Regenerate.
 677         * fr30-opc.c: Regenerate.
 678         * fr30-opc.h: Regenerate.
 679         * frv-asm.c: Regenerate.
 680         * frv-desc.c: Regenerate.
 681         * frv-desc.h: Regenerate.
 682         * frv-dis.c: Regenerate.
 683         * frv-ibld.c: Regenerate.
 684         * frv-opc.c: Regenerate.
 685         * frv-opc.h: Regenerate.
 686         * ip2k-asm.c: Regenerate.
 687         * ip2k-desc.c: Regenerate.
 688         * ip2k-desc.h: Regenerate.
 689         * ip2k-dis.c: Regenerate.
 690         * ip2k-ibld.c: Regenerate.
 691         * ip2k-opc.c: Regenerate.
 692         * ip2k-opc.h: Regenerate.
 693         * iq2000-asm.c: Regenerate.
 694         * iq2000-desc.c: Regenerate.
 695         * iq2000-desc.h: Regenerate.
 696         * iq2000-dis.c: Regenerate.
 697         * iq2000-ibld.c: Regenerate.
 698         * iq2000-opc.c: Regenerate.
 699         * iq2000-opc.h: Regenerate.
 700         * lm32-asm.c: Regenerate.
 701         * lm32-desc.c: Regenerate.
 702         * lm32-desc.h: Regenerate.
 703         * lm32-dis.c: Regenerate.
 704         * lm32-ibld.c: Regenerate.
 705         * lm32-opc.c: Regenerate.
 706         * lm32-opc.h: Regenerate.
 707         * lm32-opinst.c: Regenerate.
 708         * m32c-asm.c: Regenerate.
 709         * m32c-desc.c: Regenerate.
 710         * m32c-desc.h: Regenerate.
 711         * m32c-dis.c: Regenerate.
 712         * m32c-ibld.c: Regenerate.
 713         * m32c-opc.c: Regenerate.
 714         * m32c-opc.h: Regenerate.
 715         * m32r-asm.c: Regenerate.
 716         * m32r-desc.c: Regenerate.
 717         * m32r-desc.h: Regenerate.
 718         * m32r-dis.c: Regenerate.
 719         * m32r-ibld.c: Regenerate.
 720         * m32r-opc.c: Regenerate.
 721         * m32r-opc.h: Regenerate.
 722         * m32r-opinst.c: Regenerate.
 723         * mep-asm.c: Regenerate.
 724         * mep-desc.c: Regenerate.
 725         * mep-desc.h: Regenerate.
 726         * mep-dis.c: Regenerate.
 727         * mep-ibld.c: Regenerate.
 728         * mep-opc.c: Regenerate.
 729         * mep-opc.h: Regenerate.
 730         * mt-asm.c: Regenerate.
 731         * mt-desc.c: Regenerate.
 732         * mt-desc.h: Regenerate.
 733         * mt-dis.c: Regenerate.
 734         * mt-ibld.c: Regenerate.
 735         * mt-opc.c: Regenerate.
 736         * mt-opc.h: Regenerate.
 737         * or1k-asm.c: Regenerate.
 738         * or1k-desc.c: Regenerate.
 739         * or1k-desc.h: Regenerate.
 740         * or1k-dis.c: Regenerate.
 741         * or1k-ibld.c: Regenerate.
 742         * or1k-opc.c: Regenerate.
 743         * or1k-opc.h: Regenerate.
 744         * or1k-opinst.c: Regenerate.
 745         * xc16x-asm.c: Regenerate.
 746         * xc16x-desc.c: Regenerate.
 747         * xc16x-desc.h: Regenerate.
 748         * xc16x-dis.c: Regenerate.
 749         * xc16x-ibld.c: Regenerate.
 750         * xc16x-opc.c: Regenerate.
 751         * xc16x-opc.h: Regenerate.
 752         * xstormy16-asm.c: Regenerate.
 753         * xstormy16-desc.c: Regenerate.
 754         * xstormy16-desc.h: Regenerate.
 755         * xstormy16-dis.c: Regenerate.
 756         * xstormy16-ibld.c: Regenerate.
 757         * xstormy16-opc.c: Regenerate.
 758         * xstormy16-opc.h: Regenerate.
 759
 760 2017-07-07  Alan Modra  <amodra@gmail.com>
 761
 762         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 763         * m32c-dis.c: Regenerate.
 764         * mep-dis.c: Regenerate.
 765
 766 2017-07-05  Borislav Petkov  <bp@suse.de>
 767
 768         * i386-dis.c: Enable ModRM.reg /6 aliases.
 769
 770 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 771
 772         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 773         with vmrs and vmsr.
 774
 775 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 776
 777         * configure: Regenerate.
 778
 779 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 780
 781         * po/opcodes.pot: Regenerate.
 782
 783 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 784
 785         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 786         entries to the MSA ASE instruction block.
 787
 788 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 789             Maciej W. Rozycki  <macro@imgtec.com>
 790
 791         * micromips-opc.c (XPA, XPAVZ): New macros.
 792         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 793         "mthgc0".
 794
 795 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 796             Maciej W. Rozycki  <macro@imgtec.com>
 797
 798         * micromips-opc.c (I36): New macro.
 799         (micromips_opcodes): Add "eretnc".
 800
 801 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 802             Andrew Bennett  <andrew.bennett@imgtec.com>
 803
 804         * mips-dis.c (mips_calculate_combination_ases): Handle the
 805         ASE_XPA_VIRT flag.
 806         (parse_mips_ase_option): New function.
 807         (parse_mips_dis_option): Factor out ASE option handling to the
 808         new function.  Call `mips_calculate_combination_ases'.
 809         * mips-opc.c (XPAVZ): New macro.
 810         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 811         "mfhgc0", "mthc0" and "mthgc0".
 812
 813 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 814
 815         * mips-dis.c (mips_calculate_combination_ases): New function.
 816         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 817         calculation to the new function.
 818         (set_default_mips_dis_options): Call the new function.
 819
 820 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 821
 822         * arc-dis.c (parse_disassembler_options): Use
 823         FOR_EACH_DISASSEMBLER_OPTION.
 824
 825 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 826
 827         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 828         disassembler option strings.
 829         (parse_cpu_option): Likewise.
 830
 831 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 832
 833         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 834         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 835         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 836         (aarch64_feature_dotprod, DOT_INSN): New.
 837         (udot, sdot): New.
 838         * aarch64-dis-2.c: Regenerated.
 839
 840 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 841
 842         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 843
 844 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 845             Matthew Fortune  <matthew.fortune@imgtec.com>
 846             Andrew Bennett  <andrew.bennett@imgtec.com>
 847
 848         * mips-formats.h (INT_BIAS): New macro.
 849         (INT_ADJ): Redefine in INT_BIAS terms.
 850         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 851         (mips_print_save_restore): New function.
 852         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 853         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 854         call.
 855         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 856         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 857         OP_SAVE_RESTORE_LIST handling, factored out from here.
 858         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 859         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 860         (mips_builtin_opcodes): Add "restore" and "save" entries.
 861         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 862         (IAMR2): New macro.
 863         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 864
 865 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 866
 867         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 868         alias; do not mark SLTI instruction as an alias.
 869
 870 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         * i386-dis.c (RM_0FAE_REG_5): Removed.
 873         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 874         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 875         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 876         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 877         PREFIX_MOD_3_0F01_REG_5_RM_0.
 878         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 879         PREFIX_MOD_3_0FAE_REG_5.
 880         (mod_table): Update MOD_0FAE_REG_5.
 881         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 882         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 883         * i386-tbl.h: Regenerated.
 884
 885 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 886
 887         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 888         * i386-opc.tbl: Likewise.
 889         * i386-tbl.h: Regenerated.
 890
 891 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 892
 893         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 894         and "jmp{&|}".
 895         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 896         prefix.
 897
 898 2017-06-19  Nick Clifton  <nickc@redhat.com>
 899
 900         PR binutils/21614
 901         * score-dis.c (score_opcodes): Add sentinel.
 902
 903 2017-06-16  Alan Modra  <amodra@gmail.com>
 904
 905         * rx-decode.c: Regenerate.
 906
 907 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 908
 909         PR binutils/21594
 910         * i386-dis.c (OP_E_register): Check valid bnd register.
 911         (OP_G): Likewise.
 912
 913 2017-06-15  Nick Clifton  <nickc@redhat.com>
 914
 915         PR binutils/21595
 916         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 917         range value.
 918
 919 2017-06-15  Nick Clifton  <nickc@redhat.com>
 920
 921         PR binutils/21588
 922         * rl78-decode.opc (OP_BUF_LEN): Define.
 923         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 924         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 925         array.
 926         * rl78-decode.c: Regenerate.
 927
 928 2017-06-15  Nick Clifton  <nickc@redhat.com>
 929
 930         PR binutils/21586
 931         * bfin-dis.c (gregs): Clip index to prevent overflow.
 932         (regs): Likewise.
 933         (regs_lo): Likewise.
 934         (regs_hi): Likewise.
 935
 936 2017-06-14  Nick Clifton  <nickc@redhat.com>
 937
 938         PR binutils/21576
 939         * score7-dis.c (score_opcodes): Add sentinel.
 940
 941 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 942
 943         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 944         * arm-dis.c: Likewise.
 945         * ia64-dis.c: Likewise.
 946         * mips-dis.c: Likewise.
 947         * spu-dis.c: Likewise.
 948         * disassemble.h (print_insn_aarch64): New declaration, moved from
 949         include/dis-asm.h.
 950         (print_insn_big_arm, print_insn_big_mips): Likewise.
 951         (print_insn_i386, print_insn_ia64): Likewise.
 952         (print_insn_little_arm, print_insn_little_mips): Likewise.
 953
 954 2017-06-14  Nick Clifton  <nickc@redhat.com>
 955
 956         PR binutils/21587
 957         * rx-decode.opc: Include libiberty.h
 958         (GET_SCALE): New macro - validates access to SCALE array.
 959         (GET_PSCALE): New macro - validates access to PSCALE array.
 960         (DIs, SIs, S2Is, rx_disp): Use new macros.
 961         * rx-decode.c: Regenerate.
 962
 963 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 964
 965         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 966
 967 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 968
 969         * arc-dis.c (enforced_isa_mask): Declare.
 970         (cpu_types): Likewise.
 971         (parse_cpu_option): New function.
 972         (parse_disassembler_options): Use it.
 973         (print_insn_arc): Use enforced_isa_mask.
 974         (print_arc_disassembler_options): Document new options.
 975
 976 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 977
 978         * alpha-dis.c: Include disassemble.h, don't include
 979         dis-asm.h.
 980         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 981         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 982         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 983         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 984         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 985         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 986         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 987         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 988         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 989         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 990         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 991         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 992         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 993         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 994         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 995         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 996         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 997         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 998         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 999         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1000         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1001         * z80-dis.c, z8k-dis.c: Likewise.
1002         * disassemble.h: New file.
1003
1004 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1005
1006         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1007         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1008
1009 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1010
1011         * disassemble.c (disassembler): Add arguments a, big and mach.
1012         Use them.
1013
1014 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
1015
1016         * i386-dis.c (NOTRACK_Fixup): New.
1017         (NOTRACK): Likewise.
1018         (NOTRACK_PREFIX): Likewise.
1019         (last_active_prefix): Likewise.
1020         (reg_table): Use NOTRACK on indirect call and jmp.
1021         (ckprefix): Set last_active_prefix.
1022         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1023         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1024         * i386-opc.h (NoTrackPrefixOk): New.
1025         (i386_opcode_modifier): Add notrackprefixok.
1026         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1027         Add notrack.
1028         * i386-tbl.h: Regenerated.
1029
1030 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1031
1032         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1033         (X_IMM2): Define.
1034         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1035         bfd_mach_sparc_v9m8.
1036         (print_insn_sparc): Handle new operand types.
1037         * sparc-opc.c (MASK_M8): Define.
1038         (v6): Add MASK_M8.
1039         (v6notlet): Likewise.
1040         (v7): Likewise.
1041         (v8): Likewise.
1042         (v9): Likewise.
1043         (v9a): Likewise.
1044         (v9b): Likewise.
1045         (v9c): Likewise.
1046         (v9d): Likewise.
1047         (v9e): Likewise.
1048         (v9v): Likewise.
1049         (v9m): Likewise.
1050         (v9andleon): Likewise.
1051         (m8): Define.
1052         (HWS_VM8): Define.
1053         (HWS2_VM8): Likewise.
1054         (sparc_opcode_archs): Add entry for "m8".
1055         (sparc_opcodes): Add OSA2017 and M8 instructions
1056         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1057         fpx{ll,ra,rl}64x,
1058         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1059         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1060         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1061         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1062         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1063         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1064         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1065         ASI_CORE_SELECT_COMMIT_NHT.
1066
1067 2017-05-18  Alan Modra  <amodra@gmail.com>
1068
1069         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1070         * aarch64-dis.c: Likewise.
1071         * aarch64-gen.c: Likewise.
1072         * aarch64-opc.c: Likewise.
1073
1074 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1075             Matthew Fortune  <matthew.fortune@imgtec.com>
1076
1077         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1078         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1079         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1080         (print_insn_arg) <OP_REG28>: Add handler.
1081         (validate_insn_args) <OP_REG28>: Handle.
1082         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1083         32-bit encoding and 9-bit immediates.
1084         (print_insn_mips16): Handle MIPS16 instructions that require
1085         32-bit encoding and MFC0/MTC0 operand decoding.
1086         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1087         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1088         (RD_C0, WR_C0, E2, E2MT): New macros.
1089         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1090         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1091         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1092         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1093         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1094         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1095         instructions, "swl", "swr", "sync" and its "sync_acquire",
1096         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1097         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1098         regular/extended entries for original MIPS16 ISA revision
1099         instructions whose extended forms are subdecoded in the MIPS16e2
1100         ISA revision: "li", "sll" and "srl".
1101
1102 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1103
1104         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1105         reference in CP0 move operand decoding.
1106
1107 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1108
1109         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1110         type to hexadecimal.
1111         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1112
1113 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1114
1115         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1116         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1117         "sync_rmb" and "sync_wmb" as aliases.
1118         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1119         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1120
1121 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1122
1123         * arc-dis.c (parse_option): Update quarkse_em option..
1124         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1125         QUARKSE1.
1126         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1127
1128 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1129
1130         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1131
1132 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1133
1134         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1135         register.
1136
1137 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1138
1139         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1140         and branches and not synthetic data instructions.
1141
1142 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1143
1144         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1145
1146 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1147
1148         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1149         * arc-opc.c (insert_r13el): New function.
1150         (R13_EL): Define.
1151         * arc-tbl.h: Add new enter/leave variants.
1152
1153 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1154
1155         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1156
1157 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1158
1159         * mips-dis.c (print_mips_disassembler_options): Add
1160         `no-aliases'.
1161
1162 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1163
1164         * mips16-opc.c (AL): New macro.
1165         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1166         of "ld" and "lw" as aliases.
1167
1168 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1169
1170         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1171         arguments.
1172
1173 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1174             Alan Modra  <amodra@gmail.com>
1175
1176         * ppc-opc.c (ELEV): Define.
1177         (vle_opcodes): Add se_rfgi and e_sc.
1178         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1179         for E200Z4.
1180
1181 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1182
1183         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1184
1185 2017-04-21  Nick Clifton  <nickc@redhat.com>
1186
1187         PR binutils/21380
1188         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1189         LD3R and LD4R.
1190
1191 2017-04-13  Alan Modra  <amodra@gmail.com>
1192
1193         * epiphany-desc.c: Regenerate.
1194         * fr30-desc.c: Regenerate.
1195         * frv-desc.c: Regenerate.
1196         * ip2k-desc.c: Regenerate.
1197         * iq2000-desc.c: Regenerate.
1198         * lm32-desc.c: Regenerate.
1199         * m32c-desc.c: Regenerate.
1200         * m32r-desc.c: Regenerate.
1201         * mep-desc.c: Regenerate.
1202         * mt-desc.c: Regenerate.
1203         * or1k-desc.c: Regenerate.
1204         * xc16x-desc.c: Regenerate.
1205         * xstormy16-desc.c: Regenerate.
1206
1207 2017-04-11  Alan Modra  <amodra@gmail.com>
1208
1209         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1210         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1211         PPC_OPCODE_TMR for e6500.
1212         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1213         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1214         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1215         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1216         (PPCHTM): Define as PPC_OPCODE_POWER8.
1217         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1218
1219 2017-04-10  Alan Modra  <amodra@gmail.com>
1220
1221         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1222         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1223         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1224         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1225
1226 2017-04-09  Pip Cet  <pipcet@gmail.com>
1227
1228         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1229         appropriate floating-point precision directly.
1230
1231 2017-04-07  Alan Modra  <amodra@gmail.com>
1232
1233         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1234         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1235         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1236         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1237         vector instructions with E6500 not PPCVEC2.
1238
1239 2017-04-06  Pip Cet  <pipcet@gmail.com>
1240
1241         * Makefile.am: Add wasm32-dis.c.
1242         * configure.ac: Add wasm32-dis.c to wasm32 target.
1243         * disassemble.c: Add wasm32 disassembler code.
1244         * wasm32-dis.c: New file.
1245         * Makefile.in: Regenerate.
1246         * configure: Regenerate.
1247         * po/POTFILES.in: Regenerate.
1248         * po/opcodes.pot: Regenerate.
1249
1250 2017-04-05  Pedro Alves  <palves@redhat.com>
1251
1252         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1253         * arm-dis.c (parse_arm_disassembler_options): Constify.
1254         * ppc-dis.c (powerpc_init_dialect): Constify local.
1255         * vax-dis.c (parse_disassembler_options): Constify.
1256
1257 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1258
1259         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1260         RISCV_GP_SYMBOL.
1261
1262 2017-03-30  Pip Cet  <pipcet@gmail.com>
1263
1264         * configure.ac: Add (empty) bfd_wasm32_arch target.
1265         * configure: Regenerate
1266         * po/opcodes.pot: Regenerate.
1267
1268 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1269
1270         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1271         OSA2015.
1272         * opcodes/sparc-opc.c (asi_table): New ASIs.
1273
1274 2017-03-29  Alan Modra  <amodra@gmail.com>
1275
1276         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1277         "raw" option.
1278         (lookup_powerpc): Don't special case -1 dialect.  Handle
1279         PPC_OPCODE_RAW.
1280         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1281         lookup_powerpc call, pass it on second.
1282
1283 2017-03-27  Alan Modra  <amodra@gmail.com>
1284
1285         PR 21303
1286         * ppc-dis.c (struct ppc_mopt): Comment.
1287         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1288
1289 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1290
1291         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1292         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1293         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1294         (insert_nps_misc_imm_offset): New function.
1295         (extract_nps_misc imm_offset): New function.
1296         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1297         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1298
1299 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1300
1301         * s390-mkopc.c (main): Remove vx2 check.
1302         * s390-opc.txt: Remove vx2 instruction flags.
1303
1304 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1305
1306         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1307         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1308         (insert_nps_imm_offset): New function.
1309         (extract_nps_imm_offset): New function.
1310         (insert_nps_imm_entry): New function.
1311         (extract_nps_imm_entry): New function.
1312
1313 2017-03-17  Alan Modra  <amodra@gmail.com>
1314
1315         PR 21248
1316         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1317         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1318         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1319
1320 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1321
1322         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1323         <c.andi>: Likewise.
1324         <c.addiw> Likewise.
1325
1326 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1327
1328         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1329
1330 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1331
1332         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1333         <srl> Likewise.
1334         <srai> Likewise.
1335         <sra> Likewise.
1336
1337 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1338
1339         * i386-gen.c (opcode_modifiers): Replace S with Load.
1340         * i386-opc.h (S): Removed.
1341         (Load): New.
1342         (i386_opcode_modifier): Replace s with load.
1343         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1344         and {evex}.  Replace S with Load.
1345         * i386-tbl.h: Regenerated.
1346
1347 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1348
1349         * i386-opc.tbl: Use CpuCET on rdsspq.
1350         * i386-tbl.h: Regenerated.
1351
1352 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1353
1354         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1355         <vsx>: Do not use PPC_OPCODE_VSX3;
1356
1357 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1358
1359         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1360
1361 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1362
1363         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1364         (MOD_0F1E_PREFIX_1): Likewise.
1365         (MOD_0F38F5_PREFIX_2): Likewise.
1366         (MOD_0F38F6_PREFIX_0): Likewise.
1367         (RM_0F1E_MOD_3_REG_7): Likewise.
1368         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1369         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1370         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1371         (PREFIX_0F1E): Likewise.
1372         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1373         (PREFIX_0F38F5): Likewise.
1374         (dis386_twobyte): Use PREFIX_0F1E.
1375         (reg_table): Add REG_0F1E_MOD_3.
1376         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1377         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1378         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1379         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1380         (three_byte_table): Use PREFIX_0F38F5.
1381         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1382         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1383         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1384         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1385         PREFIX_MOD_3_0F01_REG_5_RM_2.
1386         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1387         (cpu_flags): Add CpuCET.
1388         * i386-opc.h (CpuCET): New enum.
1389         (CpuUnused): Commented out.
1390         (i386_cpu_flags): Add cpucet.
1391         * i386-opc.tbl: Add Intel CET instructions.
1392         * i386-init.h: Regenerated.
1393         * i386-tbl.h: Likewise.
1394
1395 2017-03-06  Alan Modra  <amodra@gmail.com>
1396
1397         PR 21124
1398         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1399         (extract_raq, extract_ras, extract_rbx): New functions.
1400         (powerpc_operands): Use opposite corresponding insert function.
1401         (Q_MASK): Define.
1402         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1403         register restriction.
1404
1405 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1406
1407         * disassemble.c Include "safe-ctype.h".
1408         (disassemble_init_for_target): Handle s390 init.
1409         (remove_whitespace_and_extra_commas): New function.
1410         (disassembler_options_cmp): Likewise.
1411         * arm-dis.c: Include "libiberty.h".
1412         (NUM_ELEM): Delete.
1413         (regnames): Use long disassembler style names.
1414         Add force-thumb and no-force-thumb options.
1415         (NUM_ARM_REGNAMES): Rename from this...
1416         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1417         (get_arm_regname_num_options): Delete.
1418         (set_arm_regname_option): Likewise.
1419         (get_arm_regnames): Likewise.
1420         (parse_disassembler_options): Likewise.
1421         (parse_arm_disassembler_option): Rename from this...
1422         (parse_arm_disassembler_options): ...to this.  Make static.
1423         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1424         (print_insn): Use parse_arm_disassembler_options.
1425         (disassembler_options_arm): New function.
1426         (print_arm_disassembler_options): Handle updated regnames.
1427         * ppc-dis.c: Include "libiberty.h".
1428         (ppc_opts): Add "32" and "64" entries.
1429         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1430         (powerpc_init_dialect): Add break to switch statement.
1431         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1432         (disassembler_options_powerpc): New function.
1433         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1434         Remove printing of "32" and "64".
1435         * s390-dis.c: Include "libiberty.h".
1436         (init_flag): Remove unneeded variable.
1437         (struct s390_options_t): New structure type.
1438         (options): New structure.
1439         (init_disasm): Rename from this...
1440         (disassemble_init_s390): ...to this.  Add initializations for
1441         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1442         (print_insn_s390): Delete call to init_disasm.
1443         (disassembler_options_s390): New function.
1444         (print_s390_disassembler_options): Print using information from
1445         struct 'options'.
1446         * po/opcodes.pot: Regenerate.
1447
1448 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1449
1450         * i386-dis.c (PCMPESTR_Fixup): New.
1451         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1452         (prefix_table): Use PCMPESTR_Fixup.
1453         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1454         PCMPESTR_Fixup.
1455         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1456         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1457         Split 64-bit and non-64-bit variants.
1458         * opcodes/i386-tbl.h: Re-generate.
1459
1460 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1461
1462         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1463         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1464         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1465         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1466         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1467         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1468         (OP_SVE_V_HSD): New macros.
1469         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1470         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1471         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1472         (aarch64_opcode_table): Add new SVE instructions.
1473         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1474         for rotation operands.  Add new SVE operands.
1475         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1476         (ins_sve_quad_index): Likewise.
1477         (ins_imm_rotate): Split into...
1478         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1479         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1480         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1481         functions.
1482         (aarch64_ins_sve_addr_ri_s4): New function.
1483         (aarch64_ins_sve_quad_index): Likewise.
1484         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1485         * aarch64-asm-2.c: Regenerate.
1486         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1487         (ext_sve_quad_index): Likewise.
1488         (ext_imm_rotate): Split into...
1489         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1490         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1491         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1492         functions.
1493         (aarch64_ext_sve_addr_ri_s4): New function.
1494         (aarch64_ext_sve_quad_index): Likewise.
1495         (aarch64_ext_sve_index): Allow quad indices.
1496         (do_misc_decoding): Likewise.
1497         * aarch64-dis-2.c: Regenerate.
1498         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1499         aarch64_field_kinds.
1500         (OPD_F_OD_MASK): Widen by one bit.
1501         (OPD_F_NO_ZR): Bump accordingly.
1502         (get_operand_field_width): New function.
1503         * aarch64-opc.c (fields): Add new SVE fields.
1504         (operand_general_constraint_met_p): Handle new SVE operands.
1505         (aarch64_print_operand): Likewise.
1506         * aarch64-opc-2.c: Regenerate.
1507
1508 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1509
1510         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1511         (aarch64_feature_compnum): ...this.
1512         (SIMD_V8_3): Replace with...
1513         (COMPNUM): ...this.
1514         (CNUM_INSN): New macro.
1515         (aarch64_opcode_table): Use it for the complex number instructions.
1516
1517 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1518
1519         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1520
1521 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1522
1523         Add support for associating SPARC ASIs with an architecture level.
1524         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1525         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1526         decoding of SPARC ASIs.
1527
1528 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1529
1530         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1531         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1532
1533 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1534
1535         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1536         1 (instead of to itself). Correct typo.
1537
1538 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1539
1540         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1541         pseudoinstructions.
1542
1543 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1544
1545         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1546         (aarch64_sys_reg_supported_p): Handle them.
1547
1548 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1549
1550         * arc-opc.c (UIMM6_20R): Define.
1551         (SIMM12_20): Use above.
1552         (SIMM12_20R): Define.
1553         (SIMM3_5_S): Use above.
1554         (UIMM7_A32_11R_S): Define.
1555         (UIMM7_9_S): Use above.
1556         (UIMM3_13R_S): Define.
1557         (SIMM11_A32_7_S): Use above.
1558         (SIMM9_8R): Define.
1559         (UIMM10_A32_8_S): Use above.
1560         (UIMM8_8R_S): Define.
1561         (W6): Use above.
1562         (arc_relax_opcodes): Use all above defines.
1563
1564 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1565
1566         * arc-regs.h: Distinguish some of the registers different on
1567         ARC700 and HS38 cpus.
1568
1569 2017-02-14  Alan Modra  <amodra@gmail.com>
1570
1571         PR 21118
1572         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1573         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1574
1575 2017-02-11  Stafford Horne  <shorne@gmail.com>
1576             Alan Modra  <amodra@gmail.com>
1577
1578         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1579         Use insn_bytes_value and insn_int_value directly instead.  Don't
1580         free allocated memory until function exit.
1581
1582 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1583
1584         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1585
1586 2017-02-03  Nick Clifton  <nickc@redhat.com>
1587
1588         PR 21096
1589         * aarch64-opc.c (print_register_list): Ensure that the register
1590         list index will fir into the tb buffer.
1591         (print_register_offset_address): Likewise.
1592         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1593
1594 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1595
1596         PR 21056
1597         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1598         instructions when the previous fetch packet ends with a 32-bit
1599         instruction.
1600
1601 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1602
1603         * pru-opc.c: Remove vague reference to a future GDB port.
1604
1605 2017-01-20  Nick Clifton  <nickc@redhat.com>
1606
1607         * po/ga.po: Updated Irish translation.
1608
1609 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1610
1611         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1612
1613 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1614
1615         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1616         if FETCH_DATA returns 0.
1617         (m68k_scan_mask): Likewise.
1618         (print_insn_m68k): Update code to handle -1 return value.
1619
1620 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1621
1622         * m68k-dis.c (enum print_insn_arg_error): New.
1623         (NEXTBYTE): Replace -3 with
1624         PRINT_INSN_ARG_MEMORY_ERROR.
1625         (NEXTULONG): Likewise.
1626         (NEXTSINGLE): Likewise.
1627         (NEXTDOUBLE): Likewise.
1628         (NEXTDOUBLE): Likewise.
1629         (NEXTPACKED): Likewise.
1630         (FETCH_ARG): Likewise.
1631         (FETCH_DATA): Update comments.
1632         (print_insn_arg): Update comments. Replace magic numbers with
1633         enum.
1634         (match_insn_m68k): Likewise.
1635
1636 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1637
1638         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1639         * i386-dis-evex.h (evex_table): Updated.
1640         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1641         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1642         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1643         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1644         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1645         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1646         * i386-init.h: Regenerate.
1647         * i386-tbl.h: Ditto.
1648
1649 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1650
1651         * msp430-dis.c (msp430_singleoperand): Return -1 if
1652         msp430dis_opcode_signed returns false.
1653         (msp430_doubleoperand): Likewise.
1654         (msp430_branchinstr): Return -1 if
1655         msp430dis_opcode_unsigned returns false.
1656         (msp430x_calla_instr): Likewise.
1657         (print_insn_msp430): Likewise.
1658
1659 2017-01-05  Nick Clifton  <nickc@redhat.com>
1660
1661         PR 20946
1662         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1663         could not be matched.
1664         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1665         NULL.
1666
1667 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1668
1669         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1670         (aarch64_opcode_table): Use RCPC_INSN.
1671
1672 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1673
1674         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1675         extension.
1676         * riscv-opcodes/all-opcodes: Likewise.
1677
1678 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1679
1680         * riscv-dis.c (print_insn_args): Add fall through comment.
1681
1682 2017-01-03  Nick Clifton  <nickc@redhat.com>
1683
1684         * po/sr.po: New Serbian translation.
1685         * configure.ac (ALL_LINGUAS): Add sr.
1686         * configure: Regenerate.
1687
1688 2017-01-02  Alan Modra  <amodra@gmail.com>
1689
1690         * epiphany-desc.h: Regenerate.
1691         * epiphany-opc.h: Regenerate.
1692         * fr30-desc.h: Regenerate.
1693         * fr30-opc.h: Regenerate.
1694         * frv-desc.h: Regenerate.
1695         * frv-opc.h: Regenerate.
1696         * ip2k-desc.h: Regenerate.
1697         * ip2k-opc.h: Regenerate.
1698         * iq2000-desc.h: Regenerate.
1699         * iq2000-opc.h: Regenerate.
1700         * lm32-desc.h: Regenerate.
1701         * lm32-opc.h: Regenerate.
1702         * m32c-desc.h: Regenerate.
1703         * m32c-opc.h: Regenerate.
1704         * m32r-desc.h: Regenerate.
1705         * m32r-opc.h: Regenerate.
1706         * mep-desc.h: Regenerate.
1707         * mep-opc.h: Regenerate.
1708         * mt-desc.h: Regenerate.
1709         * mt-opc.h: Regenerate.
1710         * or1k-desc.h: Regenerate.
1711         * or1k-opc.h: Regenerate.
1712         * xc16x-desc.h: Regenerate.
1713         * xc16x-opc.h: Regenerate.
1714         * xstormy16-desc.h: Regenerate.
1715         * xstormy16-opc.h: Regenerate.
1716
1717 2017-01-02  Alan Modra  <amodra@gmail.com>
1718
1719         Update year range in copyright notice of all files.
1720
1721 For older changes see ChangeLog-2016
1722 \f
1723 Copyright (C) 2017 Free Software Foundation, Inc.
1724
1725 Copying and distribution of this file, with or without modification,
1726 are permitted in any medium without royalty provided the copyright
1727 notice and this notice are preserved.
1728
1729 Local Variables:
1730 mode: change-log
1731 left-margin: 8
1732 fill-column: 74
1733 version-control: never
1734 End: