opcodes/ChangeLog

   1 2020-02-14  Jan Beulich  <jbeulich@suse.com>
   2
   3         PR gas/25438
   4         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
   5         destination for Cpu64-only variant.
   6         (movzx): Fold patterns.
   7         * i386-tbl.h: Re-generate.
   8
   9 2020-02-13  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
  12         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
  13         CPU_ANY_SSE4_FLAGS entry.
  14         * i386-init.h: Re-generate.
  15
  16 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
  19         with Unspecified, making the present one AT&T syntax only.
  20         * i386-tbl.h: Re-generate.
  21
  22 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  25         * i386-tbl.h: Re-generate.
  26
  27 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  28
  29         PR gas/24546
  30         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
  31         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
  32         Amd64 and Intel64 templates.
  33         (call, jmp): Likewise for far indirect variants. Dro
  34         Unspecified.
  35         * i386-tbl.h: Re-generate.
  36
  37 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  38
  39         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
  40         * i386-opc.h (ShortForm): Delete.
  41         (struct i386_opcode_modifier): Remove shortform field.
  42         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
  43         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
  44         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
  45         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
  46         Drop ShortForm.
  47         * i386-tbl.h: Re-generate.
  48
  49 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
  52         fucompi): Drop ShortForm from operand-less templates.
  53         * i386-tbl.h: Re-generate.
  54
  55 2020-02-11  Alan Modra  <amodra@gmail.com>
  56
  57         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
  58         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
  59         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
  60         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
  61         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
  62
  63 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
  64
  65         * arm-dis.c (print_insn_cde): Define 'V' parse character.
  66         (cde_opcodes): Add VCX* instructions.
  67
  68 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
  69             Matthew Malcomson  <matthew.malcomson@arm.com>
  70
  71         * arm-dis.c (struct cdeopcode32): New.
  72         (CDE_OPCODE): New macro.
  73         (cde_opcodes): New disassembly table.
  74         (regnames): New option to table.
  75         (cde_coprocs): New global variable.
  76         (print_insn_cde): New
  77         (print_insn_thumb32): Use print_insn_cde.
  78         (parse_arm_disassembler_options): Parse coprocN args.
  79
  80 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
  81
  82         PR gas/25516
  83         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
  84         with ISA64.
  85         * i386-opc.h (AMD64): Removed.
  86         (Intel64): Likewose.
  87         (AMD64): New.
  88         (INTEL64): Likewise.
  89         (INTEL64ONLY): Likewise.
  90         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
  91         * i386-opc.tbl (Amd64): New.
  92         (Intel64): Likewise.
  93         (Intel64Only): Likewise.
  94         Replace AMD64 with Amd64.  Update sysenter/sysenter with
  95         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
  96         * i386-tbl.h: Regenerated.
  97
  98 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
  99
 100         PR 25469
 101         * z80-dis.c: Add support for GBZ80 opcodes.
 102
 103 2020-02-04  Alan Modra  <amodra@gmail.com>
 104
 105         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 106
 107 2020-02-03  Alan Modra  <amodra@gmail.com>
 108
 109         * m32c-ibld.c: Regenerate.
 110
 111 2020-02-01  Alan Modra  <amodra@gmail.com>
 112
 113         * frv-ibld.c: Regenerate.
 114
 115 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 118         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 119         (OP_E_memory): Replace xmm_mdq_mode case label by
 120         vex_scalar_w_dq_mode one.
 121         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 122
 123 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 126         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 127         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 128         (intel_operand_size): Drop vex_w_dq_mode case label.
 129
 130 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 131
 132         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 133         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 134
 135 2020-01-30  Alan Modra  <amodra@gmail.com>
 136
 137         * m32c-ibld.c: Regenerate.
 138
 139 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 140
 141         * bpf-opc.c: Regenerate.
 142
 143 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 146         (dis386): Use them to replace C2/C3 table entries.
 147         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 148         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 149         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 150         * i386-tbl.h: Re-generate.
 151
 152 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 155         forms.
 156         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 157         DefaultSize.
 158         * i386-tbl.h: Re-generate.
 159
 160 2020-01-30  Alan Modra  <amodra@gmail.com>
 161
 162         * tic4x-dis.c (tic4x_dp): Make unsigned.
 163
 164 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 165             Jan Beulich  <jbeulich@suse.com>
 166
 167         PR binutils/25445
 168         * i386-dis.c (MOVSXD_Fixup): New function.
 169         (movsxd_mode): New enum.
 170         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 171         (intel_operand_size): Handle movsxd_mode.
 172         (OP_E_register): Likewise.
 173         (OP_G): Likewise.
 174         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 175         register on movsxd.  Add movsxd with 16-bit destination register
 176         for AMD64 and Intel64 ISAs.
 177         * i386-tbl.h: Regenerated.
 178
 179 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 180
 181         PR 25403
 182         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 183         * aarch64-asm-2.c: Regenerate
 184         * aarch64-dis-2.c: Likewise.
 185         * aarch64-opc-2.c: Likewise.
 186
 187 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-opc.tbl (sysret): Drop DefaultSize.
 190         * i386-tbl.h: Re-generate.
 191
 192 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 193
 194         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 195         Dword.
 196         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 197         * i386-tbl.h: Re-generate.
 198
 199 2020-01-20  Nick Clifton  <nickc@redhat.com>
 200
 201         * po/de.po: Updated German translation.
 202         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 203         * po/uk.po: Updated Ukranian translation.
 204
 205 2020-01-20  Alan Modra  <amodra@gmail.com>
 206
 207         * hppa-dis.c (fput_const): Remove useless cast.
 208
 209 2020-01-20  Alan Modra  <amodra@gmail.com>
 210
 211         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 212
 213 2020-01-18  Nick Clifton  <nickc@redhat.com>
 214
 215         * configure: Regenerate.
 216         * po/opcodes.pot: Regenerate.
 217
 218 2020-01-18  Nick Clifton  <nickc@redhat.com>
 219
 220         Binutils 2.34 branch created.
 221
 222 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 223
 224         * opintl.h: Fix spelling error (seperate).
 225
 226 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 227
 228         * i386-opc.tbl: Add {vex} pseudo prefix.
 229         * i386-tbl.h: Regenerated.
 230
 231 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 232
 233         PR 25376
 234         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 235         (neon_opcodes): Likewise.
 236         (select_arm_features): Make sure we enable MVE bits when selecting
 237         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 238         any architecture.
 239
 240 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 241
 242         * i386-opc.tbl: Drop stale comment from XOP section.
 243
 244 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 245
 246         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 247         (extractps): Add VexWIG to SSE2AVX forms.
 248         * i386-tbl.h: Re-generate.
 249
 250 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 251
 252         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 253         Size64 from and use VexW1 on SSE2AVX forms.
 254         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 255         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 256         * i386-tbl.h: Re-generate.
 257
 258 2020-01-15  Alan Modra  <amodra@gmail.com>
 259
 260         * tic4x-dis.c (tic4x_version): Make unsigned long.
 261         (optab, optab_special, registernames): New file scope vars.
 262         (tic4x_print_register): Set up registernames rather than
 263         malloc'd registertable.
 264         (tic4x_disassemble): Delete optable and optable_special.  Use
 265         optab and optab_special instead.  Throw away old optab,
 266         optab_special and registernames when info->mach changes.
 267
 268 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 269
 270         PR 25377
 271         * z80-dis.c (suffix): Use .db instruction to generate double
 272         prefix.
 273
 274 2020-01-14  Alan Modra  <amodra@gmail.com>
 275
 276         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 277         values to unsigned before shifting.
 278
 279 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 280
 281         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 282         flow instructions.
 283         (print_insn_thumb16, print_insn_thumb32): Likewise.
 284         (print_insn): Initialize the insn info.
 285         * i386-dis.c (print_insn): Initialize the insn info fields, and
 286         detect jumps.
 287
 288 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 289
 290         * arc-opc.c (C_NE): Make it required.
 291
 292 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 293
 294         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 295         reserved register name.
 296
 297 2020-01-13  Alan Modra  <amodra@gmail.com>
 298
 299         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 300         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 301
 302 2020-01-13  Alan Modra  <amodra@gmail.com>
 303
 304         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 305         result of wasm_read_leb128 in a uint64_t and check that bits
 306         are not lost when copying to other locals.  Use uint32_t for
 307         most locals.  Use PRId64 when printing int64_t.
 308
 309 2020-01-13  Alan Modra  <amodra@gmail.com>
 310
 311         * score-dis.c: Formatting.
 312         * score7-dis.c: Formatting.
 313
 314 2020-01-13  Alan Modra  <amodra@gmail.com>
 315
 316         * score-dis.c (print_insn_score48): Use unsigned variables for
 317         unsigned values.  Don't left shift negative values.
 318         (print_insn_score32): Likewise.
 319         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 320
 321 2020-01-13  Alan Modra  <amodra@gmail.com>
 322
 323         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 324
 325 2020-01-13  Alan Modra  <amodra@gmail.com>
 326
 327         * fr30-ibld.c: Regenerate.
 328
 329 2020-01-13  Alan Modra  <amodra@gmail.com>
 330
 331         * xgate-dis.c (print_insn): Don't left shift signed value.
 332         (ripBits): Formatting, use 1u.
 333
 334 2020-01-10  Alan Modra  <amodra@gmail.com>
 335
 336         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 337         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 338
 339 2020-01-10  Alan Modra  <amodra@gmail.com>
 340
 341         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 342         and XRREG value earlier to avoid a shift with negative exponent.
 343         * m10200-dis.c (disassemble): Similarly.
 344
 345 2020-01-09  Nick Clifton  <nickc@redhat.com>
 346
 347         PR 25224
 348         * z80-dis.c (ld_ii_ii): Use correct cast.
 349
 350 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 351
 352         PR 25224
 353         * z80-dis.c (ld_ii_ii): Use character constant when checking
 354         opcode byte value.
 355
 356 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 357
 358         * i386-dis.c (SEP_Fixup): New.
 359         (SEP): Define.
 360         (dis386_twobyte): Use it for sysenter/sysexit.
 361         (enum x86_64_isa): Change amd64 enumerator to value 1.
 362         (OP_J): Compare isa64 against intel64 instead of amd64.
 363         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 364         forms.
 365         * i386-tbl.h: Re-generate.
 366
 367 2020-01-08  Alan Modra  <amodra@gmail.com>
 368
 369         * z8k-dis.c: Include libiberty.h
 370         (instr_data_s): Make max_fetched unsigned.
 371         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 372         Don't exceed byte_info bounds.
 373         (output_instr): Make num_bytes unsigned.
 374         (unpack_instr): Likewise for nibl_count and loop.
 375         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 376         idx unsigned.
 377         * z8k-opc.h: Regenerate.
 378
 379 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 380
 381         * arc-tbl.h (llock): Use 'LLOCK' as class.
 382         (llockd): Likewise.
 383         (scond): Use 'SCOND' as class.
 384         (scondd): Likewise.
 385         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 386         (scondd): Likewise.
 387
 388 2020-01-06  Alan Modra  <amodra@gmail.com>
 389
 390         * m32c-ibld.c: Regenerate.
 391
 392 2020-01-06  Alan Modra  <amodra@gmail.com>
 393
 394         PR 25344
 395         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 396         Peek at next byte to prevent recursion on repeated prefix bytes.
 397         Ensure uninitialised "mybuf" is not accessed.
 398         (print_insn_z80): Don't zero n_fetch and n_used here,..
 399         (print_insn_z80_buf): ..do it here instead.
 400
 401 2020-01-04  Alan Modra  <amodra@gmail.com>
 402
 403         * m32r-ibld.c: Regenerate.
 404
 405 2020-01-04  Alan Modra  <amodra@gmail.com>
 406
 407         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 408
 409 2020-01-04  Alan Modra  <amodra@gmail.com>
 410
 411         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 412
 413 2020-01-04  Alan Modra  <amodra@gmail.com>
 414
 415         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 416
 417 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 418
 419         * aarch64-tbl.h (aarch64_opcode_table): Use
 420         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 421
 422 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 423
 424         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 425         forms of SUDOT and USDOT.
 426
 427 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 428
 429         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 430         uzip{1,2}.
 431         * opcodes/aarch64-dis-2.c: Re-generate.
 432
 433 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 434
 435         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 436         FMMLA encoding.
 437         * opcodes/aarch64-dis-2.c: Re-generate.
 438
 439 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 440
 441         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 442
 443 2020-01-01  Alan Modra  <amodra@gmail.com>
 444
 445         Update year range in copyright notice of all files.
 446
 447 For older changes see ChangeLog-2019
 448 \f
 449 Copyright (C) 2020 Free Software Foundation, Inc.
 450
 451 Copying and distribution of this file, with or without modification,
 452 are permitted in any medium without royalty provided the copyright
 453 notice and this notice are preserved.
 454
 455 Local Variables:
 456 mode: change-log
 457 left-margin: 8
 458 fill-column: 74
 459 version-control: never
 460 End: