1 2019-12-26 Alan Modra <amodra@gmail.com>
3 * v850-dis.c (disassemble): Avoid signed overflow. Don't use
4 long vars when unsigned int will do.
6 2019-12-24 Alan Modra <amodra@gmail.com>
8 * arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
10 2019-12-23 Jan Beulich <jbeulich@suse.com>
12 * ppc-dis.c (print_insn_powerpc): Rename local variable "spaces"
14 * ppc-opc.c (D34, SI34, NSI34): Use UINT64_C().
16 2019-12-23 Alan Modra <amodra@gmail.com>
18 * score-dis.c (print_insn_score32): Avoid signed overflow.
19 (print_insn_score48): Likewise. Don't cast to int when printing
22 2019-12-23 Alan Modra <amodra@gmail.com>
24 * iq2000-ibld.c: Regenerate.
26 2019-12-23 Alan Modra <amodra@gmail.com>
28 * d30v-dis.c (extract_value): Make num param a uint64_t, constify
29 oper. Use unsigned vars.
30 (print_insn): Make num var uint64_t. Constify oper and remove now
31 unnecessary casts on extract_value calls.
32 (print_insn_d30v): Use unsigned vars. Adjust printf formats.
34 2019-12-23 Alan Modra <amodra@gmail.com>
36 * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
37 Catch value overflow. Sign extend only on terminating byte.
39 2019-12-20 Alan Modra <amodra@gmail.com>
42 * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
43 and MOVY_NOPX insns. For invalid cases include 0xf000 in the word
44 printed. Print .word in more cases.
46 2019-12-20 Alan Modra <amodra@gmail.com>
48 * or1k-ibld.c: Regenerate.
50 2019-12-20 Alan Modra <amodra@gmail.com>
52 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
55 2019-12-20 Alan Modra <amodra@gmail.com>
57 * m68hc11-dis.c (read_memory): Delete forward decls.
58 (print_indexed_operand, print_insn): Likewise.
59 (print_indexed_operand): Formatting. Don't rely on short being
60 exactly 16 bits, make sign extension explicit.
61 (print_insn): Likewise. Avoid signed overflow.
63 2019-12-19 Alan Modra <amodra@gmail.com>
65 * vax-dis.c (print_insn_mode): Stop index mode recursion.
67 2019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
70 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
72 * microblaze-opc.h (opcodes): Adjust to suit.
74 2019-12-18 Alan Modra <amodra@gmail.com>
76 * alpha-opc.c (OP): Avoid signed overflow.
77 * arm-dis.c (print_insn): Likewise.
78 * mcore-dis.c (print_insn_mcore): Likewise.
79 * pj-dis.c (get_int): Likewise.
80 * ppc-opc.c (EBD15, EBD15BI): Likewise.
81 * score7-dis.c (s7_print_insn): Likewise.
82 * tic30-dis.c (print_insn_tic30): Likewise.
83 * v850-opc.c (insert_SELID): Likewise.
84 * vax-dis.c (print_insn_vax): Likewise.
85 * arc-ext.c (create_map): Likewise.
86 (struct ExtAuxRegister): Make "address" field unsigned int.
87 (arcExtMap_auxRegName): Pass unsigned address.
88 (dump_ARC_extmap): Adjust.
89 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
91 2019-12-17 Alan Modra <amodra@gmail.com>
93 * visium-dis.c (print_insn_visium): Avoid signed overflow.
95 2019-12-17 Alan Modra <amodra@gmail.com>
97 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
98 (value_fit_unsigned_field_p): Likewise.
99 (aarch64_wide_constant_p): Likewise.
100 (operand_general_constraint_met_p): Likewise.
101 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
103 2019-12-17 Alan Modra <amodra@gmail.com>
105 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
106 (print_insn_nds32): Use uint64_t for "given" and "given1".
108 2019-12-17 Alan Modra <amodra@gmail.com>
110 * tic80-dis.c: Delete file.
111 * tic80-opc.c: Delete file.
112 * disassemble.c: Remove tic80 support.
113 * disassemble.h: Likewise.
114 * Makefile.am: Likewise.
115 * configure.ac: Likewise.
116 * Makefile.in: Regenerate.
117 * configure: Regenerate.
118 * po/POTFILES.in: Regenerate.
120 2019-12-17 Alan Modra <amodra@gmail.com>
122 * bpf-ibld.c: Regenerate.
124 2019-12-16 Alan Modra <amodra@gmail.com>
126 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
128 (aarch64_ext_imm): Avoid signed overflow.
130 2019-12-16 Alan Modra <amodra@gmail.com>
132 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
134 2019-12-16 Alan Modra <amodra@gmail.com>
136 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
138 2019-12-16 Alan Modra <amodra@gmail.com>
140 * xstormy16-ibld.c: Regenerate.
142 2019-12-16 Alan Modra <amodra@gmail.com>
144 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
145 value adjustment so that it doesn't affect reg field too.
147 2019-12-16 Alan Modra <amodra@gmail.com>
149 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
150 (get_number_of_operands, getargtype, getbits, getregname),
151 (getcopregname, getprocregname, gettrapstring, getcinvstring),
152 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
153 (powerof2, match_opcode, make_instruction, print_arguments),
154 (print_arg): Delete forward declarations, moving static to..
155 (getregname, getcopregname, getregliststring): ..these definitions.
156 (build_mask): Return unsigned int mask.
157 (match_opcode): Use unsigned int vars.
159 2019-12-16 Alan Modra <amodra@gmail.com>
161 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
163 2019-12-16 Alan Modra <amodra@gmail.com>
165 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
166 (struct objdump_disasm_info): Delete.
167 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
168 N32_IMMS to unsigned before shifting left.
170 2019-12-16 Alan Modra <amodra@gmail.com>
172 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
173 (print_insn_moxie): Remove unnecessary cast.
175 2019-12-12 Alan Modra <amodra@gmail.com>
177 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
180 2019-12-11 Alan Modra <amodra@gmail.com>
182 * arc-dis.c (BITS): Don't truncate high bits with shifts.
183 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
184 * tic54x-dis.c (print_instruction): Likewise.
185 * tilegx-opc.c (parse_insn_tilegx): Likewise.
186 * tilepro-opc.c (parse_insn_tilepro): Likewise.
187 * visium-dis.c (disassem_class0): Likewise.
188 * pdp11-dis.c (sign_extend): Likewise.
190 * epiphany-ibld.c: Regenerate.
191 * lm32-ibld.c: Regenerate.
192 * m32c-ibld.c: Regenerate.
194 2019-12-11 Alan Modra <amodra@gmail.com>
196 * ns32k-dis.c (sign_extend): Correct last patch.
198 2019-12-11 Alan Modra <amodra@gmail.com>
200 * vax-dis.c (NEXTLONG): Avoid signed overflow.
202 2019-12-11 Alan Modra <amodra@gmail.com>
204 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
205 sign extend using shifts.
207 2019-12-11 Alan Modra <amodra@gmail.com>
209 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
211 2019-12-11 Alan Modra <amodra@gmail.com>
213 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
214 on NULL registertable entry.
215 (tic4x_hash_opcode): Use unsigned arithmetic.
217 2019-12-11 Alan Modra <amodra@gmail.com>
219 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
221 2019-12-11 Alan Modra <amodra@gmail.com>
223 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
224 (bit_extract_simple, sign_extend): Likewise.
226 2019-12-11 Alan Modra <amodra@gmail.com>
228 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
230 2019-12-11 Alan Modra <amodra@gmail.com>
232 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
234 2019-12-11 Alan Modra <amodra@gmail.com>
236 * m68k-dis.c (COERCE32): Cast value first.
237 (NEXTLONG, NEXTULONG): Avoid signed overflow.
239 2019-12-11 Alan Modra <amodra@gmail.com>
241 * h8300-dis.c (extract_immediate): Avoid signed overflow.
242 (bfd_h8_disassemble): Likewise.
244 2019-12-11 Alan Modra <amodra@gmail.com>
246 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
247 past end of operands array.
249 2019-12-11 Alan Modra <amodra@gmail.com>
251 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
252 overflow when collecting bytes of a number.
254 2019-12-11 Alan Modra <amodra@gmail.com>
256 * cris-dis.c (print_with_operands): Avoid signed integer
257 overflow when collecting bytes of a 32-bit integer.
259 2019-12-11 Alan Modra <amodra@gmail.com>
261 * cr16-dis.c (EXTRACT, SBM): Rewrite.
262 (cr16_match_opcode): Delete duplicate bcond test.
264 2019-12-11 Alan Modra <amodra@gmail.com>
266 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
268 (MASKBITS, SIGNEXTEND): Rewrite.
269 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
270 unsigned arithmetic, instead assign result of SIGNEXTEND back
272 (fmtconst_val): Use 1u in shift expression.
274 2019-12-11 Alan Modra <amodra@gmail.com>
276 * arc-dis.c (find_format_from_table): Use ull constant when
277 shifting by up to 32.
279 2019-12-11 Alan Modra <amodra@gmail.com>
282 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
283 false when field is zero for sve_size_tsz_bhs.
285 2019-12-11 Alan Modra <amodra@gmail.com>
287 * epiphany-ibld.c: Regenerate.
289 2019-12-10 Alan Modra <amodra@gmail.com>
292 * disassemble.c (disassemble_free_target): New function.
294 2019-12-10 Alan Modra <amodra@gmail.com>
296 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
297 * disassemble.c (disassemble_init_for_target): Likewise.
298 * bpf-dis.c: Regenerate.
299 * epiphany-dis.c: Regenerate.
300 * fr30-dis.c: Regenerate.
301 * frv-dis.c: Regenerate.
302 * ip2k-dis.c: Regenerate.
303 * iq2000-dis.c: Regenerate.
304 * lm32-dis.c: Regenerate.
305 * m32c-dis.c: Regenerate.
306 * m32r-dis.c: Regenerate.
307 * mep-dis.c: Regenerate.
308 * mt-dis.c: Regenerate.
309 * or1k-dis.c: Regenerate.
310 * xc16x-dis.c: Regenerate.
311 * xstormy16-dis.c: Regenerate.
313 2019-12-10 Alan Modra <amodra@gmail.com>
315 * ppc-dis.c (private): Delete variable.
316 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
317 (powerpc_init_dialect): Don't use global private.
319 2019-12-10 Alan Modra <amodra@gmail.com>
321 * s12z-opc.c: Formatting.
323 2019-12-08 Alan Modra <amodra@gmail.com>
325 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
328 2019-12-05 Jan Beulich <jbeulich@suse.com>
330 * aarch64-tbl.h (aarch64_feature_crypto,
331 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
332 CRYPTO_V8_2_INSN): Delete.
334 2019-12-05 Alan Modra <amodra@gmail.com>
337 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
338 (struct string_buf): New.
339 (strbuf): New function.
340 (get_field): Use strbuf rather than strdup of local temp.
341 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
342 (get_field_rfsl, get_field_imm15): Likewise.
343 (get_field_rd, get_field_r1, get_field_r2): Update macros.
344 (get_field_special): Likewise. Don't strcpy spr. Formatting.
345 (print_insn_microblaze): Formatting. Init and pass string_buf to
348 2019-12-04 Jan Beulich <jbeulich@suse.com>
350 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
351 * i386-tbl.h: Re-generate.
353 2019-12-04 Jan Beulich <jbeulich@suse.com>
355 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
357 2019-12-04 Jan Beulich <jbeulich@suse.com>
359 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
361 (xbegin): Drop DefaultSize.
362 * i386-tbl.h: Re-generate.
364 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
366 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
367 Change the coproc CRC conditions to use the extension
368 feature set, second word, base on ARM_EXT2_CRC.
370 2019-11-14 Jan Beulich <jbeulich@suse.com>
372 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
373 * i386-tbl.h: Re-generate.
375 2019-11-14 Jan Beulich <jbeulich@suse.com>
377 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
378 JumpInterSegment, and JumpAbsolute entries.
379 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
380 JUMP_ABSOLUTE): Define.
381 (struct i386_opcode_modifier): Extend jump field to 3 bits.
382 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
384 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
385 JumpInterSegment): Define.
386 * i386-tbl.h: Re-generate.
388 2019-11-14 Jan Beulich <jbeulich@suse.com>
390 * i386-gen.c (operand_type_init): Remove
391 OPERAND_TYPE_JUMPABSOLUTE entry.
392 (opcode_modifiers): Add JumpAbsolute entry.
393 (operand_types): Remove JumpAbsolute entry.
394 * i386-opc.h (JumpAbsolute): Move between enums.
395 (struct i386_opcode_modifier): Add jumpabsolute field.
396 (union i386_operand_type): Remove jumpabsolute field.
397 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
398 * i386-init.h, i386-tbl.h: Re-generate.
400 2019-11-14 Jan Beulich <jbeulich@suse.com>
402 * i386-gen.c (opcode_modifiers): Add AnySize entry.
403 (operand_types): Remove AnySize entry.
404 * i386-opc.h (AnySize): Move between enums.
405 (struct i386_opcode_modifier): Add anysize field.
406 (OTUnused): Un-comment.
407 (union i386_operand_type): Remove anysize field.
408 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
409 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
410 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
412 * i386-tbl.h: Re-generate.
414 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
416 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
417 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
418 use the floating point register (FPR).
420 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
422 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
424 (is_mve_encoding_conflict): Update cmode conflict checks for
427 2019-11-12 Jan Beulich <jbeulich@suse.com>
429 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
431 (operand_types): Remove EsSeg entry.
432 (main): Replace stale use of OTMax.
433 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
434 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
436 (OTUnused): Comment out.
437 (union i386_operand_type): Remove esseg field.
438 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
439 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
440 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
441 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
442 * i386-init.h, i386-tbl.h: Re-generate.
444 2019-11-12 Jan Beulich <jbeulich@suse.com>
446 * i386-gen.c (operand_instances): Add RegB entry.
447 * i386-opc.h (enum operand_instance): Add RegB.
448 * i386-opc.tbl (RegC, RegD, RegB): Define.
449 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
450 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
451 monitorx, mwaitx): Drop ImmExt and convert encodings
453 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
454 (edx, rdx): Add Instance=RegD.
455 (ebx, rbx): Add Instance=RegB.
456 * i386-tbl.h: Re-generate.
458 2019-11-12 Jan Beulich <jbeulich@suse.com>
460 * i386-gen.c (operand_type_init): Adjust
461 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
462 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
463 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
464 (operand_instances): New.
465 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
466 (output_operand_type): New parameter "instance". Process it.
467 (process_i386_operand_type): New local variable "instance".
468 (main): Adjust static assertions.
469 * i386-opc.h (INSTANCE_WIDTH): Define.
470 (enum operand_instance): New.
471 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
472 (union i386_operand_type): Replace acc, inoutportreg, and
473 shiftcount by instance.
474 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
475 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
477 * i386-init.h, i386-tbl.h: Re-generate.
479 2019-11-11 Jan Beulich <jbeulich@suse.com>
481 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
482 smaxp/sminp entries' "tied_operand" field to 2.
484 2019-11-11 Jan Beulich <jbeulich@suse.com>
486 * aarch64-opc.c (operand_general_constraint_met_p): Replace
487 "index" local variable by that of the already existing "num".
489 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
492 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
493 * i386-tbl.h: Regenerated.
495 2019-11-08 Jan Beulich <jbeulich@suse.com>
497 * i386-gen.c (operand_type_init): Add Class= to
498 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
499 OPERAND_TYPE_REGBND entry.
500 (operand_classes): Add RegMask and RegBND entries.
501 (operand_types): Drop RegMask and RegBND entry.
502 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
503 (RegMask, RegBND): Delete.
504 (union i386_operand_type): Remove regmask and regbnd fields.
505 * i386-opc.tbl (RegMask, RegBND): Define.
506 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
508 * i386-init.h, i386-tbl.h: Re-generate.
510 2019-11-08 Jan Beulich <jbeulich@suse.com>
512 * i386-gen.c (operand_type_init): Add Class= to
513 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
514 OPERAND_TYPE_REGZMM entries.
515 (operand_classes): Add RegMMX and RegSIMD entries.
516 (operand_types): Drop RegMMX and RegSIMD entries.
517 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
518 (RegMMX, RegSIMD): Delete.
519 (union i386_operand_type): Remove regmmx and regsimd fields.
520 * i386-opc.tbl (RegMMX): Define.
521 (RegXMM, RegYMM, RegZMM): Add Class=.
522 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
524 * i386-init.h, i386-tbl.h: Re-generate.
526 2019-11-08 Jan Beulich <jbeulich@suse.com>
528 * i386-gen.c (operand_type_init): Add Class= to
529 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
531 (operand_classes): Add RegCR, RegDR, and RegTR entries.
532 (operand_types): Drop Control, Debug, and Test entries.
533 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
534 (Control, Debug, Test): Delete.
535 (union i386_operand_type): Remove control, debug, and test
537 * i386-opc.tbl (Control, Debug, Test): Define.
538 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
539 Class=RegDR, and Test by Class=RegTR.
540 * i386-init.h, i386-tbl.h: Re-generate.
542 2019-11-08 Jan Beulich <jbeulich@suse.com>
544 * i386-gen.c (operand_type_init): Add Class= to
545 OPERAND_TYPE_SREG entry.
546 (operand_classes): Add SReg entry.
547 (operand_types): Drop SReg entry.
548 * i386-opc.h (enum operand_class): Add SReg.
550 (union i386_operand_type): Remove sreg field.
551 * i386-opc.tbl (SReg): Define.
552 * i386-reg.tbl: Replace SReg by Class=SReg.
553 * i386-init.h, i386-tbl.h: Re-generate.
555 2019-11-08 Jan Beulich <jbeulich@suse.com>
557 * i386-gen.c (operand_type_init): Add Class=. New
558 OPERAND_TYPE_ANYIMM entry.
559 (operand_classes): New.
560 (operand_types): Drop Reg entry.
561 (output_operand_type): New parameter "class". Process it.
562 (process_i386_operand_type): New local variable "class".
563 (main): Adjust static assertions.
564 * i386-opc.h (CLASS_WIDTH): Define.
565 (enum operand_class): New.
566 (Reg): Replace by Class. Adjust comment.
567 (union i386_operand_type): Replace reg by class.
568 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
570 * i386-reg.tbl: Replace Reg by Class=Reg.
571 * i386-init.h: Re-generate.
573 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
575 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
576 (aarch64_opcode_table): Add data gathering hint mnemonic.
577 * opcodes/aarch64-dis-2.c: Account for new instruction.
579 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
581 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
584 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
586 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
587 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
588 aarch64_feature_f64mm): New feature sets.
589 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
590 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
592 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
594 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
595 (OP_SVE_QQQ): New qualifier.
596 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
597 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
598 the movprfx constraint.
599 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
600 (aarch64_opcode_table): Define new instructions smmla,
601 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
603 * aarch64-opc.c (operand_general_constraint_met_p): Handle
604 AARCH64_OPND_SVE_ADDR_RI_S4x32.
605 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
606 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
607 Account for new instructions.
608 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
610 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
612 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
613 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
615 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
617 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
618 (neon_opcodes): Add bfloat SIMD instructions.
619 (print_insn_coprocessor): Add new control character %b to print
620 condition code without checking cp_num.
621 (print_insn_neon): Account for BFloat16 instructions that have no
622 special top-byte handling.
624 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
625 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
627 * arm-dis.c (print_insn_coprocessor,
628 print_insn_generic_coprocessor): Create wrapper functions around
629 the implementation of the print_insn_coprocessor control codes.
630 (print_insn_coprocessor_1): Original print_insn_coprocessor
631 function that now takes which array to look at as an argument.
632 (print_insn_arm): Use both print_insn_coprocessor and
633 print_insn_generic_coprocessor.
634 (print_insn_thumb32): As above.
636 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
637 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
639 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
640 in reglane special case.
641 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
642 aarch64_find_next_opcode): Account for new instructions.
643 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
644 in reglane special case.
645 * aarch64-opc.c (struct operand_qualifier_data): Add data for
646 new AARCH64_OPND_QLF_S_2H qualifier.
647 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
648 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
649 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
651 (BFLOAT_SVE, BFLOAT): New feature set macros.
652 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
654 (aarch64_opcode_table): Define new instructions bfdot,
655 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
658 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
659 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
661 * aarch64-tbl.h (ARMV8_6): New macro.
663 2019-11-07 Jan Beulich <jbeulich@suse.com>
665 * i386-dis.c (prefix_table): Add mcommit.
666 (rm_table): Add rdpru.
667 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
668 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
669 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
670 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
671 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
672 * i386-opc.tbl (mcommit, rdpru): New.
673 * i386-init.h, i386-tbl.h: Re-generate.
675 2019-11-07 Jan Beulich <jbeulich@suse.com>
677 * i386-dis.c (OP_Mwait): Drop local variable "names", use
679 (OP_Monitor): Drop local variable "op1_names", re-purpose
680 "names" for it instead, and replace former "names" uses by
683 2019-11-07 Jan Beulich <jbeulich@suse.com>
686 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
688 * opcodes/i386-tbl.h: Re-generate.
690 2019-11-05 Jan Beulich <jbeulich@suse.com>
692 * i386-dis.c (OP_Mwaitx): Delete.
693 (prefix_table): Use OP_Mwait for mwaitx entry.
694 (OP_Mwait): Also handle mwaitx.
696 2019-11-05 Jan Beulich <jbeulich@suse.com>
698 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
699 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
700 (prefix_table): Add respective entries.
701 (rm_table): Link to those entries.
703 2019-11-05 Jan Beulich <jbeulich@suse.com>
705 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
706 (REG_0F1C_P_0_MOD_0): ... this.
707 (REG_0F1E_MOD_3): Rename to ...
708 (REG_0F1E_P_1_MOD_3): ... this.
709 (RM_0F01_REG_5): Rename to ...
710 (RM_0F01_REG_5_MOD_3): ... this.
711 (RM_0F01_REG_7): Rename to ...
712 (RM_0F01_REG_7_MOD_3): ... this.
713 (RM_0F1E_MOD_3_REG_7): Rename to ...
714 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
715 (RM_0FAE_REG_6): Rename to ...
716 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
717 (RM_0FAE_REG_7): Rename to ...
718 (RM_0FAE_REG_7_MOD_3): ... this.
719 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
720 (PREFIX_0F01_REG_5_MOD_0): ... this.
721 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
722 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
723 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
724 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
725 (PREFIX_0FAE_REG_0): Rename to ...
726 (PREFIX_0FAE_REG_0_MOD_3): ... this.
727 (PREFIX_0FAE_REG_1): Rename to ...
728 (PREFIX_0FAE_REG_1_MOD_3): ... this.
729 (PREFIX_0FAE_REG_2): Rename to ...
730 (PREFIX_0FAE_REG_2_MOD_3): ... this.
731 (PREFIX_0FAE_REG_3): Rename to ...
732 (PREFIX_0FAE_REG_3_MOD_3): ... this.
733 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
734 (PREFIX_0FAE_REG_4_MOD_0): ... this.
735 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
736 (PREFIX_0FAE_REG_4_MOD_3): ... this.
737 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
738 (PREFIX_0FAE_REG_5_MOD_0): ... this.
739 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
740 (PREFIX_0FAE_REG_5_MOD_3): ... this.
741 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
742 (PREFIX_0FAE_REG_6_MOD_0): ... this.
743 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
744 (PREFIX_0FAE_REG_6_MOD_3): ... this.
745 (PREFIX_0FAE_REG_7): Rename to ...
746 (PREFIX_0FAE_REG_7_MOD_0): ... this.
747 (PREFIX_MOD_0_0FC3): Rename to ...
748 (PREFIX_0FC3_MOD_0): ... this.
749 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
750 (PREFIX_0FC7_REG_6_MOD_0): ... this.
751 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
752 (PREFIX_0FC7_REG_6_MOD_3): ... this.
753 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
754 (PREFIX_0FC7_REG_7_MOD_3): ... this.
755 (reg_table, prefix_table, mod_table, rm_table): Adjust
758 2019-11-04 Nick Clifton <nickc@redhat.com>
760 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
761 of a v850 system register. Move the v850_sreg_names array into
763 (get_v850_reg_name): Likewise for ordinary register names.
764 (get_v850_vreg_name): Likewise for vector register names.
765 (get_v850_cc_name): Likewise for condition codes.
766 * get_v850_float_cc_name): Likewise for floating point condition
768 (get_v850_cacheop_name): Likewise for cache-ops.
769 (get_v850_prefop_name): Likewise for pref-ops.
770 (disassemble): Use the new accessor functions.
772 2019-10-30 Delia Burduv <delia.burduv@arm.com>
774 * aarch64-opc.c (print_immediate_offset_address): Don't print the
775 immediate for the writeback form of ldraa/ldrab if it is 0.
776 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
777 * aarch64-opc-2.c: Regenerated.
779 2019-10-30 Jan Beulich <jbeulich@suse.com>
781 * i386-gen.c (operand_type_shorthands): Delete.
782 (operand_type_init): Expand previous shorthands.
783 (set_bitfield_from_shorthand): Rename back to ...
784 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
785 of operand_type_init[].
786 (set_bitfield): Adjust call to the above function.
787 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
788 RegXMM, RegYMM, RegZMM): Define.
789 * i386-reg.tbl: Expand prior shorthands.
791 2019-10-30 Jan Beulich <jbeulich@suse.com>
793 * i386-gen.c (output_i386_opcode): Change order of fields
795 * i386-opc.h (struct insn_template): Move operands field.
796 Convert extension_opcode field to unsigned short.
797 * i386-tbl.h: Re-generate.
799 2019-10-30 Jan Beulich <jbeulich@suse.com>
801 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
803 * i386-opc.h (W): Extend comment.
804 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
805 general purpose variants not allowing for byte operands.
806 * i386-tbl.h: Re-generate.
808 2019-10-29 Nick Clifton <nickc@redhat.com>
810 * tic30-dis.c (print_branch): Correct size of operand array.
812 2019-10-29 Nick Clifton <nickc@redhat.com>
814 * d30v-dis.c (print_insn): Check that operand index is valid
815 before attempting to access the operands array.
817 2019-10-29 Nick Clifton <nickc@redhat.com>
819 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
820 locating the bit to be tested.
822 2019-10-29 Nick Clifton <nickc@redhat.com>
824 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
826 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
827 (print_insn_s12z): Check for illegal size values.
829 2019-10-28 Nick Clifton <nickc@redhat.com>
831 * csky-dis.c (csky_chars_to_number): Check for a negative
832 count. Use an unsigned integer to construct the return value.
834 2019-10-28 Nick Clifton <nickc@redhat.com>
836 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
837 operand buffer. Set value to 15 not 13.
838 (get_register_operand): Use OPERAND_BUFFER_LEN.
839 (get_indirect_operand): Likewise.
840 (print_two_operand): Likewise.
841 (print_three_operand): Likewise.
842 (print_oar_insn): Likewise.
844 2019-10-28 Nick Clifton <nickc@redhat.com>
846 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
847 (bit_extract_simple): Likewise.
848 (bit_copy): Likewise.
849 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
850 index_offset array are not accessed.
852 2019-10-28 Nick Clifton <nickc@redhat.com>
854 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
857 2019-10-25 Nick Clifton <nickc@redhat.com>
859 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
860 access to opcodes.op array element.
862 2019-10-23 Nick Clifton <nickc@redhat.com>
864 * rx-dis.c (get_register_name): Fix spelling typo in error
866 (get_condition_name, get_flag_name, get_double_register_name)
867 (get_double_register_high_name, get_double_register_low_name)
868 (get_double_control_register_name, get_double_condition_name)
869 (get_opsize_name, get_size_name): Likewise.
871 2019-10-22 Nick Clifton <nickc@redhat.com>
873 * rx-dis.c (get_size_name): New function. Provides safe
874 access to name array.
875 (get_opsize_name): Likewise.
876 (print_insn_rx): Use the accessor functions.
878 2019-10-16 Nick Clifton <nickc@redhat.com>
880 * rx-dis.c (get_register_name): New function. Provides safe
881 access to name array.
882 (get_condition_name, get_flag_name, get_double_register_name)
883 (get_double_register_high_name, get_double_register_low_name)
884 (get_double_control_register_name, get_double_condition_name):
886 (print_insn_rx): Use the accessor functions.
888 2019-10-09 Nick Clifton <nickc@redhat.com>
891 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
894 2019-10-07 Jan Beulich <jbeulich@suse.com>
896 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
897 (cmpsd): Likewise. Move EsSeg to other operand.
898 * opcodes/i386-tbl.h: Re-generate.
900 2019-09-23 Alan Modra <amodra@gmail.com>
902 * m68k-dis.c: Include cpu-m68k.h
904 2019-09-23 Alan Modra <amodra@gmail.com>
906 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
907 "elf/mips.h" earlier.
909 2018-09-20 Jan Beulich <jbeulich@suse.com>
912 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
914 * i386-tbl.h: Re-generate.
916 2019-09-18 Alan Modra <amodra@gmail.com>
918 * arc-ext.c: Update throughout for bfd section macro changes.
920 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
922 * Makefile.in: Re-generate.
923 * configure: Re-generate.
925 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
927 * riscv-opc.c (riscv_opcodes): Change subset field
928 to insn_class field for all instructions.
929 (riscv_insn_types): Likewise.
931 2019-09-16 Phil Blundell <pb@pbcl.net>
933 * configure: Regenerated.
935 2019-09-10 Miod Vallat <miod@online.fr>
938 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
940 2019-09-09 Phil Blundell <pb@pbcl.net>
942 binutils 2.33 branch created.
944 2019-09-03 Nick Clifton <nickc@redhat.com>
947 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
948 greater than zero before indexing via (bufcnt -1).
950 2019-09-03 Nick Clifton <nickc@redhat.com>
953 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
954 (MAX_SPEC_REG_NAME_LEN): Define.
955 (struct mmix_dis_info): Use defined constants for array lengths.
956 (get_reg_name): New function.
957 (get_sprec_reg_name): New function.
958 (print_insn_mmix): Use new functions.
960 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
962 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
963 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
964 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
966 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
968 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
969 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
970 (aarch64_sys_reg_supported_p): Update checks for the above.
972 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
974 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
975 cases MVE_SQRSHRL and MVE_UQRSHLL.
976 (print_insn_mve): Add case for specifier 'k' to check
977 specific bit of the instruction.
979 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
982 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
983 encountering an unknown machine type.
984 (print_insn_arc): Handle arc_insn_length returning 0. In error
985 cases return -1 rather than calling abort.
987 2019-08-07 Jan Beulich <jbeulich@suse.com>
989 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
990 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
992 * i386-tbl.h: Re-generate.
994 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
996 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
999 2019-07-30 Mel Chen <mel.chen@sifive.com>
1001 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
1002 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
1004 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
1007 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1009 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
1010 and MPY class instructions.
1011 (parse_option): Add nps400 option.
1012 (print_arc_disassembler_options): Add nps400 info.
1014 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1016 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
1019 * arc-opc.c (RAD_CHK): Add.
1020 * arc-tbl.h: Regenerate.
1022 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1024 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
1025 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
1027 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
1029 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
1030 instructions as UNPREDICTABLE.
1032 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1034 * bpf-desc.c: Regenerated.
1036 2019-07-17 Jan Beulich <jbeulich@suse.com>
1038 * i386-gen.c (static_assert): Define.
1040 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1041 (Opcode_Modifier_Num): ... this.
1044 2019-07-16 Jan Beulich <jbeulich@suse.com>
1046 * i386-gen.c (operand_types): Move RegMem ...
1047 (opcode_modifiers): ... here.
1048 * i386-opc.h (RegMem): Move to opcode modifer enum.
1049 (union i386_operand_type): Move regmem field ...
1050 (struct i386_opcode_modifier): ... here.
1051 * i386-opc.tbl (RegMem): Define.
1052 (mov, movq): Move RegMem on segment, control, debug, and test
1054 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1055 to non-SSE2AVX flavor.
1056 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1057 Move RegMem on register only flavors. Drop IgnoreSize from
1058 legacy encoding flavors.
1059 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1061 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1062 register only flavors.
1063 (vmovd): Move RegMem and drop IgnoreSize on register only
1064 flavor. Change opcode and operand order to store form.
1065 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1067 2019-07-16 Jan Beulich <jbeulich@suse.com>
1069 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1071 * i386-opc.h (SReg2, SReg3): Replace by ...
1073 (union i386_operand_type): Replace sreg fields.
1074 * i386-opc.tbl (mov, ): Use SReg.
1075 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1077 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1078 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1080 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1082 * bpf-desc.c: Regenerate.
1083 * bpf-opc.c: Likewise.
1084 * bpf-opc.h: Likewise.
1086 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1088 * bpf-desc.c: Regenerate.
1089 * bpf-opc.c: Likewise.
1091 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1093 * arm-dis.c (print_insn_coprocessor): Rename index to
1096 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
1098 * riscv-opc.c (riscv_insn_types): Add r4 type.
1100 * riscv-opc.c (riscv_insn_types): Add b and j type.
1102 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1103 format for sb type and correct s type.
1105 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1107 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1108 SVE FMOV alias of FCPY.
1110 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1112 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1113 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1115 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1117 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1118 registers in an instruction prefixed by MOVPRFX.
1120 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1122 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1123 sve_size_13 icode to account for variant behaviour of
1125 * aarch64-dis-2.c: Regenerate.
1126 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1127 sve_size_13 icode to account for variant behaviour of
1129 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1130 (OP_SVE_VVV_Q_D): Add new qualifier.
1131 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1132 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1135 2019-07-01 Jan Beulich <jbeulich@suse.com>
1137 * opcodes/i386-gen.c (operand_type_init): Remove
1138 OPERAND_TYPE_VEC_IMM4 entry.
1139 (operand_types): Remove Vec_Imm4.
1140 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1141 (union i386_operand_type): Remove vec_imm4.
1142 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1143 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1145 2019-07-01 Jan Beulich <jbeulich@suse.com>
1147 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1148 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1149 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1150 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1151 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1152 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1153 * i386-tbl.h: Re-generate.
1155 2019-07-01 Jan Beulich <jbeulich@suse.com>
1157 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1159 * i386-tbl.h: Re-generate.
1161 2019-07-01 Jan Beulich <jbeulich@suse.com>
1163 * i386-opc.tbl (C): New.
1164 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1165 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1166 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1167 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1168 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1169 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1170 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1171 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1172 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1173 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1174 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1175 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1176 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1177 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1178 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1179 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1180 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1181 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1182 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1183 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1184 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1185 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1186 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1187 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1188 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1189 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1191 * i386-tbl.h: Re-generate.
1193 2019-07-01 Jan Beulich <jbeulich@suse.com>
1195 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1197 * i386-tbl.h: Re-generate.
1199 2019-07-01 Jan Beulich <jbeulich@suse.com>
1201 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1202 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1203 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1204 * i386-tbl.h: Re-generate.
1206 2019-07-01 Jan Beulich <jbeulich@suse.com>
1208 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1209 Disp8MemShift from register only templates.
1210 * i386-tbl.h: Re-generate.
1212 2019-07-01 Jan Beulich <jbeulich@suse.com>
1214 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1215 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1216 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1217 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1218 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1219 EVEX_W_0F11_P_3_M_1): Delete.
1220 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1221 EVEX_W_0F11_P_3): New.
1222 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1223 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1224 MOD_EVEX_0F11_PREFIX_3 table entries.
1225 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1226 PREFIX_EVEX_0F11 table entries.
1227 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1228 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1229 EVEX_W_0F11_P_3_M_{0,1} table entries.
1231 2019-07-01 Jan Beulich <jbeulich@suse.com>
1233 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1236 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1239 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1240 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1241 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1242 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1243 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1244 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1245 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1246 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1247 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1248 PREFIX_EVEX_0F38C6_REG_6 entries.
1249 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1250 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1251 EVEX_W_0F38C7_R_6_P_2 entries.
1252 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1253 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1254 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1255 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1256 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1257 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1258 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1260 2019-06-27 Jan Beulich <jbeulich@suse.com>
1262 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1263 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1264 VEX_LEN_0F2D_P_3): Delete.
1265 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1266 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1267 (prefix_table): ... here.
1269 2019-06-27 Jan Beulich <jbeulich@suse.com>
1271 * i386-dis.c (Iq): Delete.
1273 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1275 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1276 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1277 (OP_E_memory): Also honor needindex when deciding whether an
1278 address size prefix needs printing.
1279 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1281 2019-06-26 Jim Wilson <jimw@sifive.com>
1284 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1285 Set info->display_endian to info->endian_code.
1287 2019-06-25 Jan Beulich <jbeulich@suse.com>
1289 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1290 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1291 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1292 OPERAND_TYPE_ACC64 entries.
1293 * i386-init.h: Re-generate.
1295 2019-06-25 Jan Beulich <jbeulich@suse.com>
1297 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1299 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1301 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1303 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1304 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1306 2019-06-25 Jan Beulich <jbeulich@suse.com>
1308 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1311 2019-06-25 Jan Beulich <jbeulich@suse.com>
1313 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1314 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1316 * i386-opc.tbl (movnti): Add IgnoreSize.
1317 * i386-tbl.h: Re-generate.
1319 2019-06-25 Jan Beulich <jbeulich@suse.com>
1321 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1322 * i386-tbl.h: Re-generate.
1324 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1326 * i386-dis-evex.h: Break into ...
1327 * i386-dis-evex-len.h: New file.
1328 * i386-dis-evex-mod.h: Likewise.
1329 * i386-dis-evex-prefix.h: Likewise.
1330 * i386-dis-evex-reg.h: Likewise.
1331 * i386-dis-evex-w.h: Likewise.
1332 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1333 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1334 i386-dis-evex-mod.h.
1336 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1339 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1340 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1342 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1343 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1344 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1345 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1346 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1347 EVEX_LEN_0F385B_P_2_W_1.
1348 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1349 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1350 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1351 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1352 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1353 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1354 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1355 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1356 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1357 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1359 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1362 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1363 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1364 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1365 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1366 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1367 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1368 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1369 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1370 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1371 EVEX_LEN_0F3A43_P_2_W_1.
1372 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1373 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1374 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1375 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1376 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1377 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1378 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1379 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1380 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1381 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1382 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1383 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1385 2019-06-14 Nick Clifton <nickc@redhat.com>
1387 * po/fr.po; Updated French translation.
1389 2019-06-13 Stafford Horne <shorne@gmail.com>
1391 * or1k-asm.c: Regenerated.
1392 * or1k-desc.c: Regenerated.
1393 * or1k-desc.h: Regenerated.
1394 * or1k-dis.c: Regenerated.
1395 * or1k-ibld.c: Regenerated.
1396 * or1k-opc.c: Regenerated.
1397 * or1k-opc.h: Regenerated.
1398 * or1k-opinst.c: Regenerated.
1400 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1402 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1404 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1407 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1408 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1409 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1410 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1411 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1412 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1413 EVEX_LEN_0F3A1B_P_2_W_1.
1414 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1415 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1416 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1417 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1418 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1419 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1420 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1421 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1423 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1426 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1427 EVEX.vvvv when disassembling VEX and EVEX instructions.
1428 (OP_VEX): Set vex.register_specifier to 0 after readding
1429 vex.register_specifier.
1430 (OP_Vex_2src_1): Likewise.
1431 (OP_Vex_2src_2): Likewise.
1432 (OP_LWP_E): Likewise.
1433 (OP_EX_Vex): Don't check vex.register_specifier.
1434 (OP_XMM_Vex): Likewise.
1436 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1437 Lili Cui <lili.cui@intel.com>
1439 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1440 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1442 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1443 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1444 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1445 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1446 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1447 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1448 * i386-init.h: Regenerated.
1449 * i386-tbl.h: Likewise.
1451 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1452 Lili Cui <lili.cui@intel.com>
1454 * doc/c-i386.texi: Document enqcmd.
1455 * testsuite/gas/i386/enqcmd-intel.d: New file.
1456 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1457 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1458 * testsuite/gas/i386/enqcmd.d: Likewise.
1459 * testsuite/gas/i386/enqcmd.s: Likewise.
1460 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1461 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1462 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1463 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1464 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1465 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1466 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1469 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1471 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1473 2019-06-03 Alan Modra <amodra@gmail.com>
1475 * ppc-dis.c (prefix_opcd_indices): Correct size.
1477 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1480 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1482 * i386-tbl.h: Regenerated.
1484 2019-05-24 Alan Modra <amodra@gmail.com>
1486 * po/POTFILES.in: Regenerate.
1488 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1489 Alan Modra <amodra@gmail.com>
1491 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1492 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1493 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1494 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1495 XTOP>): Define and add entries.
1496 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1497 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1498 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1499 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1501 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1502 Alan Modra <amodra@gmail.com>
1504 * ppc-dis.c (ppc_opts): Add "future" entry.
1505 (PREFIX_OPCD_SEGS): Define.
1506 (prefix_opcd_indices): New array.
1507 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1508 (lookup_prefix): New function.
1509 (print_insn_powerpc): Handle 64-bit prefix instructions.
1510 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1511 (PMRR, POWERXX): Define.
1512 (prefix_opcodes): New instruction table.
1513 (prefix_num_opcodes): New constant.
1515 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1517 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1518 * configure: Regenerated.
1519 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1521 (HFILES): Add bpf-desc.h and bpf-opc.h.
1522 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1523 bpf-ibld.c and bpf-opc.c.
1525 * Makefile.in: Regenerated.
1526 * disassemble.c (ARCH_bpf): Define.
1527 (disassembler): Add case for bfd_arch_bpf.
1528 (disassemble_init_for_target): Likewise.
1529 (enum epbf_isa_attr): Define.
1530 * disassemble.h: extern print_insn_bpf.
1531 * bpf-asm.c: Generated.
1532 * bpf-opc.h: Likewise.
1533 * bpf-opc.c: Likewise.
1534 * bpf-ibld.c: Likewise.
1535 * bpf-dis.c: Likewise.
1536 * bpf-desc.h: Likewise.
1537 * bpf-desc.c: Likewise.
1539 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1541 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1542 and VMSR with the new operands.
1544 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1546 * arm-dis.c (enum mve_instructions): New enum
1547 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1549 (mve_opcodes): New instructions as above.
1550 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1552 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1554 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1556 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1557 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1558 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1559 uqshl, urshrl and urshr.
1560 (is_mve_okay_in_it): Add new instructions to TRUE list.
1561 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1562 (print_insn_mve): Updated to accept new %j,
1563 %<bitfield>m and %<bitfield>n patterns.
1565 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1567 * mips-opc.c (mips_builtin_opcodes): Change source register
1568 constraint for DAUI.
1570 2019-05-20 Nick Clifton <nickc@redhat.com>
1572 * po/fr.po: Updated French translation.
1574 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1575 Michael Collison <michael.collison@arm.com>
1577 * arm-dis.c (thumb32_opcodes): Add new instructions.
1578 (enum mve_instructions): Likewise.
1579 (enum mve_undefined): Add new reasons.
1580 (is_mve_encoding_conflict): Handle new instructions.
1581 (is_mve_undefined): Likewise.
1582 (is_mve_unpredictable): Likewise.
1583 (print_mve_undefined): Likewise.
1584 (print_mve_size): Likewise.
1586 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1587 Michael Collison <michael.collison@arm.com>
1589 * arm-dis.c (thumb32_opcodes): Add new instructions.
1590 (enum mve_instructions): Likewise.
1591 (is_mve_encoding_conflict): Handle new instructions.
1592 (is_mve_undefined): Likewise.
1593 (is_mve_unpredictable): Likewise.
1594 (print_mve_size): Likewise.
1596 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1597 Michael Collison <michael.collison@arm.com>
1599 * arm-dis.c (thumb32_opcodes): Add new instructions.
1600 (enum mve_instructions): Likewise.
1601 (is_mve_encoding_conflict): Likewise.
1602 (is_mve_unpredictable): Likewise.
1603 (print_mve_size): Likewise.
1605 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1606 Michael Collison <michael.collison@arm.com>
1608 * arm-dis.c (thumb32_opcodes): Add new instructions.
1609 (enum mve_instructions): Likewise.
1610 (is_mve_encoding_conflict): Handle new instructions.
1611 (is_mve_undefined): Likewise.
1612 (is_mve_unpredictable): Likewise.
1613 (print_mve_size): Likewise.
1615 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1616 Michael Collison <michael.collison@arm.com>
1618 * arm-dis.c (thumb32_opcodes): Add new instructions.
1619 (enum mve_instructions): Likewise.
1620 (is_mve_encoding_conflict): Handle new instructions.
1621 (is_mve_undefined): Likewise.
1622 (is_mve_unpredictable): Likewise.
1623 (print_mve_size): Likewise.
1624 (print_insn_mve): Likewise.
1626 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1627 Michael Collison <michael.collison@arm.com>
1629 * arm-dis.c (thumb32_opcodes): Add new instructions.
1630 (print_insn_thumb32): Handle new instructions.
1632 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1633 Michael Collison <michael.collison@arm.com>
1635 * arm-dis.c (enum mve_instructions): Add new instructions.
1636 (enum mve_undefined): Add new reasons.
1637 (is_mve_encoding_conflict): Handle new instructions.
1638 (is_mve_undefined): Likewise.
1639 (is_mve_unpredictable): Likewise.
1640 (print_mve_undefined): Likewise.
1641 (print_mve_size): Likewise.
1642 (print_mve_shift_n): Likewise.
1643 (print_insn_mve): Likewise.
1645 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1646 Michael Collison <michael.collison@arm.com>
1648 * arm-dis.c (enum mve_instructions): Add new instructions.
1649 (is_mve_encoding_conflict): Handle new instructions.
1650 (is_mve_unpredictable): Likewise.
1651 (print_mve_rotate): Likewise.
1652 (print_mve_size): Likewise.
1653 (print_insn_mve): Likewise.
1655 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1656 Michael Collison <michael.collison@arm.com>
1658 * arm-dis.c (enum mve_instructions): Add new instructions.
1659 (is_mve_encoding_conflict): Handle new instructions.
1660 (is_mve_unpredictable): Likewise.
1661 (print_mve_size): Likewise.
1662 (print_insn_mve): Likewise.
1664 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1665 Michael Collison <michael.collison@arm.com>
1667 * arm-dis.c (enum mve_instructions): Add new instructions.
1668 (enum mve_undefined): Add new reasons.
1669 (is_mve_encoding_conflict): Handle new instructions.
1670 (is_mve_undefined): Likewise.
1671 (is_mve_unpredictable): Likewise.
1672 (print_mve_undefined): Likewise.
1673 (print_mve_size): Likewise.
1674 (print_insn_mve): Likewise.
1676 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1677 Michael Collison <michael.collison@arm.com>
1679 * arm-dis.c (enum mve_instructions): Add new instructions.
1680 (is_mve_encoding_conflict): Handle new instructions.
1681 (is_mve_undefined): Likewise.
1682 (is_mve_unpredictable): Likewise.
1683 (print_mve_size): Likewise.
1684 (print_insn_mve): Likewise.
1686 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1687 Michael Collison <michael.collison@arm.com>
1689 * arm-dis.c (enum mve_instructions): Add new instructions.
1690 (enum mve_unpredictable): Add new reasons.
1691 (enum mve_undefined): Likewise.
1692 (is_mve_okay_in_it): Handle new isntructions.
1693 (is_mve_encoding_conflict): Likewise.
1694 (is_mve_undefined): Likewise.
1695 (is_mve_unpredictable): Likewise.
1696 (print_mve_vmov_index): Likewise.
1697 (print_simd_imm8): Likewise.
1698 (print_mve_undefined): Likewise.
1699 (print_mve_unpredictable): Likewise.
1700 (print_mve_size): Likewise.
1701 (print_insn_mve): Likewise.
1703 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1704 Michael Collison <michael.collison@arm.com>
1706 * arm-dis.c (enum mve_instructions): Add new instructions.
1707 (enum mve_unpredictable): Add new reasons.
1708 (enum mve_undefined): Likewise.
1709 (is_mve_encoding_conflict): Handle new instructions.
1710 (is_mve_undefined): Likewise.
1711 (is_mve_unpredictable): Likewise.
1712 (print_mve_undefined): Likewise.
1713 (print_mve_unpredictable): Likewise.
1714 (print_mve_rounding_mode): Likewise.
1715 (print_mve_vcvt_size): Likewise.
1716 (print_mve_size): Likewise.
1717 (print_insn_mve): Likewise.
1719 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1720 Michael Collison <michael.collison@arm.com>
1722 * arm-dis.c (enum mve_instructions): Add new instructions.
1723 (enum mve_unpredictable): Add new reasons.
1724 (enum mve_undefined): Likewise.
1725 (is_mve_undefined): Handle new instructions.
1726 (is_mve_unpredictable): Likewise.
1727 (print_mve_undefined): Likewise.
1728 (print_mve_unpredictable): Likewise.
1729 (print_mve_size): Likewise.
1730 (print_insn_mve): Likewise.
1732 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1733 Michael Collison <michael.collison@arm.com>
1735 * arm-dis.c (enum mve_instructions): Add new instructions.
1736 (enum mve_undefined): Add new reasons.
1737 (insns): Add new instructions.
1738 (is_mve_encoding_conflict):
1739 (print_mve_vld_str_addr): New print function.
1740 (is_mve_undefined): Handle new instructions.
1741 (is_mve_unpredictable): Likewise.
1742 (print_mve_undefined): Likewise.
1743 (print_mve_size): Likewise.
1744 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1745 (print_insn_mve): Handle new operands.
1747 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1748 Michael Collison <michael.collison@arm.com>
1750 * arm-dis.c (enum mve_instructions): Add new instructions.
1751 (enum mve_unpredictable): Add new reasons.
1752 (is_mve_encoding_conflict): Handle new instructions.
1753 (is_mve_unpredictable): Likewise.
1754 (mve_opcodes): Add new instructions.
1755 (print_mve_unpredictable): Handle new reasons.
1756 (print_mve_register_blocks): New print function.
1757 (print_mve_size): Handle new instructions.
1758 (print_insn_mve): Likewise.
1760 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1761 Michael Collison <michael.collison@arm.com>
1763 * arm-dis.c (enum mve_instructions): Add new instructions.
1764 (enum mve_unpredictable): Add new reasons.
1765 (enum mve_undefined): Likewise.
1766 (is_mve_encoding_conflict): Handle new instructions.
1767 (is_mve_undefined): Likewise.
1768 (is_mve_unpredictable): Likewise.
1769 (coprocessor_opcodes): Move NEON VDUP from here...
1770 (neon_opcodes): ... to here.
1771 (mve_opcodes): Add new instructions.
1772 (print_mve_undefined): Handle new reasons.
1773 (print_mve_unpredictable): Likewise.
1774 (print_mve_size): Handle new instructions.
1775 (print_insn_neon): Handle vdup.
1776 (print_insn_mve): Handle new operands.
1778 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1779 Michael Collison <michael.collison@arm.com>
1781 * arm-dis.c (enum mve_instructions): Add new instructions.
1782 (enum mve_unpredictable): Add new values.
1783 (mve_opcodes): Add new instructions.
1784 (vec_condnames): New array with vector conditions.
1785 (mve_predicatenames): New array with predicate suffixes.
1786 (mve_vec_sizename): New array with vector sizes.
1787 (enum vpt_pred_state): New enum with vector predication states.
1788 (struct vpt_block): New struct type for vpt blocks.
1789 (vpt_block_state): Global struct to keep track of state.
1790 (mve_extract_pred_mask): New helper function.
1791 (num_instructions_vpt_block): Likewise.
1792 (mark_outside_vpt_block): Likewise.
1793 (mark_inside_vpt_block): Likewise.
1794 (invert_next_predicate_state): Likewise.
1795 (update_next_predicate_state): Likewise.
1796 (update_vpt_block_state): Likewise.
1797 (is_vpt_instruction): Likewise.
1798 (is_mve_encoding_conflict): Add entries for new instructions.
1799 (is_mve_unpredictable): Likewise.
1800 (print_mve_unpredictable): Handle new cases.
1801 (print_instruction_predicate): Likewise.
1802 (print_mve_size): New function.
1803 (print_vec_condition): New function.
1804 (print_insn_mve): Handle vpt blocks and new print operands.
1806 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1808 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1809 8, 14 and 15 for Armv8.1-M Mainline.
1811 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1812 Michael Collison <michael.collison@arm.com>
1814 * arm-dis.c (enum mve_instructions): New enum.
1815 (enum mve_unpredictable): Likewise.
1816 (enum mve_undefined): Likewise.
1817 (struct mopcode32): New struct.
1818 (is_mve_okay_in_it): New function.
1819 (is_mve_architecture): Likewise.
1820 (arm_decode_field): Likewise.
1821 (arm_decode_field_multiple): Likewise.
1822 (is_mve_encoding_conflict): Likewise.
1823 (is_mve_undefined): Likewise.
1824 (is_mve_unpredictable): Likewise.
1825 (print_mve_undefined): Likewise.
1826 (print_mve_unpredictable): Likewise.
1827 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1828 (print_insn_mve): New function.
1829 (print_insn_thumb32): Handle MVE architecture.
1830 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1832 2019-05-10 Nick Clifton <nickc@redhat.com>
1835 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1836 end of the table prematurely.
1838 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1840 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1843 2019-05-11 Alan Modra <amodra@gmail.com>
1845 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1846 when -Mraw is in effect.
1848 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1850 * aarch64-dis-2.c: Regenerate.
1851 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1852 (OP_SVE_BBB): New variant set.
1853 (OP_SVE_DDDD): New variant set.
1854 (OP_SVE_HHH): New variant set.
1855 (OP_SVE_HHHU): New variant set.
1856 (OP_SVE_SSS): New variant set.
1857 (OP_SVE_SSSU): New variant set.
1858 (OP_SVE_SHH): New variant set.
1859 (OP_SVE_SBBU): New variant set.
1860 (OP_SVE_DSS): New variant set.
1861 (OP_SVE_DHHU): New variant set.
1862 (OP_SVE_VMV_HSD_BHS): New variant set.
1863 (OP_SVE_VVU_HSD_BHS): New variant set.
1864 (OP_SVE_VVVU_SD_BH): New variant set.
1865 (OP_SVE_VVVU_BHSD): New variant set.
1866 (OP_SVE_VVV_QHD_DBS): New variant set.
1867 (OP_SVE_VVV_HSD_BHS): New variant set.
1868 (OP_SVE_VVV_HSD_BHS2): New variant set.
1869 (OP_SVE_VVV_BHS_HSD): New variant set.
1870 (OP_SVE_VV_BHS_HSD): New variant set.
1871 (OP_SVE_VVV_SD): New variant set.
1872 (OP_SVE_VVU_BHS_HSD): New variant set.
1873 (OP_SVE_VZVV_SD): New variant set.
1874 (OP_SVE_VZVV_BH): New variant set.
1875 (OP_SVE_VZV_SD): New variant set.
1876 (aarch64_opcode_table): Add sve2 instructions.
1878 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1880 * aarch64-asm-2.c: Regenerated.
1881 * aarch64-dis-2.c: Regenerated.
1882 * aarch64-opc-2.c: Regenerated.
1883 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1884 for SVE_SHLIMM_UNPRED_22.
1885 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1886 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1889 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1891 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1892 sve_size_tsz_bhs iclass encode.
1893 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1894 sve_size_tsz_bhs iclass decode.
1896 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1898 * aarch64-asm-2.c: Regenerated.
1899 * aarch64-dis-2.c: Regenerated.
1900 * aarch64-opc-2.c: Regenerated.
1901 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1902 for SVE_Zm4_11_INDEX.
1903 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1904 (fields): Handle SVE_i2h field.
1905 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1906 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1908 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1910 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1911 sve_shift_tsz_bhsd iclass encode.
1912 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1913 sve_shift_tsz_bhsd iclass decode.
1915 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1917 * aarch64-asm-2.c: Regenerated.
1918 * aarch64-dis-2.c: Regenerated.
1919 * aarch64-opc-2.c: Regenerated.
1920 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1921 (aarch64_encode_variant_using_iclass): Handle
1922 sve_shift_tsz_hsd iclass encode.
1923 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1924 sve_shift_tsz_hsd iclass decode.
1925 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1926 for SVE_SHRIMM_UNPRED_22.
1927 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1928 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1931 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1933 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1934 sve_size_013 iclass encode.
1935 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1936 sve_size_013 iclass decode.
1938 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1940 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1941 sve_size_bh iclass encode.
1942 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1943 sve_size_bh iclass decode.
1945 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1947 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1948 sve_size_sd2 iclass encode.
1949 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1950 sve_size_sd2 iclass decode.
1951 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1952 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1954 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1956 * aarch64-asm-2.c: Regenerated.
1957 * aarch64-dis-2.c: Regenerated.
1958 * aarch64-opc-2.c: Regenerated.
1959 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1961 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1962 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1964 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1966 * aarch64-asm-2.c: Regenerated.
1967 * aarch64-dis-2.c: Regenerated.
1968 * aarch64-opc-2.c: Regenerated.
1969 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1970 for SVE_Zm3_11_INDEX.
1971 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1972 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1973 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1975 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1977 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1979 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1980 sve_size_hsd2 iclass encode.
1981 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1982 sve_size_hsd2 iclass decode.
1983 * aarch64-opc.c (fields): Handle SVE_size field.
1984 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1986 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1988 * aarch64-asm-2.c: Regenerated.
1989 * aarch64-dis-2.c: Regenerated.
1990 * aarch64-opc-2.c: Regenerated.
1991 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1993 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1994 (fields): Handle SVE_rot3 field.
1995 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1996 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1998 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2000 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
2003 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2006 (aarch64_feature_sve2, aarch64_feature_sve2aes,
2007 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
2008 aarch64_feature_sve2bitperm): New feature sets.
2009 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
2010 for feature set addresses.
2011 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
2012 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2014 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
2015 Faraz Shahbazker <fshahbazker@wavecomp.com>
2017 * mips-dis.c (mips_calculate_combination_ases): Add ISA
2018 argument and set ASE_EVA_R6 appropriately.
2019 (set_default_mips_dis_options): Pass ISA to above.
2020 (parse_mips_dis_option): Likewise.
2021 * mips-opc.c (EVAR6): New macro.
2022 (mips_builtin_opcodes): Add llwpe, scwpe.
2024 2019-05-01 Sudakshina Das <sudi.das@arm.com>
2026 * aarch64-asm-2.c: Regenerated.
2027 * aarch64-dis-2.c: Regenerated.
2028 * aarch64-opc-2.c: Regenerated.
2029 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
2030 AARCH64_OPND_TME_UIMM16.
2031 (aarch64_print_operand): Likewise.
2032 * aarch64-tbl.h (QL_IMM_NIL): New.
2035 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2037 2019-04-29 John Darrington <john@darrington.wattle.id.au>
2039 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2041 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
2042 Faraz Shahbazker <fshahbazker@wavecomp.com>
2044 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2046 2019-04-24 John Darrington <john@darrington.wattle.id.au>
2048 * s12z-opc.h: Add extern "C" bracketing to help
2049 users who wish to use this interface in c++ code.
2051 2019-04-24 John Darrington <john@darrington.wattle.id.au>
2053 * s12z-opc.c (bm_decode): Handle bit map operations with the
2056 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2058 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2059 specifier. Add entries for VLDR and VSTR of system registers.
2060 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2061 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2062 of %J and %K format specifier.
2064 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2066 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2067 Add new entries for VSCCLRM instruction.
2068 (print_insn_coprocessor): Handle new %C format control code.
2070 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2072 * arm-dis.c (enum isa): New enum.
2073 (struct sopcode32): New structure.
2074 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2075 set isa field of all current entries to ANY.
2076 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2077 Only match an entry if its isa field allows the current mode.
2079 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2081 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2083 (print_insn_thumb32): Add logic to print %n CLRM register list.
2085 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2087 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2090 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2092 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2093 (print_insn_thumb32): Edit the switch case for %Z.
2095 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2097 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2099 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2101 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2103 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2105 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2107 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2109 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2110 Arm register with r13 and r15 unpredictable.
2111 (thumb32_opcodes): New instructions for bfx and bflx.
2113 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2115 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2117 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2119 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2121 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2123 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2125 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2127 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2129 2019-04-12 John Darrington <john@darrington.wattle.id.au>
2131 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2132 "optr". ("operator" is a reserved word in c++).
2134 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2136 * aarch64-opc.c (aarch64_print_operand): Add case for
2138 (verify_constraints): Likewise.
2139 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2140 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2141 to accept Rt|SP as first operand.
2142 (AARCH64_OPERANDS): Add new Rt_SP.
2143 * aarch64-asm-2.c: Regenerated.
2144 * aarch64-dis-2.c: Regenerated.
2145 * aarch64-opc-2.c: Regenerated.
2147 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2149 * aarch64-asm-2.c: Regenerated.
2150 * aarch64-dis-2.c: Likewise.
2151 * aarch64-opc-2.c: Likewise.
2152 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2154 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2156 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2158 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2160 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2161 * i386-init.h: Regenerated.
2163 2019-04-07 Alan Modra <amodra@gmail.com>
2165 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2166 op_separator to control printing of spaces, comma and parens
2167 rather than need_comma, need_paren and spaces vars.
2169 2019-04-07 Alan Modra <amodra@gmail.com>
2172 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2173 (print_insn_neon, print_insn_arm): Likewise.
2175 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2177 * i386-dis-evex.h (evex_table): Updated to support BF16
2179 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2180 and EVEX_W_0F3872_P_3.
2181 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2182 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2183 * i386-opc.h (enum): Add CpuAVX512_BF16.
2184 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2185 * i386-opc.tbl: Add AVX512 BF16 instructions.
2186 * i386-init.h: Regenerated.
2187 * i386-tbl.h: Likewise.
2189 2019-04-05 Alan Modra <amodra@gmail.com>
2191 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2192 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2193 to favour printing of "-" branch hint when using the "y" bit.
2194 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2196 2019-04-05 Alan Modra <amodra@gmail.com>
2198 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2199 opcode until first operand is output.
2201 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
2204 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2205 (valid_bo_post_v2): Add support for 'at' branch hints.
2206 (insert_bo): Only error on branch on ctr.
2207 (get_bo_hint_mask): New function.
2208 (insert_boe): Add new 'branch_taken' formal argument. Add support
2209 for inserting 'at' branch hints.
2210 (extract_boe): Add new 'branch_taken' formal argument. Add support
2211 for extracting 'at' branch hints.
2212 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2213 (BOE): Delete operand.
2214 (BOM, BOP): New operands.
2216 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2217 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2218 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2219 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2220 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2221 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2222 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2223 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2224 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2225 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2226 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2227 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2228 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2229 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2230 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2231 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2232 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2233 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2234 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2235 bttarl+>: New extended mnemonics.
2237 2019-03-28 Alan Modra <amodra@gmail.com>
2240 * ppc-opc.c (BTF): Define.
2241 (powerpc_opcodes): Use for mtfsb*.
2242 * ppc-dis.c (print_insn_powerpc): Print fields with both
2243 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2245 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2247 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2248 (mapping_symbol_for_insn): Implement new algorithm.
2249 (print_insn): Remove duplicate code.
2251 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2253 * aarch64-dis.c (print_insn_aarch64):
2256 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2258 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2261 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2263 * aarch64-dis.c (last_stop_offset): New.
2264 (print_insn_aarch64): Use stop_offset.
2266 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2269 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2271 * i386-init.h: Regenerated.
2273 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2276 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2277 vmovdqu16, vmovdqu32 and vmovdqu64.
2278 * i386-tbl.h: Regenerated.
2280 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2282 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2283 from vstrszb, vstrszh, and vstrszf.
2285 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2287 * s390-opc.txt: Add instruction descriptions.
2289 2019-02-08 Jim Wilson <jimw@sifive.com>
2291 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2294 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2296 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2298 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2301 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2302 * aarch64-opc.c (verify_elem_sd): New.
2303 (fields): Add FLD_sz entr.
2304 * aarch64-tbl.h (_SIMD_INSN): New.
2305 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2306 fmulx scalar and vector by element isns.
2308 2019-02-07 Nick Clifton <nickc@redhat.com>
2310 * po/sv.po: Updated Swedish translation.
2312 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2314 * s390-mkopc.c (main): Accept arch13 as cpu string.
2315 * s390-opc.c: Add new instruction formats and instruction opcode
2317 * s390-opc.txt: Add new arch13 instructions.
2319 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2321 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2322 (aarch64_opcode): Change encoding for stg, stzg
2324 * aarch64-asm-2.c: Regenerated.
2325 * aarch64-dis-2.c: Regenerated.
2326 * aarch64-opc-2.c: Regenerated.
2328 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2330 * aarch64-asm-2.c: Regenerated.
2331 * aarch64-dis-2.c: Likewise.
2332 * aarch64-opc-2.c: Likewise.
2333 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2335 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2336 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2338 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2339 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2340 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2341 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2342 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2343 case for ldstgv_indexed.
2344 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2345 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2346 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2347 * aarch64-asm-2.c: Regenerated.
2348 * aarch64-dis-2.c: Regenerated.
2349 * aarch64-opc-2.c: Regenerated.
2351 2019-01-23 Nick Clifton <nickc@redhat.com>
2353 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2355 2019-01-21 Nick Clifton <nickc@redhat.com>
2357 * po/de.po: Updated German translation.
2358 * po/uk.po: Updated Ukranian translation.
2360 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2361 * mips-dis.c (mips_arch_choices): Fix typo in
2362 gs464, gs464e and gs264e descriptors.
2364 2019-01-19 Nick Clifton <nickc@redhat.com>
2366 * configure: Regenerate.
2367 * po/opcodes.pot: Regenerate.
2369 2018-06-24 Nick Clifton <nickc@redhat.com>
2371 2.32 branch created.
2373 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2375 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2377 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2380 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2382 * configure: Regenerate.
2384 2019-01-07 Alan Modra <amodra@gmail.com>
2386 * configure: Regenerate.
2387 * po/POTFILES.in: Regenerate.
2389 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2391 * s12z-opc.c: New file.
2392 * s12z-opc.h: New file.
2393 * s12z-dis.c: Removed all code not directly related to display
2394 of instructions. Used the interface provided by the new files
2396 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2397 * Makefile.in: Regenerate.
2398 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2399 * configure: Regenerate.
2401 2019-01-01 Alan Modra <amodra@gmail.com>
2403 Update year range in copyright notice of all files.
2405 For older changes see ChangeLog-2018
2407 Copyright (C) 2019 Free Software Foundation, Inc.
2409 Copying and distribution of this file, with or without modification,
2410 are permitted in any medium without royalty provided the copyright
2411 notice and this notice are preserved.
2417 version-control: never