1 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
3 * arm-dis.c (print_insn_coprocessor): Added support for quarter
5 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
6 quarter float bitfield format.
8 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
10 * configure: Regenerated.
12 2015-07-03 Alan Modra <amodra@gmail.com>
14 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
15 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
16 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
18 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
19 Cesar Philippidis <cesar@codesourcery.com>
21 * nios2-dis.c (nios2_extract_opcode): New.
22 (nios2_disassembler_state): New.
23 (nios2_find_opcode_hash): Use mach parameter to select correct
25 (nios2_print_insn_arg): Extend to support new R2 argument letters
27 (print_insn_nios2): Check for 16-bit instruction at end of memory.
28 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
29 (NIOS2_NUM_OPCODES): Rename to...
30 (NIOS2_NUM_R1_OPCODES): This.
31 (nios2_r2_opcodes): New.
32 (NIOS2_NUM_R2_OPCODES): New.
33 (nios2_num_r2_opcodes): New.
34 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
35 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
36 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
37 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
38 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
40 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
42 * i386-dis.c (OP_Mwaitx): New.
43 (rm_table): Add monitorx/mwaitx.
44 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
45 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
46 (operand_type_init): Add CpuMWAITX.
47 * i386-opc.h (CpuMWAITX): New.
48 (i386_cpu_flags): Add cpumwaitx.
49 * i386-opc.tbl: Add monitorx and mwaitx.
50 * i386-init.h: Regenerated.
51 * i386-tbl.h: Likewise.
53 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
55 * ppc-opc.c (insert_ls): Test for invalid LS operands.
56 (insert_esync): New function.
57 (LS, WC): Use insert_ls.
58 (ESYNC): Use insert_esync.
60 2015-06-22 Nick Clifton <nickc@redhat.com>
62 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
63 requested region lies beyond it.
64 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
65 looking for 32-bit insns.
66 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
68 * sh-dis.c (print_insn_sh): Likewise.
69 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
70 blocks of instructions.
71 * vax-dis.c (print_insn_vax): Check that the requested address
72 does not clash with the stop_vma.
74 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
76 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
77 * ppc-opc.c (FXM4): Add non-zero optional value.
80 (insert_fxm): Handle new default operand value.
81 (extract_fxm): Likewise.
82 (insert_tbr): Likewise.
83 (extract_tbr): Likewise.
85 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
87 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
89 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
91 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
93 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
95 * ppc-opc.c: Add comment accidentally removed by old commit.
98 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
100 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
102 2015-06-04 Nick Clifton <nickc@redhat.com>
105 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
107 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
109 * arm-dis.c (arm_opcodes): Add "setpan".
110 (thumb_opcodes): Add "setpan".
112 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
114 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
117 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
119 * aarch64-tbl.h (aarch64_feature_rdma): New.
121 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
122 * aarch64-asm-2.c: Regenerate.
123 * aarch64-dis-2.c: Regenerate.
124 * aarch64-opc-2.c: Regenerate.
126 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
128 * aarch64-tbl.h (aarch64_feature_lor): New.
130 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
132 * aarch64-asm-2.c: Regenerate.
133 * aarch64-dis-2.c: Regenerate.
134 * aarch64-opc-2.c: Regenerate.
136 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
138 * aarch64-opc.c (F_ARCHEXT): New.
139 (aarch64_sys_regs): Add "pan".
140 (aarch64_sys_reg_supported_p): New.
141 (aarch64_pstatefields): Add "pan".
142 (aarch64_pstatefield_supported_p): New.
144 2015-06-01 Jan Beulich <jbeulich@suse.com>
146 * i386-tbl.h: Regenerate.
148 2015-06-01 Jan Beulich <jbeulich@suse.com>
150 * i386-dis.c (print_insn): Swap rounding mode specifier and
151 general purpose register in Intel mode.
153 2015-06-01 Jan Beulich <jbeulich@suse.com>
155 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
156 * i386-tbl.h: Regenerate.
158 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
160 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
161 * i386-init.h: Regenerated.
163 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
166 * i386-dis.c: Add comments for '@'.
167 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
168 (enum x86_64_isa): New.
170 (print_i386_disassembler_options): Add amd64 and intel64.
171 (print_insn): Handle amd64 and intel64.
173 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
174 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
175 * i386-opc.h (AMD64): New.
176 (CpuIntel64): Likewise.
177 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
178 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
179 Mark direct call/jmp without Disp16|Disp32 as Intel64.
180 * i386-init.h: Regenerated.
181 * i386-tbl.h: Likewise.
183 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
185 * ppc-opc.c (IH) New define.
186 (powerpc_opcodes) <wait>: Do not enable for POWER7.
187 <tlbie>: Add RS operand for POWER7.
188 <slbia>: Add IH operand for POWER6.
190 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
192 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
195 * i386-tbl.h: Regenerated.
197 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
199 * configure.ac: Support bfd_iamcu_arch.
200 * disassemble.c (disassembler): Support bfd_iamcu_arch.
201 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
202 CPU_IAMCU_COMPAT_FLAGS.
203 (cpu_flags): Add CpuIAMCU.
204 * i386-opc.h (CpuIAMCU): New.
205 (i386_cpu_flags): Add cpuiamcu.
206 * configure: Regenerated.
207 * i386-init.h: Likewise.
208 * i386-tbl.h: Likewise.
210 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
213 * i386-dis.c (X86_64_E8): New.
214 (X86_64_E9): Likewise.
215 Update comments on 'T', 'U', 'V'. Add comments for '^'.
216 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
217 (x86_64_table): Add X86_64_E8 and X86_64_E9.
218 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
220 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
223 2015-04-30 DJ Delorie <dj@redhat.com>
225 * disassemble.c (disassembler): Choose suitable disassembler based
227 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
228 it to decode mul/div insns.
229 * rl78-decode.c: Regenerate.
230 * rl78-dis.c (print_insn_rl78): Rename to...
231 (print_insn_rl78_common): ...this, take ISA parameter.
232 (print_insn_rl78): New.
233 (print_insn_rl78_g10): New.
234 (print_insn_rl78_g13): New.
235 (print_insn_rl78_g14): New.
236 (rl78_get_disassembler): New.
238 2015-04-29 Nick Clifton <nickc@redhat.com>
240 * po/fr.po: Updated French translation.
242 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
244 * ppc-opc.c (DCBT_EO): New define.
245 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
249 <waitrsv>: Do not enable for POWER7 and later.
250 <waitimpl>: Likewise.
251 <dcbt>: Default to the two operand form of the instruction for all
252 "old" cpus. For "new" cpus, use the operand ordering that matches
253 whether the cpu is server or embedded.
256 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
258 * s390-opc.c: New instruction type VV0UU2.
259 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
262 2015-04-23 Jan Beulich <jbeulich@suse.com>
264 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
265 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
266 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
267 (vfpclasspd, vfpclassps): Add %XZ.
269 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
271 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
272 (PREFIX_UD_REPZ): Likewise.
273 (PREFIX_UD_REPNZ): Likewise.
274 (PREFIX_UD_DATA): Likewise.
275 (PREFIX_UD_ADDR): Likewise.
276 (PREFIX_UD_LOCK): Likewise.
278 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
280 * i386-dis.c (prefix_requirement): Removed.
281 (print_insn): Don't set prefix_requirement. Check
282 dp->prefix_requirement instead of prefix_requirement.
284 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
287 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
288 (PREFIX_MOD_0_0FC7_REG_6): This.
289 (PREFIX_MOD_3_0FC7_REG_6): New.
290 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
291 (prefix_table): Replace PREFIX_0FC7_REG_6 with
292 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
293 PREFIX_MOD_3_0FC7_REG_7.
294 (mod_table): Replace PREFIX_0FC7_REG_6 with
295 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
296 PREFIX_MOD_3_0FC7_REG_7.
298 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
300 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
301 (PREFIX_MANDATORY_REPNZ): Likewise.
302 (PREFIX_MANDATORY_DATA): Likewise.
303 (PREFIX_MANDATORY_ADDR): Likewise.
304 (PREFIX_MANDATORY_LOCK): Likewise.
305 (PREFIX_MANDATORY): Likewise.
306 (PREFIX_UD_SHIFT): Set to 8
307 (PREFIX_UD_REPZ): Updated.
308 (PREFIX_UD_REPNZ): Likewise.
309 (PREFIX_UD_DATA): Likewise.
310 (PREFIX_UD_ADDR): Likewise.
311 (PREFIX_UD_LOCK): Likewise.
312 (PREFIX_IGNORED_SHIFT): New.
313 (PREFIX_IGNORED_REPZ): Likewise.
314 (PREFIX_IGNORED_REPNZ): Likewise.
315 (PREFIX_IGNORED_DATA): Likewise.
316 (PREFIX_IGNORED_ADDR): Likewise.
317 (PREFIX_IGNORED_LOCK): Likewise.
318 (PREFIX_OPCODE): Likewise.
319 (PREFIX_IGNORED): Likewise.
320 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
321 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
322 (three_byte_table): Likewise.
323 (mod_table): Likewise.
324 (mandatory_prefix): Renamed to ...
325 (prefix_requirement): This.
326 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
327 Update PREFIX_90 entry.
328 (get_valid_dis386): Check prefix_requirement to see if a prefix
330 (print_insn): Replace mandatory_prefix with prefix_requirement.
332 2015-04-15 Renlin Li <renlin.li@arm.com>
334 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
335 use it for ssat and ssat16.
336 (print_insn_thumb32): Add handle case for 'D' control code.
338 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
339 H.J. Lu <hongjiu.lu@intel.com>
341 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
342 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
343 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
344 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
345 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
346 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
347 Fill prefix_requirement field.
348 (struct dis386): Add prefix_requirement field.
349 (dis386): Fill prefix_requirement field.
350 (dis386_twobyte): Ditto.
351 (twobyte_has_mandatory_prefix_: Remove.
352 (reg_table): Fill prefix_requirement field.
353 (prefix_table): Ditto.
354 (x86_64_table): Ditto.
355 (three_byte_table): Ditto.
358 (vex_len_table): Ditto.
359 (vex_w_table): Ditto.
362 (print_insn): Use prefix_requirement.
363 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
364 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
367 2015-03-30 Mike Frysinger <vapier@gentoo.org>
369 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
371 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
373 * Makefile.in: Regenerated.
375 2015-03-25 Anton Blanchard <anton@samba.org>
377 * ppc-dis.c (disassemble_init_powerpc): Only initialise
378 powerpc_opcd_indices and vle_opcd_indices once.
380 2015-03-25 Anton Blanchard <anton@samba.org>
382 * ppc-opc.c (powerpc_opcodes): Add slbfee.
384 2015-03-24 Terry Guo <terry.guo@arm.com>
386 * arm-dis.c (opcode32): Updated to use new arm feature struct.
387 (opcode16): Likewise.
388 (coprocessor_opcodes): Replace bit with feature struct.
389 (neon_opcodes): Likewise.
390 (arm_opcodes): Likewise.
391 (thumb_opcodes): Likewise.
392 (thumb32_opcodes): Likewise.
393 (print_insn_coprocessor): Likewise.
394 (print_insn_arm): Likewise.
395 (select_arm_features): Follow new feature struct.
397 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
399 * i386-dis.c (rm_table): Add clzero.
400 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
401 Add CPU_CLZERO_FLAGS.
402 (cpu_flags): Add CpuCLZERO.
403 * i386-opc.h: Add CpuCLZERO.
404 * i386-opc.tbl: Add clzero.
405 * i386-init.h: Re-generated.
406 * i386-tbl.h: Re-generated.
408 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
410 * mips-opc.c (decode_mips_operand): Fix constraint issues
411 with u and y operands.
413 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
415 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
417 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
419 * s390-opc.c: Add new IBM z13 instructions.
420 * s390-opc.txt: Likewise.
422 2015-03-10 Renlin Li <renlin.li@arm.com>
424 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
425 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
427 * aarch64-asm-2.c: Regenerate.
428 * aarch64-dis-2.c: Likewise.
429 * aarch64-opc-2.c: Likewise.
431 2015-03-03 Jiong Wang <jiong.wang@arm.com>
433 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
435 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
437 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
439 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
440 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
442 2015-02-23 Vinay <Vinay.G@kpit.com>
444 * rl78-decode.opc (MOV): Added space between two operands for
445 'mov' instruction in index addressing mode.
446 * rl78-decode.c: Regenerate.
448 2015-02-19 Pedro Alves <palves@redhat.com>
450 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
452 2015-02-10 Pedro Alves <palves@redhat.com>
453 Tom Tromey <tromey@redhat.com>
455 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
456 microblaze_and, microblaze_xor.
457 * microblaze-opc.h (opcodes): Adjust.
459 2015-01-28 James Bowman <james.bowman@ftdichip.com>
461 * Makefile.am: Add FT32 files.
462 * configure.ac: Handle FT32.
463 * disassemble.c (disassembler): Call print_insn_ft32.
464 * ft32-dis.c: New file.
465 * ft32-opc.c: New file.
466 * Makefile.in: Regenerate.
467 * configure: Regenerate.
468 * po/POTFILES.in: Regenerate.
470 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
472 * nds32-asm.c (keyword_sr): Add new system registers.
474 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
476 * s390-dis.c (s390_extract_operand): Support vector register
478 (s390_print_insn_with_opcode): Support new operands types and add
479 new handling of optional operands.
480 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
481 and include opcode/s390.h instead.
482 (struct op_struct): New field `flags'.
483 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
484 (dumpTable): Dump flags.
485 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
487 * s390-opc.c: Add new operands types, instruction formats, and
489 (s390_opformats): Add new formats for .insn.
490 * s390-opc.txt: Add new instructions.
492 2015-01-01 Alan Modra <amodra@gmail.com>
494 Update year range in copyright notice of all files.
496 For older changes see ChangeLog-2014
498 Copyright (C) 2015 Free Software Foundation, Inc.
500 Copying and distribution of this file, with or without modification,
501 are permitted in any medium without royalty provided the copyright
502 notice and this notice are preserved.
508 version-control: never