1 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
3 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
5 (parse_mips_ase_option): Handle -Mginv option.
6 (print_mips_disassembler_options): Document -Mginv.
7 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
9 (mips_opcodes): Define ginvi and ginvt.
11 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
12 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
14 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
15 * mips-opc.c (CRC, CRC64): New macros.
16 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
17 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
20 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
23 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
24 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
26 2018-06-06 Alan Modra <amodra@gmail.com>
28 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
29 setjmp. Move init for some other vars later too.
31 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
33 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
34 (dis_private): Add new fields for property section tracking.
35 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
36 (xtensa_instruction_fits): New functions.
37 (fetch_data): Bump minimal fetch size to 4.
38 (print_insn_xtensa): Make struct dis_private static.
39 Load and prepare property table on section change.
40 Don't disassemble literals. Don't disassemble instructions that
41 cross property table boundaries.
43 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
45 * configure: Regenerated.
47 2018-06-01 Jan Beulich <jbeulich@suse.com>
49 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
50 * i386-tbl.h: Re-generate.
52 2018-06-01 Jan Beulich <jbeulich@suse.com>
54 * i386-opc.tbl (sldt, str): Add NoRex64.
55 * i386-tbl.h: Re-generate.
57 2018-06-01 Jan Beulich <jbeulich@suse.com>
59 * i386-opc.tbl (invpcid): Add Oword.
60 * i386-tbl.h: Re-generate.
62 2018-06-01 Alan Modra <amodra@gmail.com>
64 * sysdep.h (_bfd_error_handler): Don't declare.
65 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
66 * rl78-decode.opc: Likewise.
67 * msp430-decode.c: Regenerate.
68 * rl78-decode.c: Regenerate.
70 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
72 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
73 * i386-init.h : Regenerated.
75 2018-05-25 Alan Modra <amodra@gmail.com>
77 * Makefile.in: Regenerate.
78 * po/POTFILES.in: Regenerate.
80 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
82 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
83 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
84 (insert_bab, extract_bab, insert_btab, extract_btab,
85 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
86 (BAT, BBA VBA RBS XB6S): Delete macros.
87 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
88 (BB, BD, RBX, XC6): Update for new macros.
89 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
90 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
91 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
92 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
94 2018-05-18 John Darrington <john@darrington.wattle.id.au>
96 * Makefile.am: Add support for s12z architecture.
97 * configure.ac: Likewise.
98 * disassemble.c: Likewise.
99 * disassemble.h: Likewise.
100 * Makefile.in: Regenerate.
101 * configure: Regenerate.
102 * s12z-dis.c: New file.
105 2018-05-18 Alan Modra <amodra@gmail.com>
107 * nfp-dis.c: Don't #include libbfd.h.
108 (init_nfp3200_priv): Use bfd_get_section_contents.
109 (nit_nfp6000_mecsr_sec): Likewise.
111 2018-05-17 Nick Clifton <nickc@redhat.com>
113 * po/zh_CN.po: Updated simplified Chinese translation.
115 2018-05-16 Tamar Christina <tamar.christina@arm.com>
118 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
119 * aarch64-dis-2.c: Regenerate.
121 2018-05-15 Tamar Christina <tamar.christina@arm.com>
124 * aarch64-asm.c (opintl.h): Include.
125 (aarch64_ins_sysreg): Enforce read/write constraints.
126 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
127 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
128 (F_REG_READ, F_REG_WRITE): New.
129 * aarch64-opc.c (aarch64_print_operand): Generate notes for
131 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
132 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
133 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
134 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
135 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
136 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
137 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
138 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
139 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
140 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
141 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
142 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
143 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
144 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
145 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
146 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
147 msr (F_SYS_WRITE), mrs (F_SYS_READ).
149 2018-05-15 Tamar Christina <tamar.christina@arm.com>
152 * aarch64-dis.c (no_notes: New.
153 (parse_aarch64_dis_option): Support notes.
154 (aarch64_decode_insn, print_operands): Likewise.
155 (print_aarch64_disassembler_options): Document notes.
156 * aarch64-opc.c (aarch64_print_operand): Support notes.
158 2018-05-15 Tamar Christina <tamar.christina@arm.com>
161 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
162 and take error struct.
163 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
164 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
165 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
166 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
167 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
168 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
169 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
170 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
171 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
172 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
173 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
174 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
175 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
176 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
177 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
178 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
179 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
180 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
181 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
182 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
183 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
184 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
185 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
186 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
187 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
188 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
189 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
190 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
191 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
192 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
193 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
194 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
195 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
196 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
197 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
198 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
199 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
200 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
201 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
202 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
203 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
204 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
205 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
206 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
207 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
208 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
209 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
210 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
211 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
212 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
213 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
214 (determine_disassembling_preference, aarch64_decode_insn,
215 print_insn_aarch64_word, print_insn_data): Take errors struct.
216 (print_insn_aarch64): Use errors.
217 * aarch64-asm-2.c: Regenerate.
218 * aarch64-dis-2.c: Regenerate.
219 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
220 boolean in aarch64_insert_operan.
221 (print_operand_extractor): Likewise.
222 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
224 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
226 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
228 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
230 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
232 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
234 * cr16-opc.c (cr16_instruction): Comment typo fix.
235 * hppa-dis.c (print_insn_hppa): Likewise.
237 2018-05-08 Jim Wilson <jimw@sifive.com>
239 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
240 (match_c_slli64, match_srxi_as_c_srxi): New.
241 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
242 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
243 <c.slli, c.srli, c.srai>: Use match_s_slli.
244 <c.slli64, c.srli64, c.srai64>: New.
246 2018-05-08 Alan Modra <amodra@gmail.com>
248 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
249 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
250 partition opcode space for index lookup.
252 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
254 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
255 <insn_length>: ...with this. Update usage.
256 Remove duplicate call to *info->memory_error_func.
258 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
259 H.J. Lu <hongjiu.lu@intel.com>
261 * i386-dis.c (Gva): New.
262 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
263 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
264 (prefix_table): New instructions (see prefix above).
265 (mod_table): New instructions (see prefix above).
266 (OP_G): Handle va_mode.
267 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
269 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
270 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
271 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
272 * i386-opc.tbl: Add movidir{i,64b}.
273 * i386-init.h: Regenerated.
274 * i386-tbl.h: Likewise.
276 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
278 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
280 * i386-opc.h (AddrPrefixOp0): Renamed to ...
281 (AddrPrefixOpReg): This.
282 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
283 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
285 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
287 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
288 (vle_num_opcodes): Likewise.
289 (spe2_num_opcodes): Likewise.
290 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
292 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
293 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
296 2018-05-01 Tamar Christina <tamar.christina@arm.com>
298 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
300 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
302 Makefile.am: Added nfp-dis.c.
303 configure.ac: Added bfd_nfp_arch.
304 disassemble.h: Added print_insn_nfp prototype.
305 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
306 nfp-dis.c: New, for NFP support.
307 po/POTFILES.in: Added nfp-dis.c to the list.
308 Makefile.in: Regenerate.
309 configure: Regenerate.
311 2018-04-26 Jan Beulich <jbeulich@suse.com>
313 * i386-opc.tbl: Fold various non-memory operand AVX512VL
314 templates into their base ones.
315 * i386-tlb.h: Re-generate.
317 2018-04-26 Jan Beulich <jbeulich@suse.com>
319 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
320 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
321 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
322 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
323 * i386-init.h: Re-generate.
325 2018-04-26 Jan Beulich <jbeulich@suse.com>
327 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
328 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
329 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
330 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
332 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
334 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
336 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
337 cpuregzmm, and cpuregmask.
338 * i386-init.h: Re-generate.
339 * i386-tbl.h: Re-generate.
341 2018-04-26 Jan Beulich <jbeulich@suse.com>
343 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
344 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
345 * i386-init.h: Re-generate.
347 2018-04-26 Jan Beulich <jbeulich@suse.com>
349 * i386-gen.c (VexImmExt): Delete.
350 * i386-opc.h (VexImmExt, veximmext): Delete.
351 * i386-opc.tbl: Drop all VexImmExt uses.
352 * i386-tlb.h: Re-generate.
354 2018-04-25 Jan Beulich <jbeulich@suse.com>
356 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
358 * i386-tlb.h: Re-generate.
360 2018-04-25 Tamar Christina <tamar.christina@arm.com>
362 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
364 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
366 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
368 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
369 (cpu_flags): Add CpuCLDEMOTE.
370 * i386-init.h: Regenerate.
371 * i386-opc.h (enum): Add CpuCLDEMOTE,
372 (i386_cpu_flags): Add cpucldemote.
373 * i386-opc.tbl: Add cldemote.
374 * i386-tbl.h: Regenerate.
376 2018-04-16 Alan Modra <amodra@gmail.com>
378 * Makefile.am: Remove sh5 and sh64 support.
379 * configure.ac: Likewise.
380 * disassemble.c: Likewise.
381 * disassemble.h: Likewise.
382 * sh-dis.c: Likewise.
383 * sh64-dis.c: Delete.
384 * sh64-opc.c: Delete.
385 * sh64-opc.h: Delete.
386 * Makefile.in: Regenerate.
387 * configure: Regenerate.
388 * po/POTFILES.in: Regenerate.
390 2018-04-16 Alan Modra <amodra@gmail.com>
392 * Makefile.am: Remove w65 support.
393 * configure.ac: Likewise.
394 * disassemble.c: Likewise.
395 * disassemble.h: Likewise.
398 * Makefile.in: Regenerate.
399 * configure: Regenerate.
400 * po/POTFILES.in: Regenerate.
402 2018-04-16 Alan Modra <amodra@gmail.com>
404 * configure.ac: Remove we32k support.
405 * configure: Regenerate.
407 2018-04-16 Alan Modra <amodra@gmail.com>
409 * Makefile.am: Remove m88k support.
410 * configure.ac: Likewise.
411 * disassemble.c: Likewise.
412 * disassemble.h: Likewise.
413 * m88k-dis.c: Delete.
414 * Makefile.in: Regenerate.
415 * configure: Regenerate.
416 * po/POTFILES.in: Regenerate.
418 2018-04-16 Alan Modra <amodra@gmail.com>
420 * Makefile.am: Remove i370 support.
421 * configure.ac: Likewise.
422 * disassemble.c: Likewise.
423 * disassemble.h: Likewise.
424 * i370-dis.c: Delete.
425 * i370-opc.c: Delete.
426 * Makefile.in: Regenerate.
427 * configure: Regenerate.
428 * po/POTFILES.in: Regenerate.
430 2018-04-16 Alan Modra <amodra@gmail.com>
432 * Makefile.am: Remove h8500 support.
433 * configure.ac: Likewise.
434 * disassemble.c: Likewise.
435 * disassemble.h: Likewise.
436 * h8500-dis.c: Delete.
437 * h8500-opc.h: Delete.
438 * Makefile.in: Regenerate.
439 * configure: Regenerate.
440 * po/POTFILES.in: Regenerate.
442 2018-04-16 Alan Modra <amodra@gmail.com>
444 * configure.ac: Remove tahoe support.
445 * configure: Regenerate.
447 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
449 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
451 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
453 * i386-tbl.h: Regenerated.
455 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
457 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
458 PREFIX_MOD_1_0FAE_REG_6.
460 (OP_E_register): Use va_mode.
461 * i386-dis-evex.h (prefix_table):
462 New instructions (see prefixes above).
463 * i386-gen.c (cpu_flag_init): Add WAITPKG.
464 (cpu_flags): Likewise.
465 * i386-opc.h (enum): Likewise.
466 (i386_cpu_flags): Likewise.
467 * i386-opc.tbl: Add umonitor, umwait, tpause.
468 * i386-init.h: Regenerate.
469 * i386-tbl.h: Likewise.
471 2018-04-11 Alan Modra <amodra@gmail.com>
473 * opcodes/i860-dis.c: Delete.
474 * opcodes/i960-dis.c: Delete.
475 * Makefile.am: Remove i860 and i960 support.
476 * configure.ac: Likewise.
477 * disassemble.c: Likewise.
478 * disassemble.h: Likewise.
479 * Makefile.in: Regenerate.
480 * configure: Regenerate.
481 * po/POTFILES.in: Regenerate.
483 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
486 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
488 (print_insn): Clear vex instead of vex.evex.
490 2018-04-04 Nick Clifton <nickc@redhat.com>
492 * po/es.po: Updated Spanish translation.
494 2018-03-28 Jan Beulich <jbeulich@suse.com>
496 * i386-gen.c (opcode_modifiers): Delete VecESize.
497 * i386-opc.h (VecESize): Delete.
498 (struct i386_opcode_modifier): Delete vecesize.
499 * i386-opc.tbl: Drop VecESize.
500 * i386-tlb.h: Re-generate.
502 2018-03-28 Jan Beulich <jbeulich@suse.com>
504 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
505 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
506 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
507 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
508 * i386-tlb.h: Re-generate.
510 2018-03-28 Jan Beulich <jbeulich@suse.com>
512 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
514 * i386-tlb.h: Re-generate.
516 2018-03-28 Jan Beulich <jbeulich@suse.com>
518 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
519 (vex_len_table): Drop Y for vcvt*2si.
520 (putop): Replace plain 'Y' handling by abort().
522 2018-03-28 Nick Clifton <nickc@redhat.com>
525 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
526 instructions with only a base address register.
527 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
528 handle AARHC64_OPND_SVE_ADDR_R.
529 (aarch64_print_operand): Likewise.
530 * aarch64-asm-2.c: Regenerate.
531 * aarch64_dis-2.c: Regenerate.
532 * aarch64-opc-2.c: Regenerate.
534 2018-03-22 Jan Beulich <jbeulich@suse.com>
536 * i386-opc.tbl: Drop VecESize from register only insn forms and
537 memory forms not allowing broadcast.
538 * i386-tlb.h: Re-generate.
540 2018-03-22 Jan Beulich <jbeulich@suse.com>
542 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
543 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
544 sha256*): Drop Disp<N>.
546 2018-03-22 Jan Beulich <jbeulich@suse.com>
548 * i386-dis.c (EbndS, bnd_swap_mode): New.
549 (prefix_table): Use EbndS.
550 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
551 * i386-opc.tbl (bndmov): Move misplaced Load.
552 * i386-tlb.h: Re-generate.
554 2018-03-22 Jan Beulich <jbeulich@suse.com>
556 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
557 templates allowing memory operands and folded ones for register
559 * i386-tlb.h: Re-generate.
561 2018-03-22 Jan Beulich <jbeulich@suse.com>
563 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
564 256-bit templates. Drop redundant leftover Disp<N>.
565 * i386-tlb.h: Re-generate.
567 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
569 * riscv-opc.c (riscv_insn_types): New.
571 2018-03-13 Nick Clifton <nickc@redhat.com>
573 * po/pt_BR.po: Updated Brazilian Portuguese translation.
575 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
577 * i386-opc.tbl: Add Optimize to clr.
578 * i386-tbl.h: Regenerated.
580 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
582 * i386-gen.c (opcode_modifiers): Remove OldGcc.
583 * i386-opc.h (OldGcc): Removed.
584 (i386_opcode_modifier): Remove oldgcc.
585 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
586 instructions for old (<= 2.8.1) versions of gcc.
587 * i386-tbl.h: Regenerated.
589 2018-03-08 Jan Beulich <jbeulich@suse.com>
591 * i386-opc.h (EVEXDYN): New.
592 * i386-opc.tbl: Fold various AVX512VL templates.
593 * i386-tlb.h: Re-generate.
595 2018-03-08 Jan Beulich <jbeulich@suse.com>
597 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
598 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
599 vpexpandd, vpexpandq): Fold AFX512VF templates.
600 * i386-tlb.h: Re-generate.
602 2018-03-08 Jan Beulich <jbeulich@suse.com>
604 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
605 Fold 128- and 256-bit VEX-encoded templates.
606 * i386-tlb.h: Re-generate.
608 2018-03-08 Jan Beulich <jbeulich@suse.com>
610 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
611 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
612 vpexpandd, vpexpandq): Fold AVX512F templates.
613 * i386-tlb.h: Re-generate.
615 2018-03-08 Jan Beulich <jbeulich@suse.com>
617 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
618 64-bit templates. Drop Disp<N>.
619 * i386-tlb.h: Re-generate.
621 2018-03-08 Jan Beulich <jbeulich@suse.com>
623 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
624 and 256-bit templates.
625 * i386-tlb.h: Re-generate.
627 2018-03-08 Jan Beulich <jbeulich@suse.com>
629 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
630 * i386-tlb.h: Re-generate.
632 2018-03-08 Jan Beulich <jbeulich@suse.com>
634 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
636 * i386-tlb.h: Re-generate.
638 2018-03-08 Jan Beulich <jbeulich@suse.com>
640 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
641 * i386-tlb.h: Re-generate.
643 2018-03-08 Jan Beulich <jbeulich@suse.com>
645 * i386-gen.c (opcode_modifiers): Delete FloatD.
646 * i386-opc.h (FloatD): Delete.
647 (struct i386_opcode_modifier): Delete floatd.
648 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
650 * i386-tlb.h: Re-generate.
652 2018-03-08 Jan Beulich <jbeulich@suse.com>
654 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
656 2018-03-08 Jan Beulich <jbeulich@suse.com>
658 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
659 * i386-tlb.h: Re-generate.
661 2018-03-08 Jan Beulich <jbeulich@suse.com>
663 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
665 * i386-tlb.h: Re-generate.
667 2018-03-07 Alan Modra <amodra@gmail.com>
669 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
671 * disassemble.h (print_insn_rs6000): Delete.
672 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
673 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
674 (print_insn_rs6000): Delete.
676 2018-03-03 Alan Modra <amodra@gmail.com>
678 * sysdep.h (opcodes_error_handler): Define.
679 (_bfd_error_handler): Declare.
680 * Makefile.am: Remove stray #.
681 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
683 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
684 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
685 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
686 opcodes_error_handler to print errors. Standardize error messages.
687 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
688 and include opintl.h.
689 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
690 * i386-gen.c: Standardize error messages.
691 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
692 * Makefile.in: Regenerate.
693 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
694 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
695 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
696 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
697 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
698 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
699 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
700 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
701 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
702 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
703 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
704 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
705 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
707 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
709 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
710 vpsub[bwdq] instructions.
711 * i386-tbl.h: Regenerated.
713 2018-03-01 Alan Modra <amodra@gmail.com>
715 * configure.ac (ALL_LINGUAS): Sort.
716 * configure: Regenerate.
718 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
720 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
721 macro by assignements.
723 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
726 * i386-gen.c (opcode_modifiers): Add Optimize.
727 * i386-opc.h (Optimize): New enum.
728 (i386_opcode_modifier): Add optimize.
729 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
730 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
731 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
732 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
733 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
735 * i386-tbl.h: Regenerated.
737 2018-02-26 Alan Modra <amodra@gmail.com>
739 * crx-dis.c (getregliststring): Allocate a large enough buffer
740 to silence false positive gcc8 warning.
742 2018-02-22 Shea Levy <shea@shealevy.com>
744 * disassemble.c (ARCH_riscv): Define if ARCH_all.
746 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
748 * i386-opc.tbl: Add {rex},
749 * i386-tbl.h: Regenerated.
751 2018-02-20 Maciej W. Rozycki <macro@mips.com>
753 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
754 (mips16_opcodes): Replace `M' with `m' for "restore".
756 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
758 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
760 2018-02-13 Maciej W. Rozycki <macro@mips.com>
762 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
763 variable to `function_index'.
765 2018-02-13 Nick Clifton <nickc@redhat.com>
768 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
769 about truncation of printing.
771 2018-02-12 Henry Wong <henry@stuffedcow.net>
773 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
775 2018-02-05 Nick Clifton <nickc@redhat.com>
777 * po/pt_BR.po: Updated Brazilian Portuguese translation.
779 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
781 * i386-dis.c (enum): Add pconfig.
782 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
783 (cpu_flags): Add CpuPCONFIG.
784 * i386-opc.h (enum): Add CpuPCONFIG.
785 (i386_cpu_flags): Add cpupconfig.
786 * i386-opc.tbl: Add PCONFIG instruction.
787 * i386-init.h: Regenerate.
788 * i386-tbl.h: Likewise.
790 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
792 * i386-dis.c (enum): Add PREFIX_0F09.
793 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
794 (cpu_flags): Add CpuWBNOINVD.
795 * i386-opc.h (enum): Add CpuWBNOINVD.
796 (i386_cpu_flags): Add cpuwbnoinvd.
797 * i386-opc.tbl: Add WBNOINVD instruction.
798 * i386-init.h: Regenerate.
799 * i386-tbl.h: Likewise.
801 2018-01-17 Jim Wilson <jimw@sifive.com>
803 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
805 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
807 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
808 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
809 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
810 (cpu_flags): Add CpuIBT, CpuSHSTK.
811 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
812 (i386_cpu_flags): Add cpuibt, cpushstk.
813 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
814 * i386-init.h: Regenerate.
815 * i386-tbl.h: Likewise.
817 2018-01-16 Nick Clifton <nickc@redhat.com>
819 * po/pt_BR.po: Updated Brazilian Portugese translation.
820 * po/de.po: Updated German translation.
822 2018-01-15 Jim Wilson <jimw@sifive.com>
824 * riscv-opc.c (match_c_nop): New.
825 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
827 2018-01-15 Nick Clifton <nickc@redhat.com>
829 * po/uk.po: Updated Ukranian translation.
831 2018-01-13 Nick Clifton <nickc@redhat.com>
833 * po/opcodes.pot: Regenerated.
835 2018-01-13 Nick Clifton <nickc@redhat.com>
837 * configure: Regenerate.
839 2018-01-13 Nick Clifton <nickc@redhat.com>
843 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
845 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
846 * i386-tbl.h: Regenerate.
848 2018-01-10 Jan Beulich <jbeulich@suse.com>
850 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
851 * i386-tbl.h: Re-generate.
853 2018-01-10 Jan Beulich <jbeulich@suse.com>
855 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
856 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
857 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
858 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
859 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
860 Disp8MemShift of AVX512VL forms.
861 * i386-tbl.h: Re-generate.
863 2018-01-09 Jim Wilson <jimw@sifive.com>
865 * riscv-dis.c (maybe_print_address): If base_reg is zero,
866 then the hi_addr value is zero.
868 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
870 * arm-dis.c (arm_opcodes): Add csdb.
871 (thumb32_opcodes): Add csdb.
873 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
875 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
876 * aarch64-asm-2.c: Regenerate.
877 * aarch64-dis-2.c: Regenerate.
878 * aarch64-opc-2.c: Regenerate.
880 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
883 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
884 Remove AVX512 vmovd with 64-bit operands.
885 * i386-tbl.h: Regenerated.
887 2018-01-05 Jim Wilson <jimw@sifive.com>
889 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
892 2018-01-03 Alan Modra <amodra@gmail.com>
894 Update year range in copyright notice of all files.
896 2018-01-02 Jan Beulich <jbeulich@suse.com>
898 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
899 and OPERAND_TYPE_REGZMM entries.
901 For older changes see ChangeLog-2017
903 Copyright (C) 2018 Free Software Foundation, Inc.
905 Copying and distribution of this file, with or without modification,
906 are permitted in any medium without royalty provided the copyright
907 notice and this notice are preserved.
913 version-control: never