opcodes/ChangeLog

   1 2015-10-02  Yao Qi  <yao.qi@linaro.org>
   2
   3         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
   4         (print_insn_aarch64_word): Caller updated.
   5
   6 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
   7
   8         * s390-mkopc.c (main): Parse htm and vx flag.
   9         * s390-opc.txt: Mark instructions from the hardware transactional
  10         memory and vector facilities with the "htm"/"vx" flag.
  11
  12 2015-09-28  Nick Clifton  <nickc@redhat.com>
  13
  14         * po/de.po: Updated German translation.
  15
  16 2015-09-28  Tom Rix  <tom@bumblecow.com>
  17
  18         * ppc-opc.c (PPC500): Mark some opcodes as invalid
  19
  20 2015-09-23  Nick Clifton  <nickc@redhat.com>
  21
  22         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
  23         function.
  24         * tic30-dis.c (print_branch): Likewise.
  25         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
  26         value before left shifting.
  27         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
  28         * hppa-dis.c (print_insn_hppa): Likewise.
  29         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
  30         array.
  31         * msp430-dis.c (msp430_singleoperand): Likewise.
  32         (msp430_doubleoperand): Likewise.
  33         (print_insn_msp430): Likewise.
  34         * nds32-asm.c (parse_operand): Likewise.
  35         * sh-opc.h (MASK): Likewise.
  36         * v850-dis.c (get_operand_value): Likewise.
  37
  38 2015-09-22  Nick Clifton  <nickc@redhat.com>
  39
  40         * rx-decode.opc (bwl): Use RX_Bad_Size.
  41         (sbwl): Likewise.
  42         (ubwl): Likewise.  Rename to ubw.
  43         (uBWL): Rename to uBW.
  44         Replace all references to uBWL with uBW.
  45         * rx-decode.c: Regenerate.
  46         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
  47         (opsize_names): Likewise.
  48         (print_insn_rx): Detect and report RX_Bad_Size.
  49
  50 2015-09-22  Anton Blanchard  <anton@samba.org>
  51
  52         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
  53
  54 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
  55
  56         * sparc-dis.c (print_insn_sparc): Handle the privileged register
  57         %pmcdper.
  58
  59 2015-08-24  Jan Stancek  <jstancek@redhat.com>
  60
  61         * i386-dis.c (print_insn): Fix decoding of three byte operands.
  62
  63 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
  64
  65         PR binutils/18257
  66         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
  67         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
  68         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
  69         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
  70         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
  71         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
  72         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
  73         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
  74         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
  75         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
  76         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
  77         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
  78         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
  79         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
  80         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
  81         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
  82         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
  83         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
  84         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
  85         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
  86         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
  87         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
  88         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
  89         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
  90         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
  91         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
  92         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
  93         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
  94         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
  95         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
  96         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
  97         (vex_w_table): Replace terminals with MOD_TABLE entries for
  98         most of mask instructions.
  99
 100 2015-08-17  Alan Modra  <amodra@gmail.com>
 101
 102         * cgen.sh: Trim trailing space from cgen output.
 103         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 104         (print_dis_table): Likewise.
 105         * opc2c.c (dump_lines): Likewise.
 106         (orig_filename): Warning fix.
 107         * ia64-asmtab.c: Regenerate.
 108
 109 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 110
 111         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 112         and higher with ARM instruction set will now mark the 26-bit
 113         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 114         (arm_opcodes): Fix for unpredictable nop being recognized as a
 115         teq.
 116
 117 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 118
 119         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 120         based on 'or' is first.
 121         * mips-opc.c (mips_builtin_opcodes): Ditto.
 122
 123 2015-08-11  Nick Clifton  <nickc@redhat.com>
 124
 125         PR 18800
 126         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 127         instruction.
 128
 129 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 130
 131         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 132
 133 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 134
 135         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 136         * i386-init.h: Regenerated.
 137
 138 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 139
 140         PR binutils/13571
 141         * i386-dis.c (MOD_0FC3): New.
 142         (PREFIX_0FC3): Renamed to ...
 143         (PREFIX_MOD_0_0FC3): This.
 144         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 145         (prefix_table): Replace Ma with Ev on movntiS.
 146         (mod_table): Add MOD_0FC3.
 147
 148 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 149
 150         * configure: Regenerated.
 151
 152 2015-07-23  Alan Modra  <amodra@gmail.com>
 153
 154         PR 18708
 155         * i386-dis.c (get64): Avoid signed integer overflow.
 156
 157 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 158
 159         PR binutils/18631
 160         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 161         "EXEvexHalfBcstXmmq" for the second operand.
 162         (EVEX_W_0F79_P_2): Likewise.
 163         (EVEX_W_0F7A_P_2): Likewise.
 164         (EVEX_W_0F7B_P_2): Likewise.
 165
 166 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 167
 168         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 169         float bitfield format.
 170         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 171         quarter float bitfield format.
 172
 173 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 174
 175         * configure: Regenerated.
 176
 177 2015-07-03  Alan Modra  <amodra@gmail.com>
 178
 179         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 180         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 181         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 182
 183 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 184             Cesar Philippidis  <cesar@codesourcery.com>
 185
 186         * nios2-dis.c (nios2_extract_opcode): New.
 187         (nios2_disassembler_state): New.
 188         (nios2_find_opcode_hash): Use mach parameter to select correct
 189         disassembler state.
 190         (nios2_print_insn_arg): Extend to support new R2 argument letters
 191         and formats.
 192         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 193         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 194         (NIOS2_NUM_OPCODES): Rename to...
 195         (NIOS2_NUM_R1_OPCODES): This.
 196         (nios2_r2_opcodes): New.
 197         (NIOS2_NUM_R2_OPCODES): New.
 198         (nios2_num_r2_opcodes): New.
 199         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 200         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 201         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 202         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 203         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 204
 205 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 206
 207         * i386-dis.c (OP_Mwaitx): New.
 208         (rm_table): Add monitorx/mwaitx.
 209         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 210         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 211         (operand_type_init): Add CpuMWAITX.
 212         * i386-opc.h (CpuMWAITX): New.
 213         (i386_cpu_flags): Add cpumwaitx.
 214         * i386-opc.tbl: Add monitorx and mwaitx.
 215         * i386-init.h: Regenerated.
 216         * i386-tbl.h: Likewise.
 217
 218 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 219
 220         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 221         (insert_esync): New function.
 222         (LS, WC): Use insert_ls.
 223         (ESYNC): Use insert_esync.
 224
 225 2015-06-22  Nick Clifton  <nickc@redhat.com>
 226
 227         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 228         requested region lies beyond it.
 229         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 230         looking for 32-bit insns.
 231         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 232         data.
 233         * sh-dis.c (print_insn_sh): Likewise.
 234         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 235         blocks of instructions.
 236         * vax-dis.c (print_insn_vax): Check that the requested address
 237         does not clash with the stop_vma.
 238
 239 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 240
 241         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 242         * ppc-opc.c (FXM4): Add non-zero optional value.
 243         (TBR): Likewise.
 244         (SXL): Likewise.
 245         (insert_fxm): Handle new default operand value.
 246         (extract_fxm): Likewise.
 247         (insert_tbr): Likewise.
 248         (extract_tbr): Likewise.
 249
 250 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 251
 252         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 253
 254 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 255
 256         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 257
 258 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 259
 260         * ppc-opc.c: Add comment accidentally removed by old commit.
 261         (MTMSRD_L): Delete.
 262
 263 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 264
 265         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 266
 267 2015-06-04  Nick Clifton  <nickc@redhat.com>
 268
 269         PR 18474
 270         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 271
 272 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 273
 274         * arm-dis.c (arm_opcodes): Add "setpan".
 275         (thumb_opcodes): Add "setpan".
 276
 277 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 278
 279         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 280         macros.
 281
 282 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 283
 284         * aarch64-tbl.h (aarch64_feature_rdma): New.
 285         (RDMA): New.
 286         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 287         * aarch64-asm-2.c: Regenerate.
 288         * aarch64-dis-2.c: Regenerate.
 289         * aarch64-opc-2.c: Regenerate.
 290
 291 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 292
 293         * aarch64-tbl.h (aarch64_feature_lor): New.
 294         (LOR): New.
 295         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 296         "stllrb", "stllrh".
 297         * aarch64-asm-2.c: Regenerate.
 298         * aarch64-dis-2.c: Regenerate.
 299         * aarch64-opc-2.c: Regenerate.
 300
 301 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 302
 303         * aarch64-opc.c (F_ARCHEXT): New.
 304         (aarch64_sys_regs): Add "pan".
 305         (aarch64_sys_reg_supported_p): New.
 306         (aarch64_pstatefields): Add "pan".
 307         (aarch64_pstatefield_supported_p): New.
 308
 309 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-tbl.h: Regenerate.
 312
 313 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 314
 315         * i386-dis.c (print_insn): Swap rounding mode specifier and
 316         general purpose register in Intel mode.
 317
 318 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 319
 320         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 321         * i386-tbl.h: Regenerate.
 322
 323 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 324
 325         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 326         * i386-init.h: Regenerated.
 327
 328 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 329
 330         PR binutis/18386
 331         * i386-dis.c: Add comments for '@'.
 332         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 333         (enum x86_64_isa): New.
 334         (isa64): Likewise.
 335         (print_i386_disassembler_options): Add amd64 and intel64.
 336         (print_insn): Handle amd64 and intel64.
 337         (putop): Handle '@'.
 338         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 339         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 340         * i386-opc.h (AMD64): New.
 341         (CpuIntel64): Likewise.
 342         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 343         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 344         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 345         * i386-init.h: Regenerated.
 346         * i386-tbl.h: Likewise.
 347
 348 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 349
 350         * ppc-opc.c (IH) New define.
 351         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 352         <tlbie>: Add RS operand for POWER7.
 353         <slbia>: Add IH operand for POWER6.
 354
 355 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 356
 357         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 358         direct branch.
 359         (jmp): Likewise.
 360         * i386-tbl.h: Regenerated.
 361
 362 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 363
 364         * configure.ac: Support bfd_iamcu_arch.
 365         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 366         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 367         CPU_IAMCU_COMPAT_FLAGS.
 368         (cpu_flags): Add CpuIAMCU.
 369         * i386-opc.h (CpuIAMCU): New.
 370         (i386_cpu_flags): Add cpuiamcu.
 371         * configure: Regenerated.
 372         * i386-init.h: Likewise.
 373         * i386-tbl.h: Likewise.
 374
 375 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 376
 377         PR binutis/18386
 378         * i386-dis.c (X86_64_E8): New.
 379         (X86_64_E9): Likewise.
 380         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 381         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 382         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 383         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 384         (putop): Handle '^'.
 385         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 386         REX_W.
 387
 388 2015-04-30  DJ Delorie  <dj@redhat.com>
 389
 390         * disassemble.c (disassembler): Choose suitable disassembler based
 391         on E_ABI.
 392         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 393         it to decode mul/div insns.
 394         * rl78-decode.c: Regenerate.
 395         * rl78-dis.c (print_insn_rl78): Rename to...
 396         (print_insn_rl78_common): ...this, take ISA parameter.
 397         (print_insn_rl78): New.
 398         (print_insn_rl78_g10): New.
 399         (print_insn_rl78_g13): New.
 400         (print_insn_rl78_g14): New.
 401         (rl78_get_disassembler): New.
 402
 403 2015-04-29  Nick Clifton  <nickc@redhat.com>
 404
 405         * po/fr.po: Updated French translation.
 406
 407 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 408
 409         * ppc-opc.c (DCBT_EO): New define.
 410         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 411         <lharx>: Likewise.
 412         <stbcx.>: Likewise.
 413         <sthcx.>: Likewise.
 414         <waitrsv>: Do not enable for POWER7 and later.
 415         <waitimpl>: Likewise.
 416         <dcbt>: Default to the two operand form of the instruction for all
 417         "old" cpus.  For "new" cpus, use the operand ordering that matches
 418         whether the cpu is server or embedded.
 419         <dcbtst>: Likewise.
 420
 421 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 422
 423         * s390-opc.c: New instruction type VV0UU2.
 424         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 425         and WFC.
 426
 427 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 428
 429         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 430         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 431         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 432         (vfpclasspd, vfpclassps): Add %XZ.
 433
 434 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 435
 436         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 437         (PREFIX_UD_REPZ): Likewise.
 438         (PREFIX_UD_REPNZ): Likewise.
 439         (PREFIX_UD_DATA): Likewise.
 440         (PREFIX_UD_ADDR): Likewise.
 441         (PREFIX_UD_LOCK): Likewise.
 442
 443 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 444
 445         * i386-dis.c (prefix_requirement): Removed.
 446         (print_insn): Don't set prefix_requirement.  Check
 447         dp->prefix_requirement instead of prefix_requirement.
 448
 449 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 450
 451         PR binutils/17898
 452         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 453         (PREFIX_MOD_0_0FC7_REG_6): This.
 454         (PREFIX_MOD_3_0FC7_REG_6): New.
 455         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 456         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 457         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 458         PREFIX_MOD_3_0FC7_REG_7.
 459         (mod_table): Replace PREFIX_0FC7_REG_6 with
 460         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 461         PREFIX_MOD_3_0FC7_REG_7.
 462
 463 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 464
 465         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 466         (PREFIX_MANDATORY_REPNZ): Likewise.
 467         (PREFIX_MANDATORY_DATA): Likewise.
 468         (PREFIX_MANDATORY_ADDR): Likewise.
 469         (PREFIX_MANDATORY_LOCK): Likewise.
 470         (PREFIX_MANDATORY): Likewise.
 471         (PREFIX_UD_SHIFT): Set to 8
 472         (PREFIX_UD_REPZ): Updated.
 473         (PREFIX_UD_REPNZ): Likewise.
 474         (PREFIX_UD_DATA): Likewise.
 475         (PREFIX_UD_ADDR): Likewise.
 476         (PREFIX_UD_LOCK): Likewise.
 477         (PREFIX_IGNORED_SHIFT): New.
 478         (PREFIX_IGNORED_REPZ): Likewise.
 479         (PREFIX_IGNORED_REPNZ): Likewise.
 480         (PREFIX_IGNORED_DATA): Likewise.
 481         (PREFIX_IGNORED_ADDR): Likewise.
 482         (PREFIX_IGNORED_LOCK): Likewise.
 483         (PREFIX_OPCODE): Likewise.
 484         (PREFIX_IGNORED): Likewise.
 485         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 486         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 487         (three_byte_table): Likewise.
 488         (mod_table): Likewise.
 489         (mandatory_prefix): Renamed to ...
 490         (prefix_requirement): This.
 491         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 492         Update PREFIX_90 entry.
 493         (get_valid_dis386): Check prefix_requirement to see if a prefix
 494         should be ignored.
 495         (print_insn): Replace mandatory_prefix with prefix_requirement.
 496
 497 2015-04-15  Renlin Li  <renlin.li@arm.com>
 498
 499         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 500         use it for ssat and ssat16.
 501         (print_insn_thumb32): Add handle case for 'D' control code.
 502
 503 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 504             H.J. Lu  <hongjiu.lu@intel.com>
 505
 506         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 507         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 508         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 509         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 510         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 511         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 512         Fill prefix_requirement field.
 513         (struct dis386): Add prefix_requirement field.
 514         (dis386): Fill prefix_requirement field.
 515         (dis386_twobyte): Ditto.
 516         (twobyte_has_mandatory_prefix_: Remove.
 517         (reg_table): Fill prefix_requirement field.
 518         (prefix_table): Ditto.
 519         (x86_64_table): Ditto.
 520         (three_byte_table): Ditto.
 521         (xop_table): Ditto.
 522         (vex_table): Ditto.
 523         (vex_len_table): Ditto.
 524         (vex_w_table): Ditto.
 525         (mod_table): Ditto.
 526         (bad_opcode): Ditto.
 527         (print_insn): Use prefix_requirement.
 528         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 529         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 530         (float_reg): Ditto.
 531
 532 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 533
 534         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 535
 536 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 537
 538         * Makefile.in: Regenerated.
 539
 540 2015-03-25  Anton Blanchard  <anton@samba.org>
 541
 542         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 543         powerpc_opcd_indices and vle_opcd_indices once.
 544
 545 2015-03-25  Anton Blanchard  <anton@samba.org>
 546
 547         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 548
 549 2015-03-24  Terry Guo  <terry.guo@arm.com>
 550
 551         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 552         (opcode16): Likewise.
 553         (coprocessor_opcodes): Replace bit with feature struct.
 554         (neon_opcodes): Likewise.
 555         (arm_opcodes): Likewise.
 556         (thumb_opcodes): Likewise.
 557         (thumb32_opcodes): Likewise.
 558         (print_insn_coprocessor): Likewise.
 559         (print_insn_arm): Likewise.
 560         (select_arm_features): Follow new feature struct.
 561
 562 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 563
 564         * i386-dis.c (rm_table): Add clzero.
 565         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 566         Add CPU_CLZERO_FLAGS.
 567         (cpu_flags): Add CpuCLZERO.
 568         * i386-opc.h: Add CpuCLZERO.
 569         * i386-opc.tbl: Add clzero.
 570         * i386-init.h: Re-generated.
 571         * i386-tbl.h: Re-generated.
 572
 573 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 574
 575         * mips-opc.c (decode_mips_operand): Fix constraint issues
 576         with u and y operands.
 577
 578 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 579
 580         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 581
 582 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 583
 584         * s390-opc.c: Add new IBM z13 instructions.
 585         * s390-opc.txt: Likewise.
 586
 587 2015-03-10  Renlin Li  <renlin.li@arm.com>
 588
 589         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 590         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 591         related alias.
 592         * aarch64-asm-2.c: Regenerate.
 593         * aarch64-dis-2.c: Likewise.
 594         * aarch64-opc-2.c: Likewise.
 595
 596 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 597
 598         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 599
 600 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 601
 602         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 603         arch_sh_up.
 604         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 605         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 606
 607 2015-02-23  Vinay  <Vinay.G@kpit.com>
 608
 609         * rl78-decode.opc (MOV): Added space between two operands for
 610         'mov' instruction in index addressing mode.
 611         * rl78-decode.c: Regenerate.
 612
 613 2015-02-19  Pedro Alves  <palves@redhat.com>
 614
 615         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 616
 617 2015-02-10  Pedro Alves  <palves@redhat.com>
 618             Tom Tromey  <tromey@redhat.com>
 619
 620         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 621         microblaze_and, microblaze_xor.
 622         * microblaze-opc.h (opcodes): Adjust.
 623
 624 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 625
 626         * Makefile.am: Add FT32 files.
 627         * configure.ac: Handle FT32.
 628         * disassemble.c (disassembler): Call print_insn_ft32.
 629         * ft32-dis.c: New file.
 630         * ft32-opc.c: New file.
 631         * Makefile.in: Regenerate.
 632         * configure: Regenerate.
 633         * po/POTFILES.in: Regenerate.
 634
 635 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 636
 637         * nds32-asm.c (keyword_sr): Add new system registers.
 638
 639 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 640
 641         * s390-dis.c (s390_extract_operand): Support vector register
 642         operands.
 643         (s390_print_insn_with_opcode): Support new operands types and add
 644         new handling of optional operands.
 645         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 646         and include opcode/s390.h instead.
 647         (struct op_struct): New field `flags'.
 648         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 649         (dumpTable): Dump flags.
 650         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 651         string.
 652         * s390-opc.c: Add new operands types, instruction formats, and
 653         instruction masks.
 654         (s390_opformats): Add new formats for .insn.
 655         * s390-opc.txt: Add new instructions.
 656
 657 2015-01-01  Alan Modra  <amodra@gmail.com>
 658
 659         Update year range in copyright notice of all files.
 660
 661 For older changes see ChangeLog-2014
 662 \f
 663 Copyright (C) 2015 Free Software Foundation, Inc.
 664
 665 Copying and distribution of this file, with or without modification,
 666 are permitted in any medium without royalty provided the copyright
 667 notice and this notice are preserved.
 668
 669 Local Variables:
 670 mode: change-log
 671 left-margin: 8
 672 fill-column: 74
 673 version-control: never
 674 End: