[AArch64] Add SVE system registers
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
2
3 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
4 (aarch64_sys_reg_supported_p): Handle them.
5
6 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
7
8 * arc-opc.c (UIMM6_20R): Define.
9 (SIMM12_20): Use above.
10 (SIMM12_20R): Define.
11 (SIMM3_5_S): Use above.
12 (UIMM7_A32_11R_S): Define.
13 (UIMM7_9_S): Use above.
14 (UIMM3_13R_S): Define.
15 (SIMM11_A32_7_S): Use above.
16 (SIMM9_8R): Define.
17 (UIMM10_A32_8_S): Use above.
18 (UIMM8_8R_S): Define.
19 (W6): Use above.
20 (arc_relax_opcodes): Use all above defines.
21
22 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
23
24 * arc-regs.h: Distinguish some of the registers different on
25 ARC700 and HS38 cpus.
26
27 2017-02-14 Alan Modra <amodra@gmail.com>
28
29 PR 21118
30 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
31 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
32
33 2017-02-11 Stafford Horne <shorne@gmail.com>
34 Alan Modra <amodra@gmail.com>
35
36 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
37 Use insn_bytes_value and insn_int_value directly instead. Don't
38 free allocated memory until function exit.
39
40 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
41
42 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
43
44 2017-02-03 Nick Clifton <nickc@redhat.com>
45
46 PR 21096
47 * aarch64-opc.c (print_register_list): Ensure that the register
48 list index will fir into the tb buffer.
49 (print_register_offset_address): Likewise.
50 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
51
52 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
53
54 PR 21056
55 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
56 instructions when the previous fetch packet ends with a 32-bit
57 instruction.
58
59 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
60
61 * pru-opc.c: Remove vague reference to a future GDB port.
62
63 2017-01-20 Nick Clifton <nickc@redhat.com>
64
65 * po/ga.po: Updated Irish translation.
66
67 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
68
69 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
70
71 2017-01-13 Yao Qi <yao.qi@linaro.org>
72
73 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
74 if FETCH_DATA returns 0.
75 (m68k_scan_mask): Likewise.
76 (print_insn_m68k): Update code to handle -1 return value.
77
78 2017-01-13 Yao Qi <yao.qi@linaro.org>
79
80 * m68k-dis.c (enum print_insn_arg_error): New.
81 (NEXTBYTE): Replace -3 with
82 PRINT_INSN_ARG_MEMORY_ERROR.
83 (NEXTULONG): Likewise.
84 (NEXTSINGLE): Likewise.
85 (NEXTDOUBLE): Likewise.
86 (NEXTDOUBLE): Likewise.
87 (NEXTPACKED): Likewise.
88 (FETCH_ARG): Likewise.
89 (FETCH_DATA): Update comments.
90 (print_insn_arg): Update comments. Replace magic numbers with
91 enum.
92 (match_insn_m68k): Likewise.
93
94 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
95
96 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
97 * i386-dis-evex.h (evex_table): Updated.
98 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
99 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
100 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
101 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
102 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
103 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
104 * i386-init.h: Regenerate.
105 * i386-tbl.h: Ditto.
106
107 2017-01-12 Yao Qi <yao.qi@linaro.org>
108
109 * msp430-dis.c (msp430_singleoperand): Return -1 if
110 msp430dis_opcode_signed returns false.
111 (msp430_doubleoperand): Likewise.
112 (msp430_branchinstr): Return -1 if
113 msp430dis_opcode_unsigned returns false.
114 (msp430x_calla_instr): Likewise.
115 (print_insn_msp430): Likewise.
116
117 2017-01-05 Nick Clifton <nickc@redhat.com>
118
119 PR 20946
120 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
121 could not be matched.
122 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
123 NULL.
124
125 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
126
127 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
128 (aarch64_opcode_table): Use RCPC_INSN.
129
130 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
131
132 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
133 extension.
134 * riscv-opcodes/all-opcodes: Likewise.
135
136 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
137
138 * riscv-dis.c (print_insn_args): Add fall through comment.
139
140 2017-01-03 Nick Clifton <nickc@redhat.com>
141
142 * po/sr.po: New Serbian translation.
143 * configure.ac (ALL_LINGUAS): Add sr.
144 * configure: Regenerate.
145
146 2017-01-02 Alan Modra <amodra@gmail.com>
147
148 * epiphany-desc.h: Regenerate.
149 * epiphany-opc.h: Regenerate.
150 * fr30-desc.h: Regenerate.
151 * fr30-opc.h: Regenerate.
152 * frv-desc.h: Regenerate.
153 * frv-opc.h: Regenerate.
154 * ip2k-desc.h: Regenerate.
155 * ip2k-opc.h: Regenerate.
156 * iq2000-desc.h: Regenerate.
157 * iq2000-opc.h: Regenerate.
158 * lm32-desc.h: Regenerate.
159 * lm32-opc.h: Regenerate.
160 * m32c-desc.h: Regenerate.
161 * m32c-opc.h: Regenerate.
162 * m32r-desc.h: Regenerate.
163 * m32r-opc.h: Regenerate.
164 * mep-desc.h: Regenerate.
165 * mep-opc.h: Regenerate.
166 * mt-desc.h: Regenerate.
167 * mt-opc.h: Regenerate.
168 * or1k-desc.h: Regenerate.
169 * or1k-opc.h: Regenerate.
170 * xc16x-desc.h: Regenerate.
171 * xc16x-opc.h: Regenerate.
172 * xstormy16-desc.h: Regenerate.
173 * xstormy16-opc.h: Regenerate.
174
175 2017-01-02 Alan Modra <amodra@gmail.com>
176
177 Update year range in copyright notice of all files.
178
179 For older changes see ChangeLog-2016
180 \f
181 Copyright (C) 2017 Free Software Foundation, Inc.
182
183 Copying and distribution of this file, with or without modification,
184 are permitted in any medium without royalty provided the copyright
185 notice and this notice are preserved.
186
187 Local Variables:
188 mode: change-log
189 left-margin: 8
190 fill-column: 74
191 version-control: never
192 End:
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