1 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
3 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
4 * configure: Regenerated.
5 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
7 (HFILES): Add bpf-desc.h and bpf-opc.h.
8 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
9 bpf-ibld.c and bpf-opc.c.
11 * Makefile.in: Regenerated.
12 * disassemble.c (ARCH_bpf): Define.
13 (disassembler): Add case for bfd_arch_bpf.
14 (disassemble_init_for_target): Likewise.
15 (enum epbf_isa_attr): Define.
16 * disassemble.h: extern print_insn_bpf.
17 * bpf-asm.c: Generated.
18 * bpf-opc.h: Likewise.
19 * bpf-opc.c: Likewise.
20 * bpf-ibld.c: Likewise.
21 * bpf-dis.c: Likewise.
22 * bpf-desc.h: Likewise.
23 * bpf-desc.c: Likewise.
25 2019-05-21 Sudakshina Das <sudi.das@arm.com>
27 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
28 and VMSR with the new operands.
30 2019-05-21 Sudakshina Das <sudi.das@arm.com>
32 * arm-dis.c (enum mve_instructions): New enum
33 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
35 (mve_opcodes): New instructions as above.
36 (is_mve_encoding_conflict): Add cases for csinc, csinv,
38 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
40 2019-05-21 Sudakshina Das <sudi.das@arm.com>
42 * arm-dis.c (emun mve_instructions): Updated for new instructions.
43 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
44 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
45 uqshl, urshrl and urshr.
46 (is_mve_okay_in_it): Add new instructions to TRUE list.
47 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
48 (print_insn_mve): Updated to accept new %j,
49 %<bitfield>m and %<bitfield>n patterns.
51 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
53 * mips-opc.c (mips_builtin_opcodes): Change source register
56 2019-05-20 Nick Clifton <nickc@redhat.com>
58 * po/fr.po: Updated French translation.
60 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
61 Michael Collison <michael.collison@arm.com>
63 * arm-dis.c (thumb32_opcodes): Add new instructions.
64 (enum mve_instructions): Likewise.
65 (enum mve_undefined): Add new reasons.
66 (is_mve_encoding_conflict): Handle new instructions.
67 (is_mve_undefined): Likewise.
68 (is_mve_unpredictable): Likewise.
69 (print_mve_undefined): Likewise.
70 (print_mve_size): Likewise.
72 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
73 Michael Collison <michael.collison@arm.com>
75 * arm-dis.c (thumb32_opcodes): Add new instructions.
76 (enum mve_instructions): Likewise.
77 (is_mve_encoding_conflict): Handle new instructions.
78 (is_mve_undefined): Likewise.
79 (is_mve_unpredictable): Likewise.
80 (print_mve_size): Likewise.
82 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
83 Michael Collison <michael.collison@arm.com>
85 * arm-dis.c (thumb32_opcodes): Add new instructions.
86 (enum mve_instructions): Likewise.
87 (is_mve_encoding_conflict): Likewise.
88 (is_mve_unpredictable): Likewise.
89 (print_mve_size): Likewise.
91 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
92 Michael Collison <michael.collison@arm.com>
94 * arm-dis.c (thumb32_opcodes): Add new instructions.
95 (enum mve_instructions): Likewise.
96 (is_mve_encoding_conflict): Handle new instructions.
97 (is_mve_undefined): Likewise.
98 (is_mve_unpredictable): Likewise.
99 (print_mve_size): Likewise.
101 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
102 Michael Collison <michael.collison@arm.com>
104 * arm-dis.c (thumb32_opcodes): Add new instructions.
105 (enum mve_instructions): Likewise.
106 (is_mve_encoding_conflict): Handle new instructions.
107 (is_mve_undefined): Likewise.
108 (is_mve_unpredictable): Likewise.
109 (print_mve_size): Likewise.
110 (print_insn_mve): Likewise.
112 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
113 Michael Collison <michael.collison@arm.com>
115 * arm-dis.c (thumb32_opcodes): Add new instructions.
116 (print_insn_thumb32): Handle new instructions.
118 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
119 Michael Collison <michael.collison@arm.com>
121 * arm-dis.c (enum mve_instructions): Add new instructions.
122 (enum mve_undefined): Add new reasons.
123 (is_mve_encoding_conflict): Handle new instructions.
124 (is_mve_undefined): Likewise.
125 (is_mve_unpredictable): Likewise.
126 (print_mve_undefined): Likewise.
127 (print_mve_size): Likewise.
128 (print_mve_shift_n): Likewise.
129 (print_insn_mve): Likewise.
131 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
132 Michael Collison <michael.collison@arm.com>
134 * arm-dis.c (enum mve_instructions): Add new instructions.
135 (is_mve_encoding_conflict): Handle new instructions.
136 (is_mve_unpredictable): Likewise.
137 (print_mve_rotate): Likewise.
138 (print_mve_size): Likewise.
139 (print_insn_mve): Likewise.
141 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
142 Michael Collison <michael.collison@arm.com>
144 * arm-dis.c (enum mve_instructions): Add new instructions.
145 (is_mve_encoding_conflict): Handle new instructions.
146 (is_mve_unpredictable): Likewise.
147 (print_mve_size): Likewise.
148 (print_insn_mve): Likewise.
150 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
151 Michael Collison <michael.collison@arm.com>
153 * arm-dis.c (enum mve_instructions): Add new instructions.
154 (enum mve_undefined): Add new reasons.
155 (is_mve_encoding_conflict): Handle new instructions.
156 (is_mve_undefined): Likewise.
157 (is_mve_unpredictable): Likewise.
158 (print_mve_undefined): Likewise.
159 (print_mve_size): Likewise.
160 (print_insn_mve): Likewise.
162 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
163 Michael Collison <michael.collison@arm.com>
165 * arm-dis.c (enum mve_instructions): Add new instructions.
166 (is_mve_encoding_conflict): Handle new instructions.
167 (is_mve_undefined): Likewise.
168 (is_mve_unpredictable): Likewise.
169 (print_mve_size): Likewise.
170 (print_insn_mve): Likewise.
172 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
173 Michael Collison <michael.collison@arm.com>
175 * arm-dis.c (enum mve_instructions): Add new instructions.
176 (enum mve_unpredictable): Add new reasons.
177 (enum mve_undefined): Likewise.
178 (is_mve_okay_in_it): Handle new isntructions.
179 (is_mve_encoding_conflict): Likewise.
180 (is_mve_undefined): Likewise.
181 (is_mve_unpredictable): Likewise.
182 (print_mve_vmov_index): Likewise.
183 (print_simd_imm8): Likewise.
184 (print_mve_undefined): Likewise.
185 (print_mve_unpredictable): Likewise.
186 (print_mve_size): Likewise.
187 (print_insn_mve): Likewise.
189 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
190 Michael Collison <michael.collison@arm.com>
192 * arm-dis.c (enum mve_instructions): Add new instructions.
193 (enum mve_unpredictable): Add new reasons.
194 (enum mve_undefined): Likewise.
195 (is_mve_encoding_conflict): Handle new instructions.
196 (is_mve_undefined): Likewise.
197 (is_mve_unpredictable): Likewise.
198 (print_mve_undefined): Likewise.
199 (print_mve_unpredictable): Likewise.
200 (print_mve_rounding_mode): Likewise.
201 (print_mve_vcvt_size): Likewise.
202 (print_mve_size): Likewise.
203 (print_insn_mve): Likewise.
205 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
206 Michael Collison <michael.collison@arm.com>
208 * arm-dis.c (enum mve_instructions): Add new instructions.
209 (enum mve_unpredictable): Add new reasons.
210 (enum mve_undefined): Likewise.
211 (is_mve_undefined): Handle new instructions.
212 (is_mve_unpredictable): Likewise.
213 (print_mve_undefined): Likewise.
214 (print_mve_unpredictable): Likewise.
215 (print_mve_size): Likewise.
216 (print_insn_mve): Likewise.
218 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
219 Michael Collison <michael.collison@arm.com>
221 * arm-dis.c (enum mve_instructions): Add new instructions.
222 (enum mve_undefined): Add new reasons.
223 (insns): Add new instructions.
224 (is_mve_encoding_conflict):
225 (print_mve_vld_str_addr): New print function.
226 (is_mve_undefined): Handle new instructions.
227 (is_mve_unpredictable): Likewise.
228 (print_mve_undefined): Likewise.
229 (print_mve_size): Likewise.
230 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
231 (print_insn_mve): Handle new operands.
233 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
234 Michael Collison <michael.collison@arm.com>
236 * arm-dis.c (enum mve_instructions): Add new instructions.
237 (enum mve_unpredictable): Add new reasons.
238 (is_mve_encoding_conflict): Handle new instructions.
239 (is_mve_unpredictable): Likewise.
240 (mve_opcodes): Add new instructions.
241 (print_mve_unpredictable): Handle new reasons.
242 (print_mve_register_blocks): New print function.
243 (print_mve_size): Handle new instructions.
244 (print_insn_mve): Likewise.
246 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
247 Michael Collison <michael.collison@arm.com>
249 * arm-dis.c (enum mve_instructions): Add new instructions.
250 (enum mve_unpredictable): Add new reasons.
251 (enum mve_undefined): Likewise.
252 (is_mve_encoding_conflict): Handle new instructions.
253 (is_mve_undefined): Likewise.
254 (is_mve_unpredictable): Likewise.
255 (coprocessor_opcodes): Move NEON VDUP from here...
256 (neon_opcodes): ... to here.
257 (mve_opcodes): Add new instructions.
258 (print_mve_undefined): Handle new reasons.
259 (print_mve_unpredictable): Likewise.
260 (print_mve_size): Handle new instructions.
261 (print_insn_neon): Handle vdup.
262 (print_insn_mve): Handle new operands.
264 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
265 Michael Collison <michael.collison@arm.com>
267 * arm-dis.c (enum mve_instructions): Add new instructions.
268 (enum mve_unpredictable): Add new values.
269 (mve_opcodes): Add new instructions.
270 (vec_condnames): New array with vector conditions.
271 (mve_predicatenames): New array with predicate suffixes.
272 (mve_vec_sizename): New array with vector sizes.
273 (enum vpt_pred_state): New enum with vector predication states.
274 (struct vpt_block): New struct type for vpt blocks.
275 (vpt_block_state): Global struct to keep track of state.
276 (mve_extract_pred_mask): New helper function.
277 (num_instructions_vpt_block): Likewise.
278 (mark_outside_vpt_block): Likewise.
279 (mark_inside_vpt_block): Likewise.
280 (invert_next_predicate_state): Likewise.
281 (update_next_predicate_state): Likewise.
282 (update_vpt_block_state): Likewise.
283 (is_vpt_instruction): Likewise.
284 (is_mve_encoding_conflict): Add entries for new instructions.
285 (is_mve_unpredictable): Likewise.
286 (print_mve_unpredictable): Handle new cases.
287 (print_instruction_predicate): Likewise.
288 (print_mve_size): New function.
289 (print_vec_condition): New function.
290 (print_insn_mve): Handle vpt blocks and new print operands.
292 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
294 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
295 8, 14 and 15 for Armv8.1-M Mainline.
297 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
298 Michael Collison <michael.collison@arm.com>
300 * arm-dis.c (enum mve_instructions): New enum.
301 (enum mve_unpredictable): Likewise.
302 (enum mve_undefined): Likewise.
303 (struct mopcode32): New struct.
304 (is_mve_okay_in_it): New function.
305 (is_mve_architecture): Likewise.
306 (arm_decode_field): Likewise.
307 (arm_decode_field_multiple): Likewise.
308 (is_mve_encoding_conflict): Likewise.
309 (is_mve_undefined): Likewise.
310 (is_mve_unpredictable): Likewise.
311 (print_mve_undefined): Likewise.
312 (print_mve_unpredictable): Likewise.
313 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
314 (print_insn_mve): New function.
315 (print_insn_thumb32): Handle MVE architecture.
316 (select_arm_features): Force thumb for Armv8.1-m Mainline.
318 2019-05-10 Nick Clifton <nickc@redhat.com>
321 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
322 end of the table prematurely.
324 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
326 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
329 2019-05-11 Alan Modra <amodra@gmail.com>
331 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
332 when -Mraw is in effect.
334 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
336 * aarch64-dis-2.c: Regenerate.
337 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
338 (OP_SVE_BBB): New variant set.
339 (OP_SVE_DDDD): New variant set.
340 (OP_SVE_HHH): New variant set.
341 (OP_SVE_HHHU): New variant set.
342 (OP_SVE_SSS): New variant set.
343 (OP_SVE_SSSU): New variant set.
344 (OP_SVE_SHH): New variant set.
345 (OP_SVE_SBBU): New variant set.
346 (OP_SVE_DSS): New variant set.
347 (OP_SVE_DHHU): New variant set.
348 (OP_SVE_VMV_HSD_BHS): New variant set.
349 (OP_SVE_VVU_HSD_BHS): New variant set.
350 (OP_SVE_VVVU_SD_BH): New variant set.
351 (OP_SVE_VVVU_BHSD): New variant set.
352 (OP_SVE_VVV_QHD_DBS): New variant set.
353 (OP_SVE_VVV_HSD_BHS): New variant set.
354 (OP_SVE_VVV_HSD_BHS2): New variant set.
355 (OP_SVE_VVV_BHS_HSD): New variant set.
356 (OP_SVE_VV_BHS_HSD): New variant set.
357 (OP_SVE_VVV_SD): New variant set.
358 (OP_SVE_VVU_BHS_HSD): New variant set.
359 (OP_SVE_VZVV_SD): New variant set.
360 (OP_SVE_VZVV_BH): New variant set.
361 (OP_SVE_VZV_SD): New variant set.
362 (aarch64_opcode_table): Add sve2 instructions.
364 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
366 * aarch64-asm-2.c: Regenerated.
367 * aarch64-dis-2.c: Regenerated.
368 * aarch64-opc-2.c: Regenerated.
369 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
370 for SVE_SHLIMM_UNPRED_22.
371 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
372 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
375 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
377 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
378 sve_size_tsz_bhs iclass encode.
379 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
380 sve_size_tsz_bhs iclass decode.
382 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
384 * aarch64-asm-2.c: Regenerated.
385 * aarch64-dis-2.c: Regenerated.
386 * aarch64-opc-2.c: Regenerated.
387 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
388 for SVE_Zm4_11_INDEX.
389 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
390 (fields): Handle SVE_i2h field.
391 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
392 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
394 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
396 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
397 sve_shift_tsz_bhsd iclass encode.
398 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
399 sve_shift_tsz_bhsd iclass decode.
401 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
403 * aarch64-asm-2.c: Regenerated.
404 * aarch64-dis-2.c: Regenerated.
405 * aarch64-opc-2.c: Regenerated.
406 * aarch64-asm.c (aarch64_ins_sve_shrimm):
407 (aarch64_encode_variant_using_iclass): Handle
408 sve_shift_tsz_hsd iclass encode.
409 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
410 sve_shift_tsz_hsd iclass decode.
411 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
412 for SVE_SHRIMM_UNPRED_22.
413 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
414 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
417 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
419 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
420 sve_size_013 iclass encode.
421 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
422 sve_size_013 iclass decode.
424 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
426 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
427 sve_size_bh iclass encode.
428 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
429 sve_size_bh iclass decode.
431 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
433 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
434 sve_size_sd2 iclass encode.
435 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
436 sve_size_sd2 iclass decode.
437 * aarch64-opc.c (fields): Handle SVE_sz2 field.
438 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
440 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
442 * aarch64-asm-2.c: Regenerated.
443 * aarch64-dis-2.c: Regenerated.
444 * aarch64-opc-2.c: Regenerated.
445 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
447 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
448 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
450 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
452 * aarch64-asm-2.c: Regenerated.
453 * aarch64-dis-2.c: Regenerated.
454 * aarch64-opc-2.c: Regenerated.
455 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
456 for SVE_Zm3_11_INDEX.
457 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
458 (fields): Handle SVE_i3l and SVE_i3h2 fields.
459 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
461 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
463 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
465 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
466 sve_size_hsd2 iclass encode.
467 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
468 sve_size_hsd2 iclass decode.
469 * aarch64-opc.c (fields): Handle SVE_size field.
470 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
472 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
474 * aarch64-asm-2.c: Regenerated.
475 * aarch64-dis-2.c: Regenerated.
476 * aarch64-opc-2.c: Regenerated.
477 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
479 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
480 (fields): Handle SVE_rot3 field.
481 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
482 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
484 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
486 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
489 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
492 (aarch64_feature_sve2, aarch64_feature_sve2aes,
493 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
494 aarch64_feature_sve2bitperm): New feature sets.
495 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
496 for feature set addresses.
497 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
498 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
500 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
501 Faraz Shahbazker <fshahbazker@wavecomp.com>
503 * mips-dis.c (mips_calculate_combination_ases): Add ISA
504 argument and set ASE_EVA_R6 appropriately.
505 (set_default_mips_dis_options): Pass ISA to above.
506 (parse_mips_dis_option): Likewise.
507 * mips-opc.c (EVAR6): New macro.
508 (mips_builtin_opcodes): Add llwpe, scwpe.
510 2019-05-01 Sudakshina Das <sudi.das@arm.com>
512 * aarch64-asm-2.c: Regenerated.
513 * aarch64-dis-2.c: Regenerated.
514 * aarch64-opc-2.c: Regenerated.
515 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
516 AARCH64_OPND_TME_UIMM16.
517 (aarch64_print_operand): Likewise.
518 * aarch64-tbl.h (QL_IMM_NIL): New.
521 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
523 2019-04-29 John Darrington <john@darrington.wattle.id.au>
525 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
527 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
528 Faraz Shahbazker <fshahbazker@wavecomp.com>
530 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
532 2019-04-24 John Darrington <john@darrington.wattle.id.au>
534 * s12z-opc.h: Add extern "C" bracketing to help
535 users who wish to use this interface in c++ code.
537 2019-04-24 John Darrington <john@darrington.wattle.id.au>
539 * s12z-opc.c (bm_decode): Handle bit map operations with the
542 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
544 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
545 specifier. Add entries for VLDR and VSTR of system registers.
546 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
547 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
548 of %J and %K format specifier.
550 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
552 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
553 Add new entries for VSCCLRM instruction.
554 (print_insn_coprocessor): Handle new %C format control code.
556 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
558 * arm-dis.c (enum isa): New enum.
559 (struct sopcode32): New structure.
560 (coprocessor_opcodes): change type of entries to struct sopcode32 and
561 set isa field of all current entries to ANY.
562 (print_insn_coprocessor): Change type of insn to struct sopcode32.
563 Only match an entry if its isa field allows the current mode.
565 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
567 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
569 (print_insn_thumb32): Add logic to print %n CLRM register list.
571 2019-04-15 Sudakshina Das <sudi.das@arm.com>
573 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
576 2019-04-15 Sudakshina Das <sudi.das@arm.com>
578 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
579 (print_insn_thumb32): Edit the switch case for %Z.
581 2019-04-15 Sudakshina Das <sudi.das@arm.com>
583 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
585 2019-04-15 Sudakshina Das <sudi.das@arm.com>
587 * arm-dis.c (thumb32_opcodes): New instruction bfl.
589 2019-04-15 Sudakshina Das <sudi.das@arm.com>
591 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
593 2019-04-15 Sudakshina Das <sudi.das@arm.com>
595 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
596 Arm register with r13 and r15 unpredictable.
597 (thumb32_opcodes): New instructions for bfx and bflx.
599 2019-04-15 Sudakshina Das <sudi.das@arm.com>
601 * arm-dis.c (thumb32_opcodes): New instructions for bf.
603 2019-04-15 Sudakshina Das <sudi.das@arm.com>
605 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
607 2019-04-15 Sudakshina Das <sudi.das@arm.com>
609 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
611 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
613 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
615 2019-04-12 John Darrington <john@darrington.wattle.id.au>
617 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
618 "optr". ("operator" is a reserved word in c++).
620 2019-04-11 Sudakshina Das <sudi.das@arm.com>
622 * aarch64-opc.c (aarch64_print_operand): Add case for
624 (verify_constraints): Likewise.
625 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
626 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
627 to accept Rt|SP as first operand.
628 (AARCH64_OPERANDS): Add new Rt_SP.
629 * aarch64-asm-2.c: Regenerated.
630 * aarch64-dis-2.c: Regenerated.
631 * aarch64-opc-2.c: Regenerated.
633 2019-04-11 Sudakshina Das <sudi.das@arm.com>
635 * aarch64-asm-2.c: Regenerated.
636 * aarch64-dis-2.c: Likewise.
637 * aarch64-opc-2.c: Likewise.
638 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
640 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
642 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
644 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
646 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
647 * i386-init.h: Regenerated.
649 2019-04-07 Alan Modra <amodra@gmail.com>
651 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
652 op_separator to control printing of spaces, comma and parens
653 rather than need_comma, need_paren and spaces vars.
655 2019-04-07 Alan Modra <amodra@gmail.com>
658 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
659 (print_insn_neon, print_insn_arm): Likewise.
661 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
663 * i386-dis-evex.h (evex_table): Updated to support BF16
665 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
666 and EVEX_W_0F3872_P_3.
667 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
668 (cpu_flags): Add bitfield for CpuAVX512_BF16.
669 * i386-opc.h (enum): Add CpuAVX512_BF16.
670 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
671 * i386-opc.tbl: Add AVX512 BF16 instructions.
672 * i386-init.h: Regenerated.
673 * i386-tbl.h: Likewise.
675 2019-04-05 Alan Modra <amodra@gmail.com>
677 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
678 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
679 to favour printing of "-" branch hint when using the "y" bit.
680 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
682 2019-04-05 Alan Modra <amodra@gmail.com>
684 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
685 opcode until first operand is output.
687 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
690 * ppc-opc.c (valid_bo_pre_v2): Add comments.
691 (valid_bo_post_v2): Add support for 'at' branch hints.
692 (insert_bo): Only error on branch on ctr.
693 (get_bo_hint_mask): New function.
694 (insert_boe): Add new 'branch_taken' formal argument. Add support
695 for inserting 'at' branch hints.
696 (extract_boe): Add new 'branch_taken' formal argument. Add support
697 for extracting 'at' branch hints.
698 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
699 (BOE): Delete operand.
700 (BOM, BOP): New operands.
702 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
703 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
704 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
705 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
706 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
707 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
708 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
709 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
710 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
711 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
712 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
713 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
714 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
715 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
716 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
717 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
718 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
719 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
720 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
721 bttarl+>: New extended mnemonics.
723 2019-03-28 Alan Modra <amodra@gmail.com>
726 * ppc-opc.c (BTF): Define.
727 (powerpc_opcodes): Use for mtfsb*.
728 * ppc-dis.c (print_insn_powerpc): Print fields with both
729 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
731 2019-03-25 Tamar Christina <tamar.christina@arm.com>
733 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
734 (mapping_symbol_for_insn): Implement new algorithm.
735 (print_insn): Remove duplicate code.
737 2019-03-25 Tamar Christina <tamar.christina@arm.com>
739 * aarch64-dis.c (print_insn_aarch64):
742 2019-03-25 Tamar Christina <tamar.christina@arm.com>
744 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
747 2019-03-25 Tamar Christina <tamar.christina@arm.com>
749 * aarch64-dis.c (last_stop_offset): New.
750 (print_insn_aarch64): Use stop_offset.
752 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
755 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
757 * i386-init.h: Regenerated.
759 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
762 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
763 vmovdqu16, vmovdqu32 and vmovdqu64.
764 * i386-tbl.h: Regenerated.
766 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
768 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
769 from vstrszb, vstrszh, and vstrszf.
771 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
773 * s390-opc.txt: Add instruction descriptions.
775 2019-02-08 Jim Wilson <jimw@sifive.com>
777 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
780 2019-02-07 Tamar Christina <tamar.christina@arm.com>
782 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
784 2019-02-07 Tamar Christina <tamar.christina@arm.com>
787 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
788 * aarch64-opc.c (verify_elem_sd): New.
789 (fields): Add FLD_sz entr.
790 * aarch64-tbl.h (_SIMD_INSN): New.
791 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
792 fmulx scalar and vector by element isns.
794 2019-02-07 Nick Clifton <nickc@redhat.com>
796 * po/sv.po: Updated Swedish translation.
798 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
800 * s390-mkopc.c (main): Accept arch13 as cpu string.
801 * s390-opc.c: Add new instruction formats and instruction opcode
803 * s390-opc.txt: Add new arch13 instructions.
805 2019-01-25 Sudakshina Das <sudi.das@arm.com>
807 * aarch64-tbl.h (QL_LDST_AT): Update macro.
808 (aarch64_opcode): Change encoding for stg, stzg
810 * aarch64-asm-2.c: Regenerated.
811 * aarch64-dis-2.c: Regenerated.
812 * aarch64-opc-2.c: Regenerated.
814 2019-01-25 Sudakshina Das <sudi.das@arm.com>
816 * aarch64-asm-2.c: Regenerated.
817 * aarch64-dis-2.c: Likewise.
818 * aarch64-opc-2.c: Likewise.
819 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
821 2019-01-25 Sudakshina Das <sudi.das@arm.com>
822 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
824 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
825 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
826 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
827 * aarch64-dis.h (ext_addr_simple_2): Likewise.
828 * aarch64-opc.c (operand_general_constraint_met_p): Remove
829 case for ldstgv_indexed.
830 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
831 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
832 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
833 * aarch64-asm-2.c: Regenerated.
834 * aarch64-dis-2.c: Regenerated.
835 * aarch64-opc-2.c: Regenerated.
837 2019-01-23 Nick Clifton <nickc@redhat.com>
839 * po/pt_BR.po: Updated Brazilian Portuguese translation.
841 2019-01-21 Nick Clifton <nickc@redhat.com>
843 * po/de.po: Updated German translation.
844 * po/uk.po: Updated Ukranian translation.
846 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
847 * mips-dis.c (mips_arch_choices): Fix typo in
848 gs464, gs464e and gs264e descriptors.
850 2019-01-19 Nick Clifton <nickc@redhat.com>
852 * configure: Regenerate.
853 * po/opcodes.pot: Regenerate.
855 2018-06-24 Nick Clifton <nickc@redhat.com>
859 2019-01-09 John Darrington <john@darrington.wattle.id.au>
861 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
863 -dis.c (opr_emit_disassembly): Do not omit an index if it is
866 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
868 * configure: Regenerate.
870 2019-01-07 Alan Modra <amodra@gmail.com>
872 * configure: Regenerate.
873 * po/POTFILES.in: Regenerate.
875 2019-01-03 John Darrington <john@darrington.wattle.id.au>
877 * s12z-opc.c: New file.
878 * s12z-opc.h: New file.
879 * s12z-dis.c: Removed all code not directly related to display
880 of instructions. Used the interface provided by the new files
882 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
883 * Makefile.in: Regenerate.
884 * configure.ac (bfd_s12z_arch): Correct the dependencies.
885 * configure: Regenerate.
887 2019-01-01 Alan Modra <amodra@gmail.com>
889 Update year range in copyright notice of all files.
891 For older changes see ChangeLog-2018
893 Copyright (C) 2019 Free Software Foundation, Inc.
895 Copying and distribution of this file, with or without modification,
896 are permitted in any medium without royalty provided the copyright
897 notice and this notice are preserved.
903 version-control: never