opcodes/ChangeLog

   1 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
   4         (PREFIX_EVEX_0F3A3F): Likewise.
   5         * i386-dis-evex.h (evex_table): Updated.
   6
   7 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
   8
   9         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
  10         VCLIPW.
  11
  12 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
  13             Konrad Eisele  <konrad@gaisler.com>
  14
  15         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
  16         bfd_mach_sparc.
  17         * sparc-opc.c (MASK_LEON): Define.
  18         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
  19         (letandleon): New macro.
  20         (v9andleon): Likewise.
  21         (sparc_opc): Add leon.
  22         (umac): Enable for letandleon.
  23         (smac): Likewise.
  24         (casa): Enable for v9andleon.
  25         (cas): Likewise.
  26         (casl): Likewise.
  27
  28 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
  29             Richard Sandiford  <rdsandiford@googlemail.com>
  30
  31         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
  32         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
  33         (print_vu0_channel): New function.
  34         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
  35         (print_insn_args): Handle '#'.
  36         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
  37         * mips-opc.c (mips_vu0_channel_mask): New constant.
  38         (decode_mips_operand): Handle new VU0 operand types.
  39         (VU0, VU0CH): New macros.
  40         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
  41         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
  42         Use "+6" rather than "G" for QMFC2 and QMTC2.
  43
  44 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
  45
  46         * mips-formats.h (PCREL): Reorder parameters and update the definition
  47         to match new mips_pcrel_operand layout.
  48         (JUMP, JALX, BRANCH): Update accordingly.
  49         * mips16-opc.c (decode_mips16_operand): Likewise.
  50
  51 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  52
  53         * micromips-opc.c (WR_s): Delete.
  54
  55 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  56
  57         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
  58         New macros.
  59         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
  60         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
  61         (mips_builtin_opcodes): Use the new position-based read-write flags
  62         instead of field-based ones.  Use UDI for "udi..." instructions.
  63         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
  64         New macros.
  65         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
  66         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
  67         (WR_SP, RD_16): New macros.
  68         (RD_SP): Redefine as an INSN2_* flag.
  69         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
  70         (mips16_opcodes): Use the new position-based read-write flags
  71         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
  72         pinfo2 field.
  73         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
  74         New macros.
  75         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
  76         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
  77         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
  78         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
  79         (micromips_opcodes): Use the new position-based read-write flags
  80         instead of field-based ones.
  81         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
  82         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
  83         of field-based flags.
  84
  85 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  86
  87         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
  88         (WR_SP): Replace with...
  89         (MOD_SP): ...this.
  90         (mips16_opcodes): Update accordingly.
  91         * mips-dis.c (print_insn_mips16): Likewise.
  92
  93 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  94
  95         * mips16-opc.c (mips16_opcodes): Reformat.
  96
  97 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  98
  99         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 100         for operands that are hard-coded to $0.
 101         * micromips-opc.c (micromips_opcodes): Likewise.
 102
 103 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 104
 105         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 106         for the single-operand forms of JALR and JALR.HB.
 107         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 108         and JALRS.HB.
 109
 110 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 111
 112         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 113         instructions.  Fix them to use WR_MACC instead of WR_CC and
 114         add missing RD_MACCs.
 115
 116 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 117
 118         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 119
 120 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 121
 122         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 123
 124 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 125             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 126             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 127             Sergey Lega  <sergey.s.lega@intel.com>
 128             Anna Tikhonova  <anna.tikhonova@intel.com>
 129             Ilya Tocar  <ilya.tocar@intel.com>
 130             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 131             Ilya Verbin  <ilya.verbin@intel.com>
 132             Kirill Yukhin  <kirill.yukhin@intel.com>
 133             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 134
 135         * i386-dis-evex.h: New.
 136         * i386-dis.c (OP_Rounding): New.
 137         (VPCMP_Fixup): New.
 138         (OP_Mask): New.
 139         (Rdq): New.
 140         (XMxmmq): New.
 141         (EXdScalarS): New.
 142         (EXymm): New.
 143         (EXEvexHalfBcstXmmq): New.
 144         (EXxmm_mdq): New.
 145         (EXEvexXGscat): New.
 146         (EXEvexXNoBcst): New.
 147         (VPCMP): New.
 148         (EXxEVexR): New.
 149         (EXxEVexS): New.
 150         (XMask): New.
 151         (MaskG): New.
 152         (MaskE): New.
 153         (MaskR): New.
 154         (MaskVex): New.
 155         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 156         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 157         evex_rounding_mode, evex_sae_mode, mask_mode.
 158         (USE_EVEX_TABLE): New.
 159         (EVEX_TABLE): New.
 160         (EVEX enum): New.
 161         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 162         REG_EVEX_0F38C7.
 163         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 164         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 165         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 166         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 167         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 168         MOD_EVEX_0F38C7_REG_6.
 169         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 170         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 171         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 172         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 173         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 174         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 175         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 176         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 177         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 178         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 179         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 180         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 181         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 182         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 183         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 184         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 185         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 186         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 187         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 188         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 189         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 190         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 191         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 192         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 193         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 194         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 195         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 196         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 197         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 198         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 199         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 200         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 201         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 202         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 203         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 204         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 205         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 206         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 207         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 208         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 209         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 210         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 211         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 212         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 213         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 214         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 215         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 216         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 217         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 218         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 219         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 220         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 221         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 222         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 223         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 224         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 225         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 226         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 227         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 228         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 229         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 230         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 231         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 232         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 233         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 234         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 235         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 236         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 237         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 238         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 239         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 240         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 241         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 242         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 243         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 244         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 245         PREFIX_EVEX_0F3A55.
 246         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 247         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 248         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 249         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 250         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 251         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 252         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 253         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 254         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 255         VEX_W_0F3A32_P_2_LEN_0.
 256         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 257         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 258         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 259         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 260         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 261         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 262         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 263         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 264         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 265         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 266         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 267         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 268         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 269         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 270         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 271         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 272         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 273         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 274         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 275         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 276         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 277         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 278         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 279         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 280         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 281         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 282         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 283         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 284         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 285         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 286         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 287         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 288         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 289         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 290         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 291         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 292         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 293         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 294         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 295         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 296         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 297         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 298         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 299         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 300         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 301         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 302         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 303         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 304         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 305         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 306         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 307         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 308         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 309         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 310         (struct vex): Add fields evex, r, v, mask_register_specifier,
 311         zeroing, ll, b.
 312         (intel_names_xmm): Add upper 16 registers.
 313         (att_names_xmm): Ditto.
 314         (intel_names_ymm): Ditto.
 315         (att_names_ymm): Ditto.
 316         (names_zmm): New.
 317         (intel_names_zmm): Ditto.
 318         (att_names_zmm): Ditto.
 319         (names_mask): Ditto.
 320         (intel_names_mask): Ditto.
 321         (att_names_mask): Ditto.
 322         (names_rounding): Ditto.
 323         (names_broadcast): Ditto.
 324         (x86_64_table): Add escape to evex-table.
 325         (reg_table): Include reg_table evex-entries from
 326         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 327         (prefix_table): Add entries for new instructions.
 328         (vex_table): Ditto.
 329         (vex_len_table): Ditto.
 330         (vex_w_table): Ditto.
 331         (mod_table): Ditto.
 332         (get_valid_dis386): Properly handle new instructions.
 333         (print_insn): Handle zmm and mask registers, print mask operand.
 334         (intel_operand_size): Support EVEX, new modes and sizes.
 335         (OP_E_register): Handle new modes.
 336         (OP_E_memory): Ditto.
 337         (OP_G): Ditto.
 338         (OP_XMM): Ditto.
 339         (OP_EX): Ditto.
 340         (OP_VEX): Ditto.
 341         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 342         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 343         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 344         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 345         CpuAVX512PF and CpuVREX.
 346         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 347         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 348         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 349         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 350         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 351         * i386-init.h: Regenerate.
 352         * i386-opc.h (CpuAVX512F): New.
 353         (CpuAVX512CD): New.
 354         (CpuAVX512ER): New.
 355         (CpuAVX512PF): New.
 356         (CpuVREX): New.
 357         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 358         cpuavx512pf and cpuvrex fields.
 359         (VecSIB): Add VecSIB512.
 360         (EVex): New.
 361         (Masking): New.
 362         (VecESize): New.
 363         (Broadcast): New.
 364         (StaticRounding): New.
 365         (SAE): New.
 366         (Disp8MemShift): New.
 367         (NoDefMask): New.
 368         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 369         staticrounding, sae, disp8memshift and nodefmask.
 370         (RegZMM): New.
 371         (Zmmword): Ditto.
 372         (Vec_Disp8): Ditto.
 373         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 374         fields.
 375         (RegVRex): New.
 376         * i386-opc.tbl: Add AVX512 instructions.
 377         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 378         registers, mask registers.
 379         * i386-tbl.h: Regenerate.
 380
 381 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 382
 383         PR gas/15220
 384         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 385         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 386
 387 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 388
 389         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 390         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 391         PREFIX_0F3ACC.
 392         (prefix_table): Updated.
 393         (three_byte_table): Likewise.
 394         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 395         (cpu_flags): Add CpuSHA.
 396         (i386_cpu_flags): Add cpusha.
 397         * i386-init.h: Regenerate.
 398         * i386-opc.h (CpuSHA): New.
 399         (CpuUnused): Restored.
 400         (i386_cpu_flags): Add cpusha.
 401         * i386-opc.tbl: Add SHA instructions.
 402         * i386-tbl.h: Regenerate.
 403
 404 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 405             Kirill Yukhin  <kirill.yukhin@intel.com>
 406             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 407
 408         * i386-dis.c (BND_Fixup): New.
 409         (Ebnd): New.
 410         (Ev_bnd): New.
 411         (Gbnd): New.
 412         (BND): New.
 413         (v_bnd_mode): New.
 414         (bnd_mode): New.
 415         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 416         MOD_0F1B_PREFIX_1.
 417         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 418         (dis tables): Replace XX with BND for near branch and call
 419         instructions.
 420         (prefix_table): Add new entries.
 421         (mod_table): Likewise.
 422         (names_bnd): New.
 423         (intel_names_bnd): New.
 424         (att_names_bnd): New.
 425         (BND_PREFIX): New.
 426         (prefix_name): Handle BND_PREFIX.
 427         (print_insn): Initialize names_bnd.
 428         (intel_operand_size): Handle new modes.
 429         (OP_E_register): Likewise.
 430         (OP_E_memory): Likewise.
 431         (OP_G): Likewise.
 432         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 433         (cpu_flags): Add CpuMPX.
 434         (operand_type_init): Add RegBND.
 435         (opcode_modifiers): Add BNDPrefixOk.
 436         (operand_types): Add RegBND.
 437         * i386-init.h: Regenerate.
 438         * i386-opc.h (CpuMPX): New.
 439         (CpuUnused): Comment out.
 440         (i386_cpu_flags): Add cpumpx.
 441         (BNDPrefixOk): New.
 442         (i386_opcode_modifier): Add bndprefixok.
 443         (RegBND): New.
 444         (i386_operand_type): Add regbnd.
 445         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 446         Add MPX instructions and bnd prefix.
 447         * i386-reg.tbl: Add bnd0-bnd3 registers.
 448         * i386-tbl.h: Regenerate.
 449
 450 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 451
 452         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 453         ATTRIBUTE_UNUSED.
 454
 455 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 456
 457         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 458         special rules.
 459         * Makefile.in: Regenerate.
 460         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 461         all fields.  Reformat.
 462
 463 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 464
 465         * mips16-opc.c: Include mips-formats.h.
 466         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 467         static arrays.
 468         (decode_mips16_operand): New function.
 469         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 470         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 471         Abort for OP_SAVE_RESTORE_LIST.
 472         (print_mips16_insn_arg): Change interface.  Use mips_operand
 473         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 474         (print_insn_mips16): ...here.  Call init_print_arg_state.
 475         Update the call to print_mips16_insn_arg.
 476
 477 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 478
 479         * mips-formats.h: New file.
 480         * mips-opc.c: Include mips-formats.h.
 481         (reg_0_map): New static array.
 482         (decode_mips_operand): New function.
 483         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 484         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 485         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 486         (int_c_map): New static arrays.
 487         (decode_micromips_operand): New function.
 488         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 489         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 490         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 491         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 492         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 493         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 494         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 495         (print_reg): New function.
 496         (mips_print_arg_state): New structure.
 497         (init_print_arg_state, print_insn_arg): New functions.
 498         (print_insn_args): Change interface and use mips_operand structures.
 499         Delete GET_OP_S.  Move GET_OP definition to...
 500         (print_insn_mips): ...here.  Update the call to print_insn_args.
 501         (print_insn_micromips): Use print_insn_args.
 502
 503 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 504
 505         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 506         in macros.
 507
 508 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 509
 510         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 511         ADDA.S, MULA.S and SUBA.S.
 512
 513 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 514
 515         PR gas/13572
 516         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 517         * i386-tbl.h: Regenerated.
 518
 519 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 520
 521         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 522         and SD A(B) macros up.
 523         * micromips-opc.c (micromips_opcodes): Likewise.
 524
 525 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 526
 527         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 528         instructions.
 529
 530 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 531
 532         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 533         MDMX-like instructions.
 534         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 535         printing "Q" operands for INSN_5400 instructions.
 536
 537 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 538
 539         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 540         "+S" for "cins".
 541         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 542         Combine cases.
 543
 544 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 545
 546         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 547         "jalx".
 548         * mips16-opc.c (mips16_opcodes): Likewise.
 549         * micromips-opc.c (micromips_opcodes): Likewise.
 550         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 551         (print_insn_mips16): Handle "+i".
 552         (print_insn_micromips): Likewise.  Conditionally preserve the
 553         ISA bit for "a" but not for "+i".
 554
 555 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 556
 557         * micromips-opc.c (WR_mhi): Rename to..
 558         (WR_mh): ...this.
 559         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 560         "mh,mi" with "mh".
 561         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 562         (micromips_to_32_reg_h_map1): ...this.
 563         (micromips_to_32_reg_i_map): Rename to...
 564         (micromips_to_32_reg_h_map2): ...this.
 565         (print_micromips_insn): Remove "mi" case.  Print both registers
 566         in the pair for "mh".
 567
 568 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 569
 570         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 571         * micromips-opc.c (micromips_opcodes): Likewise.
 572         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 573         and "+T" handling.  Check for a "0" suffix when deciding whether to
 574         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 575
 576 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 577
 578         * s390-opc.c (J12_12, J24_24): New macros.
 579         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 580         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 581         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 582
 583 2013-07-04  Alan Modra  <amodra@gmail.com>
 584
 585         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 586
 587 2013-06-26  Nick Clifton  <nickc@redhat.com>
 588
 589         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 590         field when checking for type 2 nop.
 591         * rx-decode.c: Regenerate.
 592
 593 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 594
 595         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 596         and "movep" macros.
 597
 598 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 599
 600         * mips-dis.c (is_mips16_plt_tail): New function.
 601         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 602         word.
 603         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 604
 605 2013-06-21  DJ Delorie  <dj@redhat.com>
 606
 607         * msp430-decode.opc: New.
 608         * msp430-decode.c: New/generated.
 609         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 610         (MAINTAINER_CLEANFILES): Likewise.
 611         Add rule to build msp430-decode.c frommsp430decode.opc
 612         using the opc2c program.
 613         * Makefile.in: Regenerate.
 614         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 615         * configure: Regenerate.
 616
 617 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 618
 619         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 620         (SYMTAB_AVAILABLE): Removed.
 621         (#include "elf/aarch64.h): Ditto.
 622
 623 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 624             Maciej W. Rozycki  <macro@codesourcery.com>
 625             Chao-Ying Fu  <fu@mips.com>
 626
 627         * micromips-opc.c (EVA): Define.
 628         (TLBINV): Define.
 629         (micromips_opcodes): Add EVA opcodes.
 630         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 631         (print_insn_args): Handle EVA offsets.
 632         (print_insn_micromips): Likewise.
 633         * mips-opc.c (EVA): Define.
 634         (TLBINV): Define.
 635         (mips_builtin_opcodes): Add EVA opcodes.
 636
 637 2013-06-17  Alan Modra  <amodra@gmail.com>
 638
 639         * Makefile.am (mips-opc.lo): Add rules to create automatic
 640         dependency files.  Pass archdefs.
 641         (micromips-opc.lo, mips16-opc.lo): Likewise.
 642         * Makefile.in: Regenerate.
 643
 644 2013-06-14  DJ Delorie  <dj@redhat.com>
 645
 646         * rx-decode.opc (rx_decode_opcode): Bit operations on
 647         registers are 32-bit operations, not 8-bit operations.
 648         * rx-decode.c: Regenerate.
 649
 650 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 651
 652         * micromips-opc.c (IVIRT): New define.
 653         (IVIRT64): New define.
 654         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 655         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 656
 657         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 658         dmtgc0 to print cp0 names.
 659
 660 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 661
 662         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 663         argument.
 664
 665 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 666             Richard Sandiford  <rdsandiford@googlemail.com>
 667
 668         * micromips-opc.c (D32, D33, MC): Update definitions.
 669         (micromips_opcodes):  Initialize ase field.
 670         * mips-dis.c (mips_arch_choice): Add ase field.
 671         (mips_arch_choices): Initialize ase field.
 672         (set_default_mips_dis_options): Declare and setup mips_ase.
 673         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 674         MT32, MC): Update definitions.
 675         (mips_builtin_opcodes): Initialize ase field.
 676
 677 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 678
 679         * s390-opc.txt (flogr): Require a register pair destination.
 680
 681 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 682
 683         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 684         instruction format.
 685
 686 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 687
 688         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 689
 690 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 691
 692         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 693         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 694         XLS_MASK, PPCVSX2): New defines.
 695         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 696         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 697         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 698         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 699         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 700         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 701         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 702         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 703         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 704         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 705         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 706         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 707         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 708         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 709         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 710         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 711         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 712         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 713         <lxvx, stxvx>: New extended mnemonics.
 714
 715 2013-05-17  Alan Modra  <amodra@gmail.com>
 716
 717         * ia64-raw.tbl: Replace non-ASCII char.
 718         * ia64-waw.tbl: Likewise.
 719         * ia64-asmtab.c: Regenerate.
 720
 721 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 722
 723         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 724         * i386-init.h: Regenerated.
 725
 726 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 727
 728         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 729         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 730         check from [0, 255] to [-128, 255].
 731
 732 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 733
 734         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 735         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 736         (parse_mips_dis_option): Handle the virt option.
 737         (print_insn_args): Handle "+J".
 738         (print_mips_disassembler_options): Print out message about virt64.
 739         * mips-opc.c (IVIRT): New define.
 740         (IVIRT64): New define.
 741         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 742         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 743         Move rfe to the bottom as it conflicts with tlbgp.
 744
 745 2013-05-09  Alan Modra  <amodra@gmail.com>
 746
 747         * ppc-opc.c (extract_vlesi): Properly sign extend.
 748         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 749
 750 2013-05-02  Nick Clifton  <nickc@redhat.com>
 751
 752         * msp430-dis.c: Add support for MSP430X instructions.
 753
 754 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 755
 756         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 757         to "eccinj".
 758
 759 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 760
 761         PR binutils/15369
 762         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 763         of CGEN_CPU_ENDIAN.
 764         (hash_insns_list): Likewise.
 765
 766 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 767
 768         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 769         warning workaround.
 770
 771 2013-04-08  Jan Beulich <jbeulich@suse.com>
 772
 773         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 774         * i386-tbl.h: Re-generate.
 775
 776 2013-04-06  David S. Miller  <davem@davemloft.net>
 777
 778         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 779         of an opcode, prefer the one with F_PREFERRED set.
 780         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 781         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 782         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 783         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 784         instructions generating condition codes, mark existing mnenomics
 785         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 786         existing mnenomics as aliases.
 787
 788 2013-04-03  Nick Clifton  <nickc@redhat.com>
 789
 790         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 791         destination address by subtracting the operand from the current
 792         address.
 793         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 794         a positive value in the insn.
 795         (extract_u16_loop): Do not negate the returned value.
 796         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 797
 798         (ceilf.sw): Remove duplicate entry.
 799         (cvtf.hs): New entry.
 800         (cvtf.sh): Likewise.
 801         (fmaf.s): Likewise.
 802         (fmsf.s): Likewise.
 803         (fnmaf.s): Likewise.
 804         (fnmsf.s): Likewise.
 805         (maddf.s): Restrict to E3V5 architectures.
 806         (msubf.s): Likewise.
 807         (nmaddf.s): Likewise.
 808         (nmsubf.s): Likewise.
 809
 810 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 811
 812         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 813         check address mode.
 814         (print_insn): Pass sizeflag to get_sib.
 815
 816 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 817
 818         PR binutils/15068
 819         * tic6x-dis.c: Add support for displaying 16-bit insns.
 820
 821 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 822
 823         PR gas/15095
 824         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 825         individual msb and lsb halves in src1 & src2 fields.  Discard the
 826         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 827         follow what Ti SDK does in that case as any value in the src1
 828         field yields the same output with SDK disassembler.
 829
 830 2013-03-12  Michael Eager <eager@eagercon.com>
 831
 832         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 833
 834 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 835
 836         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 837
 838 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 839
 840         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 841
 842 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 843
 844         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 845
 846 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 847
 848         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 849         (thumb32_opcodes): Likewise.
 850         (print_insn_thumb32): Handle 'S' control char.
 851
 852 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 853
 854         * lm32-desc.c: Regenerate.
 855
 856 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 857
 858         * i386-reg.tbl (riz): Add RegRex64.
 859         * i386-tbl.h: Regenerated.
 860
 861 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 862
 863         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 864         (aarch64_feature_crc): New static.
 865         (CRC): New macro.
 866         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 867         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 868         * aarch64-asm-2.c: Re-generate.
 869         * aarch64-dis-2.c: Ditto.
 870         * aarch64-opc-2.c: Ditto.
 871
 872 2013-02-27  Alan Modra  <amodra@gmail.com>
 873
 874         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 875         * rl78-decode.c: Regenerate.
 876
 877 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 878
 879         * rl78-decode.opc: Fix encoding of DIVWU insn.
 880         * rl78-decode.c: Regenerate.
 881
 882 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 883
 884         PR gas/15159
 885         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 886
 887         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 888         (cpu_flags): Add CpuSMAP.
 889
 890         * i386-opc.h (CpuSMAP): New.
 891         (i386_cpu_flags): Add cpusmap.
 892
 893         * i386-opc.tbl: Add clac and stac.
 894
 895         * i386-init.h: Regenerated.
 896         * i386-tbl.h: Likewise.
 897
 898 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 899
 900         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 901         which also makes the disassembler output be in little
 902         endian like it should be.
 903
 904 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 905
 906         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 907         fields to NULL.
 908         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 909
 910 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 911
 912         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 913         section disassembled.
 914
 915 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 916
 917         * arm-dis.c: Update strht pattern.
 918
 919 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 920
 921         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 922         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 923         trunc.w.s macro for EE.
 924
 925 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 926             Andrew Jenner <andrew@codesourcery.com>
 927
 928         Based on patches from Altera Corporation.
 929
 930         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 931         nios2-opc.c.
 932         * Makefile.in: Regenerated.
 933         * configure.in: Add case for bfd_nios2_arch.
 934         * configure: Regenerated.
 935         * disassemble.c (ARCH_nios2): Define.
 936         (disassembler): Add case for bfd_arch_nios2.
 937         * nios2-dis.c: New file.
 938         * nios2-opc.c: New file.
 939
 940 2013-02-04  Alan Modra  <amodra@gmail.com>
 941
 942         * po/POTFILES.in: Regenerate.
 943         * rl78-decode.c: Regenerate.
 944         * rx-decode.c: Regenerate.
 945
 946 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 947
 948         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 949         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 950         * aarch64-asm.c (convert_xtl_to_shll): New function.
 951         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 952         calling convert_xtl_to_shll.
 953         * aarch64-dis.c (convert_shll_to_xtl): New function.
 954         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 955         calling convert_shll_to_xtl.
 956         * aarch64-gen.c: Update copyright year.
 957         * aarch64-asm-2.c: Re-generate.
 958         * aarch64-dis-2.c: Re-generate.
 959         * aarch64-opc-2.c: Re-generate.
 960
 961 2013-01-24  Nick Clifton  <nickc@redhat.com>
 962
 963         * v850-dis.c: Add support for e3v5 architecture.
 964         * v850-opc.c: Likewise.
 965
 966 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 967
 968         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 969         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 970         * aarch64-opc.c (operand_general_constraint_met_p): For
 971         AARCH64_MOD_LSL, move the range check on the shift amount before the
 972         alignment check; change to call set_sft_amount_out_of_range_error
 973         instead of set_imm_out_of_range_error.
 974         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 975         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 976         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 977         SIMD_IMM_SFT.
 978
 979 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 980
 981         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 982
 983         * i386-init.h: Regenerated.
 984         * i386-tbl.h: Likewise.
 985
 986 2013-01-15  Nick Clifton  <nickc@redhat.com>
 987
 988         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 989         values.
 990         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 991
 992 2013-01-14  Will Newton <will.newton@imgtec.com>
 993
 994         * metag-dis.c (REG_WIDTH): Increase to 64.
 995
 996 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 997
 998         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 999         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1000         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1001         (SH6): Update.
1002         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1003         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1004         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1005         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1006
1007 2013-01-10  Will Newton <will.newton@imgtec.com>
1008
1009         * Makefile.am: Add Meta.
1010         * configure.in: Add Meta.
1011         * disassemble.c: Add Meta support.
1012         * metag-dis.c: New file.
1013         * Makefile.in: Regenerate.
1014         * configure: Regenerate.
1015
1016 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1017
1018         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1019         (match_opcode): Rename to cr16_match_opcode.
1020
1021 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1022
1023         * mips-dis.c: Add names for CP0 registers of r5900.
1024         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1025         instructions sq and lq.
1026         Add support for MIPS r5900 CPU.
1027         Add support for 128 bit MMI (Multimedia Instructions).
1028         Add support for EE instructions (Emotion Engine).
1029         Disable unsupported floating point instructions (64 bit and
1030         undefined compare operations).
1031         Enable instructions of MIPS ISA IV which are supported by r5900.
1032         Disable 64 bit co processor instructions.
1033         Disable 64 bit multiplication and division instructions.
1034         Disable instructions for co-processor 2 and 3, because these are
1035         not supported (preparation for later VU0 support (Vector Unit)).
1036         Disable cvt.w.s because this behaves like trunc.w.s and the
1037         correct execution can't be ensured on r5900.
1038         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1039         will confuse less developers and compilers.
1040
1041 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1042
1043         * aarch64-opc.c (aarch64_print_operand): Change to print
1044         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1045         in comment.
1046         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1047         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1048         OP_MOV_IMM_WIDE.
1049
1050 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1051
1052         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1053         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1054
1055 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1056
1057         * i386-gen.c (process_copyright): Update copyright year to 2013.
1058
1059 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1060
1061         * cr16-dis.c (match_opcode,make_instruction): Remove static
1062         declaration.
1063         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1064         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1065
1066 For older changes see ChangeLog-2012
1067 \f
1068 Copyright (C) 2013 Free Software Foundation, Inc.
1069
1070 Copying and distribution of this file, with or without modification,
1071 are permitted in any medium without royalty provided the copyright
1072 notice and this notice are preserved.
1073
1074 Local Variables:
1075 mode: change-log
1076 left-margin: 8
1077 fill-column: 74
1078 version-control: never
1079 End: