1 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
3 * ppc-opc.c (insert_ls): Test for invalid LS operands.
4 (insert_esync): New function.
5 (LS, WC): Use insert_ls.
6 (ESYNC): Use insert_esync.
8 2015-06-22 Nick Clifton <nickc@redhat.com>
10 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
11 requested region lies beyond it.
12 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
13 looking for 32-bit insns.
14 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
16 * sh-dis.c (print_insn_sh): Likewise.
17 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
18 blocks of instructions.
19 * vax-dis.c (print_insn_vax): Check that the requested address
20 does not clash with the stop_vma.
22 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
24 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
25 * ppc-opc.c (FXM4): Add non-zero optional value.
28 (insert_fxm): Handle new default operand value.
29 (extract_fxm): Likewise.
30 (insert_tbr): Likewise.
31 (extract_tbr): Likewise.
33 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
35 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
37 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
39 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
41 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
43 * ppc-opc.c: Add comment accidentally removed by old commit.
46 2015-06-04 Nick Clifton <nickc@redhat.com>
49 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
51 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
53 * arm-dis.c (arm_opcodes): Add "setpan".
54 (thumb_opcodes): Add "setpan".
56 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
58 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
61 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
63 * aarch64-tbl.h (aarch64_feature_rdma): New.
65 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
66 * aarch64-asm-2.c: Regenerate.
67 * aarch64-dis-2.c: Regenerate.
68 * aarch64-opc-2.c: Regenerate.
70 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
72 * aarch64-tbl.h (aarch64_feature_lor): New.
74 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
76 * aarch64-asm-2.c: Regenerate.
77 * aarch64-dis-2.c: Regenerate.
78 * aarch64-opc-2.c: Regenerate.
80 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
82 * aarch64-opc.c (F_ARCHEXT): New.
83 (aarch64_sys_regs): Add "pan".
84 (aarch64_sys_reg_supported_p): New.
85 (aarch64_pstatefields): Add "pan".
86 (aarch64_pstatefield_supported_p): New.
88 2015-06-01 Jan Beulich <jbeulich@suse.com>
90 * i386-tbl.h: Regenerate.
92 2015-06-01 Jan Beulich <jbeulich@suse.com>
94 * i386-dis.c (print_insn): Swap rounding mode specifier and
95 general purpose register in Intel mode.
97 2015-06-01 Jan Beulich <jbeulich@suse.com>
99 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
100 * i386-tbl.h: Regenerate.
102 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
104 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
105 * i386-init.h: Regenerated.
107 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
110 * i386-dis.c: Add comments for '@'.
111 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
112 (enum x86_64_isa): New.
114 (print_i386_disassembler_options): Add amd64 and intel64.
115 (print_insn): Handle amd64 and intel64.
117 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
118 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
119 * i386-opc.h (AMD64): New.
120 (CpuIntel64): Likewise.
121 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
122 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
123 Mark direct call/jmp without Disp16|Disp32 as Intel64.
124 * i386-init.h: Regenerated.
125 * i386-tbl.h: Likewise.
127 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
129 * ppc-opc.c (IH) New define.
130 (powerpc_opcodes) <wait>: Do not enable for POWER7.
131 <tlbie>: Add RS operand for POWER7.
132 <slbia>: Add IH operand for POWER6.
134 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
136 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
139 * i386-tbl.h: Regenerated.
141 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
143 * configure.ac: Support bfd_iamcu_arch.
144 * disassemble.c (disassembler): Support bfd_iamcu_arch.
145 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
146 CPU_IAMCU_COMPAT_FLAGS.
147 (cpu_flags): Add CpuIAMCU.
148 * i386-opc.h (CpuIAMCU): New.
149 (i386_cpu_flags): Add cpuiamcu.
150 * configure: Regenerated.
151 * i386-init.h: Likewise.
152 * i386-tbl.h: Likewise.
154 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
157 * i386-dis.c (X86_64_E8): New.
158 (X86_64_E9): Likewise.
159 Update comments on 'T', 'U', 'V'. Add comments for '^'.
160 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
161 (x86_64_table): Add X86_64_E8 and X86_64_E9.
162 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
164 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
167 2015-04-30 DJ Delorie <dj@redhat.com>
169 * disassemble.c (disassembler): Choose suitable disassembler based
171 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
172 it to decode mul/div insns.
173 * rl78-decode.c: Regenerate.
174 * rl78-dis.c (print_insn_rl78): Rename to...
175 (print_insn_rl78_common): ...this, take ISA parameter.
176 (print_insn_rl78): New.
177 (print_insn_rl78_g10): New.
178 (print_insn_rl78_g13): New.
179 (print_insn_rl78_g14): New.
180 (rl78_get_disassembler): New.
182 2015-04-29 Nick Clifton <nickc@redhat.com>
184 * po/fr.po: Updated French translation.
186 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
188 * ppc-opc.c (DCBT_EO): New define.
189 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
193 <waitrsv>: Do not enable for POWER7 and later.
194 <waitimpl>: Likewise.
195 <dcbt>: Default to the two operand form of the instruction for all
196 "old" cpus. For "new" cpus, use the operand ordering that matches
197 whether the cpu is server or embedded.
200 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
202 * s390-opc.c: New instruction type VV0UU2.
203 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
206 2015-04-23 Jan Beulich <jbeulich@suse.com>
208 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
209 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
210 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
211 (vfpclasspd, vfpclassps): Add %XZ.
213 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
215 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
216 (PREFIX_UD_REPZ): Likewise.
217 (PREFIX_UD_REPNZ): Likewise.
218 (PREFIX_UD_DATA): Likewise.
219 (PREFIX_UD_ADDR): Likewise.
220 (PREFIX_UD_LOCK): Likewise.
222 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
224 * i386-dis.c (prefix_requirement): Removed.
225 (print_insn): Don't set prefix_requirement. Check
226 dp->prefix_requirement instead of prefix_requirement.
228 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
231 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
232 (PREFIX_MOD_0_0FC7_REG_6): This.
233 (PREFIX_MOD_3_0FC7_REG_6): New.
234 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
235 (prefix_table): Replace PREFIX_0FC7_REG_6 with
236 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
237 PREFIX_MOD_3_0FC7_REG_7.
238 (mod_table): Replace PREFIX_0FC7_REG_6 with
239 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
240 PREFIX_MOD_3_0FC7_REG_7.
242 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
244 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
245 (PREFIX_MANDATORY_REPNZ): Likewise.
246 (PREFIX_MANDATORY_DATA): Likewise.
247 (PREFIX_MANDATORY_ADDR): Likewise.
248 (PREFIX_MANDATORY_LOCK): Likewise.
249 (PREFIX_MANDATORY): Likewise.
250 (PREFIX_UD_SHIFT): Set to 8
251 (PREFIX_UD_REPZ): Updated.
252 (PREFIX_UD_REPNZ): Likewise.
253 (PREFIX_UD_DATA): Likewise.
254 (PREFIX_UD_ADDR): Likewise.
255 (PREFIX_UD_LOCK): Likewise.
256 (PREFIX_IGNORED_SHIFT): New.
257 (PREFIX_IGNORED_REPZ): Likewise.
258 (PREFIX_IGNORED_REPNZ): Likewise.
259 (PREFIX_IGNORED_DATA): Likewise.
260 (PREFIX_IGNORED_ADDR): Likewise.
261 (PREFIX_IGNORED_LOCK): Likewise.
262 (PREFIX_OPCODE): Likewise.
263 (PREFIX_IGNORED): Likewise.
264 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
265 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
266 (three_byte_table): Likewise.
267 (mod_table): Likewise.
268 (mandatory_prefix): Renamed to ...
269 (prefix_requirement): This.
270 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
271 Update PREFIX_90 entry.
272 (get_valid_dis386): Check prefix_requirement to see if a prefix
274 (print_insn): Replace mandatory_prefix with prefix_requirement.
276 2015-04-15 Renlin Li <renlin.li@arm.com>
278 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
279 use it for ssat and ssat16.
280 (print_insn_thumb32): Add handle case for 'D' control code.
282 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
283 H.J. Lu <hongjiu.lu@intel.com>
285 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
286 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
287 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
288 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
289 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
290 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
291 Fill prefix_requirement field.
292 (struct dis386): Add prefix_requirement field.
293 (dis386): Fill prefix_requirement field.
294 (dis386_twobyte): Ditto.
295 (twobyte_has_mandatory_prefix_: Remove.
296 (reg_table): Fill prefix_requirement field.
297 (prefix_table): Ditto.
298 (x86_64_table): Ditto.
299 (three_byte_table): Ditto.
302 (vex_len_table): Ditto.
303 (vex_w_table): Ditto.
306 (print_insn): Use prefix_requirement.
307 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
308 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
311 2015-03-30 Mike Frysinger <vapier@gentoo.org>
313 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
315 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
317 * Makefile.in: Regenerated.
319 2015-03-25 Anton Blanchard <anton@samba.org>
321 * ppc-dis.c (disassemble_init_powerpc): Only initialise
322 powerpc_opcd_indices and vle_opcd_indices once.
324 2015-03-25 Anton Blanchard <anton@samba.org>
326 * ppc-opc.c (powerpc_opcodes): Add slbfee.
328 2015-03-24 Terry Guo <terry.guo@arm.com>
330 * arm-dis.c (opcode32): Updated to use new arm feature struct.
331 (opcode16): Likewise.
332 (coprocessor_opcodes): Replace bit with feature struct.
333 (neon_opcodes): Likewise.
334 (arm_opcodes): Likewise.
335 (thumb_opcodes): Likewise.
336 (thumb32_opcodes): Likewise.
337 (print_insn_coprocessor): Likewise.
338 (print_insn_arm): Likewise.
339 (select_arm_features): Follow new feature struct.
341 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
343 * i386-dis.c (rm_table): Add clzero.
344 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
345 Add CPU_CLZERO_FLAGS.
346 (cpu_flags): Add CpuCLZERO.
347 * i386-opc.h: Add CpuCLZERO.
348 * i386-opc.tbl: Add clzero.
349 * i386-init.h: Re-generated.
350 * i386-tbl.h: Re-generated.
352 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
354 * mips-opc.c (decode_mips_operand): Fix constraint issues
355 with u and y operands.
357 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
359 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
361 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
363 * s390-opc.c: Add new IBM z13 instructions.
364 * s390-opc.txt: Likewise.
366 2015-03-10 Renlin Li <renlin.li@arm.com>
368 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
369 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
371 * aarch64-asm-2.c: Regenerate.
372 * aarch64-dis-2.c: Likewise.
373 * aarch64-opc-2.c: Likewise.
375 2015-03-03 Jiong Wang <jiong.wang@arm.com>
377 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
379 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
381 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
383 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
384 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
386 2015-02-23 Vinay <Vinay.G@kpit.com>
388 * rl78-decode.opc (MOV): Added space between two operands for
389 'mov' instruction in index addressing mode.
390 * rl78-decode.c: Regenerate.
392 2015-02-19 Pedro Alves <palves@redhat.com>
394 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
396 2015-02-10 Pedro Alves <palves@redhat.com>
397 Tom Tromey <tromey@redhat.com>
399 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
400 microblaze_and, microblaze_xor.
401 * microblaze-opc.h (opcodes): Adjust.
403 2015-01-28 James Bowman <james.bowman@ftdichip.com>
405 * Makefile.am: Add FT32 files.
406 * configure.ac: Handle FT32.
407 * disassemble.c (disassembler): Call print_insn_ft32.
408 * ft32-dis.c: New file.
409 * ft32-opc.c: New file.
410 * Makefile.in: Regenerate.
411 * configure: Regenerate.
412 * po/POTFILES.in: Regenerate.
414 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
416 * nds32-asm.c (keyword_sr): Add new system registers.
418 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
420 * s390-dis.c (s390_extract_operand): Support vector register
422 (s390_print_insn_with_opcode): Support new operands types and add
423 new handling of optional operands.
424 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
425 and include opcode/s390.h instead.
426 (struct op_struct): New field `flags'.
427 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
428 (dumpTable): Dump flags.
429 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
431 * s390-opc.c: Add new operands types, instruction formats, and
433 (s390_opformats): Add new formats for .insn.
434 * s390-opc.txt: Add new instructions.
436 2015-01-01 Alan Modra <amodra@gmail.com>
438 Update year range in copyright notice of all files.
440 For older changes see ChangeLog-2014
442 Copyright (C) 2015 Free Software Foundation, Inc.
444 Copying and distribution of this file, with or without modification,
445 are permitted in any medium without royalty provided the copyright
446 notice and this notice are preserved.
452 version-control: never