opcodes/ChangeLog

   1 2019-08-07  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
   4         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
   5         IgnoreSize.
   6         * i386-tbl.h: Re-generate.
   7
   8 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
   9
  10         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
  11         instructions.
  12
  13 2019-07-30  Mel Chen <mel.chen@sifive.com>
  14
  15         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
  16         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
  17
  18         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
  19         fscsr.
  20
  21 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  22
  23         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
  24         and MPY class instructions.
  25         (parse_option): Add nps400 option.
  26         (print_arc_disassembler_options): Add nps400 info.
  27
  28 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  29
  30         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
  31         (bspop): Likewise.
  32         (modapp): Likewise.
  33         * arc-opc.c (RAD_CHK): Add.
  34         * arc-tbl.h: Regenerate.
  35
  36 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  37
  38         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
  39         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
  40
  41 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
  42
  43         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
  44         instructions as UNPREDICTABLE.
  45
  46 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
  47
  48         * bpf-desc.c: Regenerated.
  49
  50 2019-07-17  Jan Beulich  <jbeulich@suse.com>
  51
  52         * i386-gen.c (static_assert): Define.
  53         (main): Use it.
  54         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
  55         (Opcode_Modifier_Num): ... this.
  56         (Mem): Delete.
  57
  58 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  59
  60         * i386-gen.c (operand_types): Move RegMem ...
  61         (opcode_modifiers): ... here.
  62         * i386-opc.h (RegMem): Move to opcode modifer enum.
  63         (union i386_operand_type): Move regmem field ...
  64         (struct i386_opcode_modifier): ... here.
  65         * i386-opc.tbl (RegMem): Define.
  66         (mov, movq): Move RegMem on segment, control, debug, and test
  67         register flavors.
  68         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
  69         to non-SSE2AVX flavor.
  70         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
  71         Move RegMem on register only flavors. Drop IgnoreSize from
  72         legacy encoding flavors.
  73         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
  74         flavors.
  75         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
  76         register only flavors.
  77         (vmovd): Move RegMem and drop IgnoreSize on register only
  78         flavor. Change opcode and operand order to store form.
  79         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  80
  81 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  82
  83         * i386-gen.c (operand_type_init, operand_types): Replace SReg
  84         entries.
  85         * i386-opc.h (SReg2, SReg3): Replace by ...
  86         (SReg): ... this.
  87         (union i386_operand_type): Replace sreg fields.
  88         * i386-opc.tbl (mov, ): Use SReg.
  89         (push, pop): Likewies. Drop i386 and x86-64 specific segment
  90         register flavors.
  91         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
  92         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  93
  94 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
  95
  96         * bpf-desc.c: Regenerate.
  97         * bpf-opc.c: Likewise.
  98         * bpf-opc.h: Likewise.
  99
 100 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 101
 102         * bpf-desc.c: Regenerate.
 103         * bpf-opc.c: Likewise.
 104
 105 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 106
 107         * arm-dis.c (print_insn_coprocessor): Rename index to
 108         index_operand.
 109
 110 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 111
 112         * riscv-opc.c (riscv_insn_types): Add r4 type.
 113
 114         * riscv-opc.c (riscv_insn_types): Add b and j type.
 115
 116         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 117         format for sb type and correct s type.
 118
 119 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 120
 121         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 122         SVE FMOV alias of FCPY.
 123
 124 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 125
 126         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 127         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 128
 129 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 130
 131         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 132         registers in an instruction prefixed by MOVPRFX.
 133
 134 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 135
 136         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 137         sve_size_13 icode to account for variant behaviour of
 138         pmull{t,b}.
 139         * aarch64-dis-2.c: Regenerate.
 140         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 141         sve_size_13 icode to account for variant behaviour of
 142         pmull{t,b}.
 143         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 144         (OP_SVE_VVV_Q_D): Add new qualifier.
 145         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 146         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 147         AES and those not.
 148
 149 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 150
 151         * opcodes/i386-gen.c (operand_type_init): Remove
 152         OPERAND_TYPE_VEC_IMM4 entry.
 153         (operand_types): Remove Vec_Imm4.
 154         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 155         (union i386_operand_type): Remove vec_imm4.
 156         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 157         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 158
 159 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 160
 161         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 162         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 163         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 164         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 165         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 166         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 167         * i386-tbl.h: Re-generate.
 168
 169 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 170
 171         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 172         register operands.
 173         * i386-tbl.h: Re-generate.
 174
 175 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 176
 177         * i386-opc.tbl (C): New.
 178         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 179         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 180         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 181         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 182         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 183         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 184         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 185         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 186         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 187         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 188         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 189         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 190         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 191         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 192         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 193         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 194         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 195         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 196         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 197         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 198         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 199         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 200         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 201         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 202         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 203         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 204         flavors.
 205         * i386-tbl.h: Re-generate.
 206
 207 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 210         register operands.
 211         * i386-tbl.h: Re-generate.
 212
 213 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 216         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 217         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 218         * i386-tbl.h: Re-generate.
 219
 220 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 221
 222         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 223         Disp8MemShift from register only templates.
 224         * i386-tbl.h: Re-generate.
 225
 226 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 227
 228         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 229         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 230         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 231         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 232         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 233         EVEX_W_0F11_P_3_M_1): Delete.
 234         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 235         EVEX_W_0F11_P_3): New.
 236         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 237         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 238         MOD_EVEX_0F11_PREFIX_3 table entries.
 239         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 240         PREFIX_EVEX_0F11 table entries.
 241         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 242         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 243         EVEX_W_0F11_P_3_M_{0,1} table entries.
 244
 245 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 248         Delete.
 249
 250 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 251
 252         PR binutils/24719
 253         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 254         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 255         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 256         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 257         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 258         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 259         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 260         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 261         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 262         PREFIX_EVEX_0F38C6_REG_6 entries.
 263         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 264         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 265         EVEX_W_0F38C7_R_6_P_2 entries.
 266         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 267         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 268         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 269         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 270         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 271         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 272         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 273
 274 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 275
 276         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 277         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 278         VEX_LEN_0F2D_P_3): Delete.
 279         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 280         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 281         (prefix_table): ... here.
 282
 283 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 284
 285         * i386-dis.c (Iq): Delete.
 286         (Id): New.
 287         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 288         TBM insns.
 289         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 290         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 291         (OP_E_memory): Also honor needindex when deciding whether an
 292         address size prefix needs printing.
 293         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 294
 295 2019-06-26  Jim Wilson  <jimw@sifive.com>
 296
 297         PR binutils/24739
 298         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 299         Set info->display_endian to info->endian_code.
 300
 301 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 302
 303         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 304         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 305         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 306         OPERAND_TYPE_ACC64 entries.
 307         * i386-init.h: Re-generate.
 308
 309 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 312         Delete.
 313         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 314         of dqa_mode.
 315         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 316         entries here.
 317         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 318         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 319
 320 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 321
 322         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 323         variables.
 324
 325 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 326
 327         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 328         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 329         movnti.
 330         * i386-opc.tbl (movnti): Add IgnoreSize.
 331         * i386-tbl.h: Re-generate.
 332
 333 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 334
 335         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 336         * i386-tbl.h: Re-generate.
 337
 338 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 339
 340         * i386-dis-evex.h: Break into ...
 341         * i386-dis-evex-len.h: New file.
 342         * i386-dis-evex-mod.h: Likewise.
 343         * i386-dis-evex-prefix.h: Likewise.
 344         * i386-dis-evex-reg.h: Likewise.
 345         * i386-dis-evex-w.h: Likewise.
 346         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 347         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 348         i386-dis-evex-mod.h.
 349
 350 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 351
 352         PR binutils/24700
 353         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 354         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 355         EVEX_W_0F385B_P_2.
 356         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 357         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 358         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 359         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 360         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 361         EVEX_LEN_0F385B_P_2_W_1.
 362         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 363         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 364         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 365         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 366         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 367         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 368         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 369         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 370         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 371         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 372
 373 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 374
 375         PR binutils/24691
 376         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 377         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 378         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 379         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 380         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 381         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 382         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 383         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 384         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 385         EVEX_LEN_0F3A43_P_2_W_1.
 386         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 387         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 388         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 389         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 390         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 391         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 392         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 393         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 394         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 395         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 396         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 397         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 398
 399 2019-06-14  Nick Clifton  <nickc@redhat.com>
 400
 401         * po/fr.po; Updated French translation.
 402
 403 2019-06-13  Stafford Horne  <shorne@gmail.com>
 404
 405         * or1k-asm.c: Regenerated.
 406         * or1k-desc.c: Regenerated.
 407         * or1k-desc.h: Regenerated.
 408         * or1k-dis.c: Regenerated.
 409         * or1k-ibld.c: Regenerated.
 410         * or1k-opc.c: Regenerated.
 411         * or1k-opc.h: Regenerated.
 412         * or1k-opinst.c: Regenerated.
 413
 414 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 415
 416         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 417
 418 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 419
 420         PR binutils/24633
 421         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 422         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 423         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 424         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 425         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 426         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 427         EVEX_LEN_0F3A1B_P_2_W_1.
 428         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 429         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 430         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 431         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 432         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 433         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 434         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 435         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 436
 437 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         PR binutils/24626
 440         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 441         EVEX.vvvv when disassembling VEX and EVEX instructions.
 442         (OP_VEX): Set vex.register_specifier to 0 after readding
 443         vex.register_specifier.
 444         (OP_Vex_2src_1): Likewise.
 445         (OP_Vex_2src_2): Likewise.
 446         (OP_LWP_E): Likewise.
 447         (OP_EX_Vex): Don't check vex.register_specifier.
 448         (OP_XMM_Vex): Likewise.
 449
 450 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 451             Lili Cui  <lili.cui@intel.com>
 452
 453         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 454         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 455         instructions.
 456         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 457         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 458         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 459         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 460         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 461         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 462         * i386-init.h: Regenerated.
 463         * i386-tbl.h: Likewise.
 464
 465 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 466             Lili Cui  <lili.cui@intel.com>
 467
 468         * doc/c-i386.texi: Document enqcmd.
 469         * testsuite/gas/i386/enqcmd-intel.d: New file.
 470         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 471         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 472         * testsuite/gas/i386/enqcmd.d: Likewise.
 473         * testsuite/gas/i386/enqcmd.s: Likewise.
 474         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 475         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 476         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 477         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 478         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 479         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 480         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 481         and x86-64-enqcmd.
 482
 483 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 484
 485         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 486
 487 2019-06-03  Alan Modra  <amodra@gmail.com>
 488
 489         * ppc-dis.c (prefix_opcd_indices): Correct size.
 490
 491 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 492
 493         PR gas/24625
 494         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 495         Disp8ShiftVL.
 496         * i386-tbl.h: Regenerated.
 497
 498 2019-05-24  Alan Modra  <amodra@gmail.com>
 499
 500         * po/POTFILES.in: Regenerate.
 501
 502 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 503             Alan Modra  <amodra@gmail.com>
 504
 505         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 506         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 507         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 508         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 509         XTOP>): Define and add entries.
 510         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 511         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 512         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 513         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 514
 515 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 516             Alan Modra  <amodra@gmail.com>
 517
 518         * ppc-dis.c (ppc_opts): Add "future" entry.
 519         (PREFIX_OPCD_SEGS): Define.
 520         (prefix_opcd_indices): New array.
 521         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 522         (lookup_prefix): New function.
 523         (print_insn_powerpc): Handle 64-bit prefix instructions.
 524         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 525         (PMRR, POWERXX): Define.
 526         (prefix_opcodes): New instruction table.
 527         (prefix_num_opcodes): New constant.
 528
 529 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 530
 531         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 532         * configure: Regenerated.
 533         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 534         and cpu/bpf.opc.
 535         (HFILES): Add bpf-desc.h and bpf-opc.h.
 536         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 537         bpf-ibld.c and bpf-opc.c.
 538         (BPF_DEPS): Define.
 539         * Makefile.in: Regenerated.
 540         * disassemble.c (ARCH_bpf): Define.
 541         (disassembler): Add case for bfd_arch_bpf.
 542         (disassemble_init_for_target): Likewise.
 543         (enum epbf_isa_attr): Define.
 544         * disassemble.h: extern print_insn_bpf.
 545         * bpf-asm.c: Generated.
 546         * bpf-opc.h: Likewise.
 547         * bpf-opc.c: Likewise.
 548         * bpf-ibld.c: Likewise.
 549         * bpf-dis.c: Likewise.
 550         * bpf-desc.h: Likewise.
 551         * bpf-desc.c: Likewise.
 552
 553 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 554
 555         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 556         and VMSR with the new operands.
 557
 558 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 559
 560         * arm-dis.c (enum mve_instructions): New enum
 561         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 562         and cneg.
 563         (mve_opcodes): New instructions as above.
 564         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 565         csneg and csel.
 566         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 567
 568 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 569
 570         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 571         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 572         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 573         uqshl, urshrl and urshr.
 574         (is_mve_okay_in_it): Add new instructions to TRUE list.
 575         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 576         (print_insn_mve): Updated to accept new %j,
 577         %<bitfield>m and %<bitfield>n patterns.
 578
 579 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 580
 581         * mips-opc.c (mips_builtin_opcodes): Change source register
 582         constraint for DAUI.
 583
 584 2019-05-20  Nick Clifton  <nickc@redhat.com>
 585
 586         * po/fr.po: Updated French translation.
 587
 588 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 589             Michael Collison <michael.collison@arm.com>
 590
 591         * arm-dis.c (thumb32_opcodes): Add new instructions.
 592         (enum mve_instructions): Likewise.
 593         (enum mve_undefined): Add new reasons.
 594         (is_mve_encoding_conflict): Handle new instructions.
 595         (is_mve_undefined): Likewise.
 596         (is_mve_unpredictable): Likewise.
 597         (print_mve_undefined): Likewise.
 598         (print_mve_size): Likewise.
 599
 600 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 601             Michael Collison <michael.collison@arm.com>
 602
 603         * arm-dis.c (thumb32_opcodes): Add new instructions.
 604         (enum mve_instructions): Likewise.
 605         (is_mve_encoding_conflict): Handle new instructions.
 606         (is_mve_undefined): Likewise.
 607         (is_mve_unpredictable): Likewise.
 608         (print_mve_size): Likewise.
 609
 610 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 611             Michael Collison <michael.collison@arm.com>
 612
 613         * arm-dis.c (thumb32_opcodes): Add new instructions.
 614         (enum mve_instructions): Likewise.
 615         (is_mve_encoding_conflict): Likewise.
 616         (is_mve_unpredictable): Likewise.
 617         (print_mve_size): Likewise.
 618
 619 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 620             Michael Collison <michael.collison@arm.com>
 621
 622         * arm-dis.c (thumb32_opcodes): Add new instructions.
 623         (enum mve_instructions): Likewise.
 624         (is_mve_encoding_conflict): Handle new instructions.
 625         (is_mve_undefined): Likewise.
 626         (is_mve_unpredictable): Likewise.
 627         (print_mve_size): Likewise.
 628
 629 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 630             Michael Collison <michael.collison@arm.com>
 631
 632         * arm-dis.c (thumb32_opcodes): Add new instructions.
 633         (enum mve_instructions): Likewise.
 634         (is_mve_encoding_conflict): Handle new instructions.
 635         (is_mve_undefined): Likewise.
 636         (is_mve_unpredictable): Likewise.
 637         (print_mve_size): Likewise.
 638         (print_insn_mve): Likewise.
 639
 640 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 641             Michael Collison <michael.collison@arm.com>
 642
 643         * arm-dis.c (thumb32_opcodes): Add new instructions.
 644         (print_insn_thumb32): Handle new instructions.
 645
 646 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 647             Michael Collison <michael.collison@arm.com>
 648
 649         * arm-dis.c (enum mve_instructions): Add new instructions.
 650         (enum mve_undefined): Add new reasons.
 651         (is_mve_encoding_conflict): Handle new instructions.
 652         (is_mve_undefined): Likewise.
 653         (is_mve_unpredictable): Likewise.
 654         (print_mve_undefined): Likewise.
 655         (print_mve_size): Likewise.
 656         (print_mve_shift_n): Likewise.
 657         (print_insn_mve): Likewise.
 658
 659 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 660             Michael Collison <michael.collison@arm.com>
 661
 662         * arm-dis.c (enum mve_instructions): Add new instructions.
 663         (is_mve_encoding_conflict): Handle new instructions.
 664         (is_mve_unpredictable): Likewise.
 665         (print_mve_rotate): Likewise.
 666         (print_mve_size): Likewise.
 667         (print_insn_mve): Likewise.
 668
 669 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 670             Michael Collison <michael.collison@arm.com>
 671
 672         * arm-dis.c (enum mve_instructions): Add new instructions.
 673         (is_mve_encoding_conflict): Handle new instructions.
 674         (is_mve_unpredictable): Likewise.
 675         (print_mve_size): Likewise.
 676         (print_insn_mve): Likewise.
 677
 678 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 679             Michael Collison <michael.collison@arm.com>
 680
 681         * arm-dis.c (enum mve_instructions): Add new instructions.
 682         (enum mve_undefined): Add new reasons.
 683         (is_mve_encoding_conflict): Handle new instructions.
 684         (is_mve_undefined): Likewise.
 685         (is_mve_unpredictable): Likewise.
 686         (print_mve_undefined): Likewise.
 687         (print_mve_size): Likewise.
 688         (print_insn_mve): Likewise.
 689
 690 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 691             Michael Collison <michael.collison@arm.com>
 692
 693         * arm-dis.c (enum mve_instructions): Add new instructions.
 694         (is_mve_encoding_conflict): Handle new instructions.
 695         (is_mve_undefined): Likewise.
 696         (is_mve_unpredictable): Likewise.
 697         (print_mve_size): Likewise.
 698         (print_insn_mve): Likewise.
 699
 700 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 701             Michael Collison <michael.collison@arm.com>
 702
 703         * arm-dis.c (enum mve_instructions): Add new instructions.
 704         (enum mve_unpredictable): Add new reasons.
 705         (enum mve_undefined): Likewise.
 706         (is_mve_okay_in_it): Handle new isntructions.
 707         (is_mve_encoding_conflict): Likewise.
 708         (is_mve_undefined): Likewise.
 709         (is_mve_unpredictable): Likewise.
 710         (print_mve_vmov_index): Likewise.
 711         (print_simd_imm8): Likewise.
 712         (print_mve_undefined): Likewise.
 713         (print_mve_unpredictable): Likewise.
 714         (print_mve_size): Likewise.
 715         (print_insn_mve): Likewise.
 716
 717 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 718             Michael Collison <michael.collison@arm.com>
 719
 720         * arm-dis.c (enum mve_instructions): Add new instructions.
 721         (enum mve_unpredictable): Add new reasons.
 722         (enum mve_undefined): Likewise.
 723         (is_mve_encoding_conflict): Handle new instructions.
 724         (is_mve_undefined): Likewise.
 725         (is_mve_unpredictable): Likewise.
 726         (print_mve_undefined): Likewise.
 727         (print_mve_unpredictable): Likewise.
 728         (print_mve_rounding_mode): Likewise.
 729         (print_mve_vcvt_size): Likewise.
 730         (print_mve_size): Likewise.
 731         (print_insn_mve): Likewise.
 732
 733 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 734             Michael Collison <michael.collison@arm.com>
 735
 736         * arm-dis.c (enum mve_instructions): Add new instructions.
 737         (enum mve_unpredictable): Add new reasons.
 738         (enum mve_undefined): Likewise.
 739         (is_mve_undefined): Handle new instructions.
 740         (is_mve_unpredictable): Likewise.
 741         (print_mve_undefined): Likewise.
 742         (print_mve_unpredictable): Likewise.
 743         (print_mve_size): Likewise.
 744         (print_insn_mve): Likewise.
 745
 746 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 747             Michael Collison <michael.collison@arm.com>
 748
 749         * arm-dis.c (enum mve_instructions): Add new instructions.
 750         (enum mve_undefined): Add new reasons.
 751         (insns): Add new instructions.
 752         (is_mve_encoding_conflict):
 753         (print_mve_vld_str_addr): New print function.
 754         (is_mve_undefined): Handle new instructions.
 755         (is_mve_unpredictable): Likewise.
 756         (print_mve_undefined): Likewise.
 757         (print_mve_size): Likewise.
 758         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 759         (print_insn_mve):  Handle new operands.
 760
 761 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 762             Michael Collison <michael.collison@arm.com>
 763
 764         * arm-dis.c (enum mve_instructions): Add new instructions.
 765         (enum mve_unpredictable): Add new reasons.
 766         (is_mve_encoding_conflict): Handle new instructions.
 767         (is_mve_unpredictable): Likewise.
 768         (mve_opcodes): Add new instructions.
 769         (print_mve_unpredictable): Handle new reasons.
 770         (print_mve_register_blocks): New print function.
 771         (print_mve_size): Handle new instructions.
 772         (print_insn_mve): Likewise.
 773
 774 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 775             Michael Collison <michael.collison@arm.com>
 776
 777         * arm-dis.c (enum mve_instructions): Add new instructions.
 778         (enum mve_unpredictable): Add new reasons.
 779         (enum mve_undefined): Likewise.
 780         (is_mve_encoding_conflict): Handle new instructions.
 781         (is_mve_undefined): Likewise.
 782         (is_mve_unpredictable): Likewise.
 783         (coprocessor_opcodes): Move NEON VDUP from here...
 784         (neon_opcodes): ... to here.
 785         (mve_opcodes): Add new instructions.
 786         (print_mve_undefined):  Handle new reasons.
 787         (print_mve_unpredictable): Likewise.
 788         (print_mve_size): Handle new instructions.
 789         (print_insn_neon): Handle vdup.
 790         (print_insn_mve): Handle new operands.
 791
 792 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 793             Michael Collison <michael.collison@arm.com>
 794
 795         * arm-dis.c (enum mve_instructions): Add new instructions.
 796         (enum mve_unpredictable): Add new values.
 797         (mve_opcodes): Add new instructions.
 798         (vec_condnames): New array with vector conditions.
 799         (mve_predicatenames): New array with predicate suffixes.
 800         (mve_vec_sizename): New array with vector sizes.
 801         (enum vpt_pred_state): New enum with vector predication states.
 802         (struct vpt_block): New struct type for vpt blocks.
 803         (vpt_block_state): Global struct to keep track of state.
 804         (mve_extract_pred_mask): New helper function.
 805         (num_instructions_vpt_block): Likewise.
 806         (mark_outside_vpt_block): Likewise.
 807         (mark_inside_vpt_block): Likewise.
 808         (invert_next_predicate_state): Likewise.
 809         (update_next_predicate_state): Likewise.
 810         (update_vpt_block_state): Likewise.
 811         (is_vpt_instruction): Likewise.
 812         (is_mve_encoding_conflict): Add entries for new instructions.
 813         (is_mve_unpredictable): Likewise.
 814         (print_mve_unpredictable): Handle new cases.
 815         (print_instruction_predicate): Likewise.
 816         (print_mve_size): New function.
 817         (print_vec_condition): New function.
 818         (print_insn_mve): Handle vpt blocks and new print operands.
 819
 820 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 821
 822         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 823         8, 14 and 15 for Armv8.1-M Mainline.
 824
 825 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 826             Michael Collison <michael.collison@arm.com>
 827
 828         * arm-dis.c (enum mve_instructions): New enum.
 829         (enum mve_unpredictable): Likewise.
 830         (enum mve_undefined): Likewise.
 831         (struct mopcode32): New struct.
 832         (is_mve_okay_in_it): New function.
 833         (is_mve_architecture): Likewise.
 834         (arm_decode_field): Likewise.
 835         (arm_decode_field_multiple): Likewise.
 836         (is_mve_encoding_conflict): Likewise.
 837         (is_mve_undefined): Likewise.
 838         (is_mve_unpredictable): Likewise.
 839         (print_mve_undefined): Likewise.
 840         (print_mve_unpredictable): Likewise.
 841         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 842         (print_insn_mve): New function.
 843         (print_insn_thumb32): Handle MVE architecture.
 844         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 845
 846 2019-05-10  Nick Clifton  <nickc@redhat.com>
 847
 848         PR 24538
 849         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 850         end of the table prematurely.
 851
 852 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 853
 854         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 855         macros for R6.
 856
 857 2019-05-11  Alan Modra  <amodra@gmail.com>
 858
 859         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 860         when -Mraw is in effect.
 861
 862 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 863
 864         * aarch64-dis-2.c: Regenerate.
 865         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 866         (OP_SVE_BBB): New variant set.
 867         (OP_SVE_DDDD): New variant set.
 868         (OP_SVE_HHH): New variant set.
 869         (OP_SVE_HHHU): New variant set.
 870         (OP_SVE_SSS): New variant set.
 871         (OP_SVE_SSSU): New variant set.
 872         (OP_SVE_SHH): New variant set.
 873         (OP_SVE_SBBU): New variant set.
 874         (OP_SVE_DSS): New variant set.
 875         (OP_SVE_DHHU): New variant set.
 876         (OP_SVE_VMV_HSD_BHS): New variant set.
 877         (OP_SVE_VVU_HSD_BHS): New variant set.
 878         (OP_SVE_VVVU_SD_BH): New variant set.
 879         (OP_SVE_VVVU_BHSD): New variant set.
 880         (OP_SVE_VVV_QHD_DBS): New variant set.
 881         (OP_SVE_VVV_HSD_BHS): New variant set.
 882         (OP_SVE_VVV_HSD_BHS2): New variant set.
 883         (OP_SVE_VVV_BHS_HSD): New variant set.
 884         (OP_SVE_VV_BHS_HSD): New variant set.
 885         (OP_SVE_VVV_SD): New variant set.
 886         (OP_SVE_VVU_BHS_HSD): New variant set.
 887         (OP_SVE_VZVV_SD): New variant set.
 888         (OP_SVE_VZVV_BH): New variant set.
 889         (OP_SVE_VZV_SD): New variant set.
 890         (aarch64_opcode_table): Add sve2 instructions.
 891
 892 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 893
 894         * aarch64-asm-2.c: Regenerated.
 895         * aarch64-dis-2.c: Regenerated.
 896         * aarch64-opc-2.c: Regenerated.
 897         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 898         for SVE_SHLIMM_UNPRED_22.
 899         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 900         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 901         operand.
 902
 903 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 904
 905         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 906         sve_size_tsz_bhs iclass encode.
 907         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 908         sve_size_tsz_bhs iclass decode.
 909
 910 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 911
 912         * aarch64-asm-2.c: Regenerated.
 913         * aarch64-dis-2.c: Regenerated.
 914         * aarch64-opc-2.c: Regenerated.
 915         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 916         for SVE_Zm4_11_INDEX.
 917         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 918         (fields): Handle SVE_i2h field.
 919         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 920         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 921
 922 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 923
 924         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 925         sve_shift_tsz_bhsd iclass encode.
 926         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 927         sve_shift_tsz_bhsd iclass decode.
 928
 929 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 930
 931         * aarch64-asm-2.c: Regenerated.
 932         * aarch64-dis-2.c: Regenerated.
 933         * aarch64-opc-2.c: Regenerated.
 934         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 935         (aarch64_encode_variant_using_iclass): Handle
 936         sve_shift_tsz_hsd iclass encode.
 937         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 938         sve_shift_tsz_hsd iclass decode.
 939         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 940         for SVE_SHRIMM_UNPRED_22.
 941         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 942         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 943         operand.
 944
 945 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 946
 947         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 948         sve_size_013 iclass encode.
 949         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 950         sve_size_013 iclass decode.
 951
 952 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 953
 954         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 955         sve_size_bh iclass encode.
 956         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 957         sve_size_bh iclass decode.
 958
 959 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 960
 961         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 962         sve_size_sd2 iclass encode.
 963         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 964         sve_size_sd2 iclass decode.
 965         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 966         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 967
 968 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 969
 970         * aarch64-asm-2.c: Regenerated.
 971         * aarch64-dis-2.c: Regenerated.
 972         * aarch64-opc-2.c: Regenerated.
 973         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 974         for SVE_ADDR_ZX.
 975         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 976         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 977
 978 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 979
 980         * aarch64-asm-2.c: Regenerated.
 981         * aarch64-dis-2.c: Regenerated.
 982         * aarch64-opc-2.c: Regenerated.
 983         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 984         for SVE_Zm3_11_INDEX.
 985         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 986         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 987         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 988         fields.
 989         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 990
 991 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 992
 993         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 994         sve_size_hsd2 iclass encode.
 995         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 996         sve_size_hsd2 iclass decode.
 997         * aarch64-opc.c (fields): Handle SVE_size field.
 998         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 999
1000 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1001
1002         * aarch64-asm-2.c: Regenerated.
1003         * aarch64-dis-2.c: Regenerated.
1004         * aarch64-opc-2.c: Regenerated.
1005         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1006         for SVE_IMM_ROT3.
1007         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1008         (fields): Handle SVE_rot3 field.
1009         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1010         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1011
1012 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1013
1014         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1015         instructions.
1016
1017 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1018
1019         * aarch64-tbl.h
1020         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1021         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1022         aarch64_feature_sve2bitperm): New feature sets.
1023         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1024         for feature set addresses.
1025         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1026         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1027
1028 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1029             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1030
1031         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1032         argument and set ASE_EVA_R6 appropriately.
1033         (set_default_mips_dis_options): Pass ISA to above.
1034         (parse_mips_dis_option): Likewise.
1035         * mips-opc.c (EVAR6): New macro.
1036         (mips_builtin_opcodes): Add llwpe, scwpe.
1037
1038 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1039
1040         * aarch64-asm-2.c: Regenerated.
1041         * aarch64-dis-2.c: Regenerated.
1042         * aarch64-opc-2.c: Regenerated.
1043         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1044         AARCH64_OPND_TME_UIMM16.
1045         (aarch64_print_operand): Likewise.
1046         * aarch64-tbl.h (QL_IMM_NIL): New.
1047         (TME): New.
1048         (_TME_INSN): New.
1049         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1050
1051 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1052
1053         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1054
1055 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1056             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1057
1058         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1059
1060 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1061
1062         * s12z-opc.h: Add extern "C" bracketing to help
1063         users who wish to use this interface in c++ code.
1064
1065 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1066
1067         * s12z-opc.c (bm_decode): Handle bit map operations with the
1068         "reserved0" mode.
1069
1070 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1071
1072         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1073         specifier.  Add entries for VLDR and VSTR of system registers.
1074         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1075         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1076         of %J and %K format specifier.
1077
1078 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1079
1080         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1081         Add new entries for VSCCLRM instruction.
1082         (print_insn_coprocessor): Handle new %C format control code.
1083
1084 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1085
1086         * arm-dis.c (enum isa): New enum.
1087         (struct sopcode32): New structure.
1088         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1089         set isa field of all current entries to ANY.
1090         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1091         Only match an entry if its isa field allows the current mode.
1092
1093 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1094
1095         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1096         CLRM.
1097         (print_insn_thumb32): Add logic to print %n CLRM register list.
1098
1099 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1100
1101         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1102         and %Q patterns.
1103
1104 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1105
1106         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1107         (print_insn_thumb32): Edit the switch case for %Z.
1108
1109 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1110
1111         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1112
1113 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1114
1115         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1116
1117 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1118
1119         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1120
1121 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1122
1123         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1124         Arm register with r13 and r15 unpredictable.
1125         (thumb32_opcodes): New instructions for bfx and bflx.
1126
1127 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1128
1129         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1130
1131 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1132
1133         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1134
1135 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1136
1137         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1138
1139 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1140
1141         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1142
1143 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1144
1145         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1146         "optr". ("operator" is a reserved word in c++).
1147
1148 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1149
1150         * aarch64-opc.c (aarch64_print_operand): Add case for
1151         AARCH64_OPND_Rt_SP.
1152         (verify_constraints): Likewise.
1153         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1154         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1155         to accept Rt|SP as first operand.
1156         (AARCH64_OPERANDS): Add new Rt_SP.
1157         * aarch64-asm-2.c: Regenerated.
1158         * aarch64-dis-2.c: Regenerated.
1159         * aarch64-opc-2.c: Regenerated.
1160
1161 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1162
1163         * aarch64-asm-2.c: Regenerated.
1164         * aarch64-dis-2.c: Likewise.
1165         * aarch64-opc-2.c: Likewise.
1166         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1167
1168 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1169
1170         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1171
1172 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1173
1174         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1175         * i386-init.h: Regenerated.
1176
1177 2019-04-07  Alan Modra  <amodra@gmail.com>
1178
1179         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1180         op_separator to control printing of spaces, comma and parens
1181         rather than need_comma, need_paren and spaces vars.
1182
1183 2019-04-07  Alan Modra  <amodra@gmail.com>
1184
1185         PR 24421
1186         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1187         (print_insn_neon, print_insn_arm): Likewise.
1188
1189 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1190
1191         * i386-dis-evex.h (evex_table): Updated to support BF16
1192         instructions.
1193         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1194         and EVEX_W_0F3872_P_3.
1195         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1196         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1197         * i386-opc.h (enum): Add CpuAVX512_BF16.
1198         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1199         * i386-opc.tbl: Add AVX512 BF16 instructions.
1200         * i386-init.h: Regenerated.
1201         * i386-tbl.h: Likewise.
1202
1203 2019-04-05  Alan Modra  <amodra@gmail.com>
1204
1205         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1206         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1207         to favour printing of "-" branch hint when using the "y" bit.
1208         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1209
1210 2019-04-05  Alan Modra  <amodra@gmail.com>
1211
1212         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1213         opcode until first operand is output.
1214
1215 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1216
1217         PR gas/24349
1218         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1219         (valid_bo_post_v2): Add support for 'at' branch hints.
1220         (insert_bo): Only error on branch on ctr.
1221         (get_bo_hint_mask): New function.
1222         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1223         for inserting 'at' branch hints.
1224         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1225         for extracting 'at' branch hints.
1226         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1227         (BOE): Delete operand.
1228         (BOM, BOP): New operands.
1229         (RM): Update value.
1230         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1231         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1232         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1233         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1234         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1235         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1236         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1237         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1238         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1239         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1240         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1241         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1242         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1243         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1244         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1245         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1246         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1247         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1248         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1249         bttarl+>: New extended mnemonics.
1250
1251 2019-03-28  Alan Modra  <amodra@gmail.com>
1252
1253         PR 24390
1254         * ppc-opc.c (BTF): Define.
1255         (powerpc_opcodes): Use for mtfsb*.
1256         * ppc-dis.c (print_insn_powerpc): Print fields with both
1257         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1258
1259 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1260
1261         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1262         (mapping_symbol_for_insn): Implement new algorithm.
1263         (print_insn): Remove duplicate code.
1264
1265 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1266
1267         * aarch64-dis.c (print_insn_aarch64):
1268         Implement override.
1269
1270 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1271
1272         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1273         order.
1274
1275 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1276
1277         * aarch64-dis.c (last_stop_offset): New.
1278         (print_insn_aarch64): Use stop_offset.
1279
1280 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1281
1282         PR gas/24359
1283         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1284         CPU_ANY_AVX2_FLAGS.
1285         * i386-init.h: Regenerated.
1286
1287 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1288
1289         PR gas/24348
1290         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1291         vmovdqu16, vmovdqu32 and vmovdqu64.
1292         * i386-tbl.h: Regenerated.
1293
1294 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1295
1296         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1297         from vstrszb, vstrszh, and vstrszf.
1298
1299 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1300
1301         * s390-opc.txt: Add instruction descriptions.
1302
1303 2019-02-08  Jim Wilson  <jimw@sifive.com>
1304
1305         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1306         <bne>: Likewise.
1307
1308 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1309
1310         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1311
1312 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1313
1314         PR binutils/23212
1315         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1316         * aarch64-opc.c (verify_elem_sd): New.
1317         (fields): Add FLD_sz entr.
1318         * aarch64-tbl.h (_SIMD_INSN): New.
1319         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1320         fmulx scalar and vector by element isns.
1321
1322 2019-02-07  Nick Clifton  <nickc@redhat.com>
1323
1324         * po/sv.po: Updated Swedish translation.
1325
1326 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1327
1328         * s390-mkopc.c (main): Accept arch13 as cpu string.
1329         * s390-opc.c: Add new instruction formats and instruction opcode
1330         masks.
1331         * s390-opc.txt: Add new arch13 instructions.
1332
1333 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1334
1335         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1336         (aarch64_opcode): Change encoding for stg, stzg
1337         st2g and st2zg.
1338         * aarch64-asm-2.c: Regenerated.
1339         * aarch64-dis-2.c: Regenerated.
1340         * aarch64-opc-2.c: Regenerated.
1341
1342 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1343
1344         * aarch64-asm-2.c: Regenerated.
1345         * aarch64-dis-2.c: Likewise.
1346         * aarch64-opc-2.c: Likewise.
1347         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1348
1349 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1350             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1351
1352         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1353         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1354         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1355         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1356         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1357         case for ldstgv_indexed.
1358         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1359         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1360         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1361         * aarch64-asm-2.c: Regenerated.
1362         * aarch64-dis-2.c: Regenerated.
1363         * aarch64-opc-2.c: Regenerated.
1364
1365 2019-01-23  Nick Clifton  <nickc@redhat.com>
1366
1367         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1368
1369 2019-01-21  Nick Clifton  <nickc@redhat.com>
1370
1371         * po/de.po: Updated German translation.
1372         * po/uk.po: Updated Ukranian translation.
1373
1374 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1375         * mips-dis.c (mips_arch_choices): Fix typo in
1376         gs464, gs464e and gs264e descriptors.
1377
1378 2019-01-19  Nick Clifton  <nickc@redhat.com>
1379
1380         * configure: Regenerate.
1381         * po/opcodes.pot: Regenerate.
1382
1383 2018-06-24  Nick Clifton  <nickc@redhat.com>
1384
1385         2.32 branch created.
1386
1387 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1388
1389         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1390         if it is null.
1391         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1392         zero.
1393
1394 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1395
1396         * configure: Regenerate.
1397
1398 2019-01-07  Alan Modra  <amodra@gmail.com>
1399
1400         * configure: Regenerate.
1401         * po/POTFILES.in: Regenerate.
1402
1403 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1404
1405         * s12z-opc.c: New file.
1406         * s12z-opc.h: New file.
1407         * s12z-dis.c: Removed all code not directly related to display
1408         of instructions.  Used the interface provided by the new files
1409         instead.
1410         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1411         * Makefile.in: Regenerate.
1412         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1413         * configure: Regenerate.
1414
1415 2019-01-01  Alan Modra  <amodra@gmail.com>
1416
1417         Update year range in copyright notice of all files.
1418
1419 For older changes see ChangeLog-2018
1420 \f
1421 Copyright (C) 2019 Free Software Foundation, Inc.
1422
1423 Copying and distribution of this file, with or without modification,
1424 are permitted in any medium without royalty provided the copyright
1425 notice and this notice are preserved.
1426
1427 Local Variables:
1428 mode: change-log
1429 left-margin: 8
1430 fill-column: 74
1431 version-control: never
1432 End: