1 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
3 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
4 `insn' together, with `extend' as the high-order 16 bits.
5 (match_kind): New enum.
6 (print_insn_mips16): Rework for 32-bit instruction matching.
7 Do not dump EXTEND prefixes here.
8 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
9 Recode `match' and `mask' fields as 32-bit in absolute "jal" and
12 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
14 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
15 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
18 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
20 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
21 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
24 2016-12-20 Andrew Waterman <andrew@sifive.com>
26 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
29 2016-12-20 Andrew Waterman <andrew@sifive.com>
31 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
34 2016-12-20 Andrew Waterman <andrew@sifive.com>
36 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
39 2016-12-20 Andrew Waterman <andrew@sifive.com>
41 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
42 XLEN when none is provided.
44 2016-12-20 Andrew Waterman <andrew@sifive.com>
46 * riscv-opc.c: Formatting fixes.
48 2016-12-20 Alan Modra <amodra@gmail.com>
50 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
51 * Makefile.in: Regenerate.
52 * po/POTFILES.in: Regenerate.
54 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
56 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
57 Only examine ELF file structures here.
59 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
61 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
62 `bfd_mips_elf_get_abiflags' here.
64 2016-12-16 Nick Clifton <nickc@redhat.com>
66 * arm-dis.c (print_insn_thumb32): Fix compile time warning
67 computing value_in_comment.
69 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
71 * mips-dis.c (mips_convert_abiflags_ases): New function.
72 (set_default_mips_dis_options): Also infer ASE flags from ELF
75 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
77 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
78 header flag interpretation code.
80 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
82 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
83 `pinfo2' with SP-relative "sd" entries.
85 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
87 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
90 2016-12-13 Renlin Li <renlin.li@arm.com>
92 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
94 (operand_general_constraint_met_p): Remove case for CP_REG.
95 (aarch64_print_operand): Print CRn, CRm operand using imm field.
96 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
98 (aarch64_opcode_table): Change CRn, CRm operand class and type.
99 * aarch64-opc-2.c : Regenerate.
100 * aarch64-asm-2.c : Likewise.
101 * aarch64-dis-2.c : Likewise.
103 2016-12-12 Yao Qi <yao.qi@linaro.org>
105 * rx-dis.c: Include <setjmp.h>
106 (struct private): New.
107 (rx_get_byte): Check return value of read_memory_func, and
108 call memory_error_func and OPCODES_SIGLONGJMP on error.
109 (print_insn_rx): Call OPCODES_SIGSETJMP.
111 2016-12-12 Yao Qi <yao.qi@linaro.org>
113 * rl78-dis.c: Include <setjmp.h>.
114 (struct private): New.
115 (rl78_get_byte): Check return value of read_memory_func, and
116 call memory_error_func and OPCODES_SIGLONGJMP on error.
117 (print_insn_rl78_common): Call OPCODES_SIGJMP.
119 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
121 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
123 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
125 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
128 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
130 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
131 to separate `extend' and its uninterpreted argument output.
132 Separate hexadecimal halves of undecoded extended instructions
135 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
137 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
138 indentation space across.
140 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
142 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
143 adjustment for PC-relative operations following MIPS16e compact
144 jumps or undefined RR/J(AL)R(C) encodings.
146 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
148 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
149 variable to `reglane_index'.
151 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
153 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
155 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
157 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
159 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
161 * mips16-opc.c (mips16_opcodes): Update comment naming structure
164 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
166 * mips-dis.c (print_mips_disassembler_options): Reformat output.
168 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
170 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
171 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
173 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
175 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
177 2016-12-01 Nick Clifton <nickc@redhat.com>
180 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
183 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
185 * arc-opc.c (insert_ra_chk): New function.
186 (insert_rb_chk): Likewise.
187 (insert_rad): Update text error message.
188 (insert_rcd): Likewise.
189 (insert_rhv2): Likewise.
190 (insert_r0): Likewise.
191 (insert_r1): Likewise.
192 (insert_r2): Likewise.
193 (insert_r3): Likewise.
194 (insert_sp): Likewise.
195 (insert_gp): Likewise.
196 (insert_pcl): Likewise.
197 (insert_blink): Likewise.
198 (insert_ilink1): Likewise.
199 (insert_ilink2): Likewise.
200 (insert_ras): Likewise.
201 (insert_rbs): Likewise.
202 (insert_rcs): Likewise.
203 (insert_simm3s): Likewise.
204 (insert_rrange): Likewise.
205 (insert_fpel): Likewise.
206 (insert_blinkel): Likewise.
207 (insert_pcel): Likewise.
208 (insert_nps_3bit_dst): Likewise.
209 (insert_nps_3bit_dst_short): Likewise.
210 (insert_nps_3bit_src2_short): Likewise.
211 (insert_nps_bitop_size_2b): Likewise.
212 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
217 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
218 * arc-tbl.h (div, divu): All instructions are DIVREM class.
219 Change first insn argument to check for LP_COUNT usage.
221 (ld, ldd): All instructions are LOAD class. Change first insn
222 argument to check for LP_COUNT usage.
223 (st, std): All instructions are STORE class.
224 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
225 Change first insn argument to check for LP_COUNT usage.
226 (mov): All instructions are MOVE class. Change first insn
227 argument to check for LP_COUNT usage.
229 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
231 * arc-dis.c (is_compatible_p): Remove function.
232 (skip_this_opcode): Don't add any decoding class to decode list.
234 (find_format_from_table): Go through all opcodes, and warn if we
235 use a guessed mnemonic.
237 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
238 Amit Pawar <amit.pawar@amd.com>
241 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
244 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
246 * configure: Regenerate.
248 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
250 * sparc-opc.c (HWS_V8): Definition moved from
251 gas/config/tc-sparc.c.
261 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
264 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
266 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
269 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
271 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
272 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
273 (aarch64_opcode_table): Add fcmla and fcadd.
274 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
275 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
276 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
277 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
278 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
279 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
280 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
281 (operand_general_constraint_met_p): Rotate and index range check.
282 (aarch64_print_operand): Handle rotate operand.
283 * aarch64-asm-2.c: Regenerate.
284 * aarch64-dis-2.c: Likewise.
285 * aarch64-opc-2.c: Likewise.
287 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
289 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
290 * aarch64-asm-2.c: Regenerate.
291 * aarch64-dis-2.c: Regenerate.
292 * aarch64-opc-2.c: Regenerate.
294 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
296 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
297 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
298 * aarch64-asm-2.c: Regenerate.
299 * aarch64-dis-2.c: Regenerate.
300 * aarch64-opc-2.c: Regenerate.
302 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
304 * aarch64-tbl.h (QL_X1NIL): New.
305 (arch64_opcode_table): Add ldraa, ldrab.
306 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
307 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
308 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
309 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
310 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
311 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
312 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
313 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
314 (aarch64_print_operand): Likewise.
315 * aarch64-asm-2.c: Regenerate.
316 * aarch64-dis-2.c: Regenerate.
317 * aarch64-opc-2.c: Regenerate.
319 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
321 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
322 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
323 * aarch64-asm-2.c: Regenerate.
324 * aarch64-dis-2.c: Regenerate.
325 * aarch64-opc-2.c: Regenerate.
327 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
329 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
330 (AARCH64_OPERANDS): Add Rm_SP.
331 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
332 * aarch64-asm-2.c: Regenerate.
333 * aarch64-dis-2.c: Regenerate.
334 * aarch64-opc-2.c: Regenerate.
336 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
338 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
339 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
340 autdzb, xpaci, xpacd.
341 * aarch64-asm-2.c: Regenerate.
342 * aarch64-dis-2.c: Regenerate.
343 * aarch64-opc-2.c: Regenerate.
345 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
347 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
348 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
349 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
350 (aarch64_sys_reg_supported_p): Add feature test for new registers.
352 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
354 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
355 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
356 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
358 * aarch64-asm-2.c: Regenerate.
359 * aarch64-dis-2.c: Regenerate.
361 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
363 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
365 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
368 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
369 * i386-dis.c (EdqwS): Removed.
370 (dqw_swap_mode): Likewise.
371 (intel_operand_size): Don't check dqw_swap_mode.
372 (OP_E_register): Likewise.
373 (OP_E_memory): Likewise.
376 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
377 * i386-tbl.h: Regerated.
379 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
381 * i386-opc.tbl: Merge AVX512F vmovq.
382 * i386-tbl.h: Regerated.
384 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
387 * i386-dis.c (THREE_BYTE_0F7A): Removed.
388 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
389 (three_byte_table): Remove THREE_BYTE_0F7A.
391 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
394 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
395 (FGRPd9_4): Replace 1 with 2.
396 (FGRPd9_5): Replace 2 with 3.
397 (FGRPd9_6): Replace 3 with 4.
398 (FGRPd9_7): Replace 4 with 5.
399 (FGRPda_5): Replace 5 with 6.
400 (FGRPdb_4): Replace 6 with 7.
401 (FGRPde_3): Replace 7 with 8.
402 (FGRPdf_4): Replace 8 with 9.
403 (fgrps): Add an entry for Bad_Opcode.
405 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
407 * arc-opc.c (arc_flag_operands): Add F_DI14.
408 (arc_flag_classes): Add C_DI14.
409 * arc-nps400-tbl.h: Add new exc instructions.
411 2016-11-03 Graham Markall <graham.markall@embecosm.com>
413 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
415 * arc-nps-400-tbl.h: Add dcmac instruction.
416 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
417 (insert_nps_rbdouble_64): Added.
418 (extract_nps_rbdouble_64): Added.
419 (insert_nps_proto_size): Added.
420 (extract_nps_proto_size): Added.
422 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
424 * arc-dis.c (struct arc_operand_iterator): Remove all fields
425 relating to long instruction processing, add new limm field.
426 (OPCODE): Rename to...
427 (OPCODE_32BIT_INSN): ...this.
429 (skip_this_opcode): Handle different instruction lengths, update
431 (special_flag_p): Update parameter type.
432 (find_format_from_table): Update for more instruction lengths.
433 (find_format_long_instructions): Delete.
434 (find_format): Update for more instruction lengths.
435 (arc_insn_length): Likewise.
436 (extract_operand_value): Update for more instruction lengths.
437 (operand_iterator_next): Remove code relating to long
439 (arc_opcode_to_insn_type): New function.
440 (print_insn_arc):Update for more instructions lengths.
441 * arc-ext.c (extInstruction_t): Change argument type.
442 * arc-ext.h (extInstruction_t): Change argument type.
443 * arc-fxi.h: Change type unsigned to unsigned long long
444 extensively throughout.
445 * arc-nps400-tbl.h: Add long instructions taken from
446 arc_long_opcodes table in arc-opc.c.
447 * arc-opc.c: Update parameter types on insert/extract handlers.
448 (arc_long_opcodes): Delete.
449 (arc_num_long_opcodes): Delete.
450 (arc_opcode_len): Update for more instruction lengths.
452 2016-11-03 Graham Markall <graham.markall@embecosm.com>
454 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
456 2016-11-03 Graham Markall <graham.markall@embecosm.com>
458 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
460 (find_format_long_instructions): Likewise.
461 * arc-opc.c (arc_opcode_len): New function.
463 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
465 * arc-nps400-tbl.h: Fix some instruction masks.
467 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
469 * i386-dis.c (REG_82): Removed.
470 (X86_64_82_REG_0): Likewise.
471 (X86_64_82_REG_1): Likewise.
472 (X86_64_82_REG_2): Likewise.
473 (X86_64_82_REG_3): Likewise.
474 (X86_64_82_REG_4): Likewise.
475 (X86_64_82_REG_5): Likewise.
476 (X86_64_82_REG_6): Likewise.
477 (X86_64_82_REG_7): Likewise.
479 (dis386): Use X86_64_82 instead of REG_82.
480 (reg_table): Remove REG_82.
481 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
482 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
483 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
486 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
489 * i386-dis.c (REG_82): New.
490 (X86_64_82_REG_0): Likewise.
491 (X86_64_82_REG_1): Likewise.
492 (X86_64_82_REG_2): Likewise.
493 (X86_64_82_REG_3): Likewise.
494 (X86_64_82_REG_4): Likewise.
495 (X86_64_82_REG_5): Likewise.
496 (X86_64_82_REG_6): Likewise.
497 (X86_64_82_REG_7): Likewise.
498 (dis386): Use REG_82.
499 (reg_table): Add REG_82.
500 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
501 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
502 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
504 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
506 * i386-dis.c (REG_82): Renamed to ...
509 (reg_table): Likewise.
511 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
513 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
514 * i386-dis-evex.h (evex_table): Updated.
515 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
516 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
517 (cpu_flags): Add CpuAVX512_4VNNIW.
518 * i386-opc.h (enum): (AVX512_4VNNIW): New.
519 (i386_cpu_flags): Add cpuavx512_4vnniw.
520 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
521 * i386-init.h: Regenerate.
524 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
526 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
527 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
528 * i386-dis-evex.h (evex_table): Updated.
529 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
530 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
531 (cpu_flags): Add CpuAVX512_4FMAPS.
532 (opcode_modifiers): Add ImplicitQuadGroup modifier.
533 * i386-opc.h (AVX512_4FMAP): New.
534 (i386_cpu_flags): Add cpuavx512_4fmaps.
535 (ImplicitQuadGroup): New.
536 (i386_opcode_modifier): Add implicitquadgroup.
537 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
538 * i386-init.h: Regenerate.
541 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
542 Andrew Waterman <andrew@sifive.com>
544 Add support for RISC-V architecture.
545 * configure.ac: Add entry for bfd_riscv_arch.
546 * configure: Regenerate.
547 * disassemble.c (disassembler): Add support for riscv.
548 (disassembler_usage): Likewise.
549 * riscv-dis.c: New file.
550 * riscv-opc.c: New file.
552 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
554 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
555 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
556 (rm_table): Update the RM_0FAE_REG_7 entry.
557 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
558 (cpu_flags): Remove CpuPCOMMIT.
559 * i386-opc.h (CpuPCOMMIT): Removed.
560 (i386_cpu_flags): Remove cpupcommit.
561 * i386-opc.tbl: Remove pcommit.
562 * i386-init.h: Regenerated.
563 * i386-tbl.h: Likewise.
565 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
568 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
569 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
570 32-bit mode. Don't check vex.register_specifier in 32-bit
572 (OP_VEX): Check for invalid mask registers.
574 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
577 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
580 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
583 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
585 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
587 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
588 local variable to `index_regno'.
590 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
592 * arc-tbl.h: Removed any "inv.+" instructions from the table.
594 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
596 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
599 2016-10-11 Jiong Wang <jiong.wang@arm.com>
602 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
604 2016-10-07 Jiong Wang <jiong.wang@arm.com>
607 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
610 2016-10-07 Alan Modra <amodra@gmail.com>
612 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
614 2016-10-06 Alan Modra <amodra@gmail.com>
616 * aarch64-opc.c: Spell fall through comments consistently.
617 * i386-dis.c: Likewise.
618 * aarch64-dis.c: Add missing fall through comments.
619 * aarch64-opc.c: Likewise.
620 * arc-dis.c: Likewise.
621 * arm-dis.c: Likewise.
622 * i386-dis.c: Likewise.
623 * m68k-dis.c: Likewise.
624 * mep-asm.c: Likewise.
625 * ns32k-dis.c: Likewise.
626 * sh-dis.c: Likewise.
627 * tic4x-dis.c: Likewise.
628 * tic6x-dis.c: Likewise.
629 * vax-dis.c: Likewise.
631 2016-10-06 Alan Modra <amodra@gmail.com>
633 * arc-ext.c (create_map): Add missing break.
634 * msp430-decode.opc (encode_as): Likewise.
635 * msp430-decode.c: Regenerate.
637 2016-10-06 Alan Modra <amodra@gmail.com>
639 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
640 * crx-dis.c (print_insn_crx): Likewise.
642 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
645 * i386-dis.c (putop): Don't assign alt twice.
647 2016-09-29 Jiong Wang <jiong.wang@arm.com>
650 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
652 2016-09-29 Alan Modra <amodra@gmail.com>
654 * ppc-opc.c (L): Make compulsory.
655 (LOPT): New, optional form of L.
656 (HTM_R): Define as LOPT.
658 (L32OPT): New, optional for 32-bit L.
659 (L2OPT): New, 2-bit L for dcbf.
662 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
663 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
665 <tlbiel, tlbie>: Use LOPT.
666 <wclr, wclrall>: Use L2.
668 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
670 * Makefile.in: Regenerate.
671 * configure: Likewise.
673 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
675 * arc-ext-tbl.h (EXTINSN2OPF): Define.
676 (EXTINSN2OP): Use EXTINSN2OPF.
677 (bspeekm, bspop, modapp): New extension instructions.
678 * arc-opc.c (F_DNZ_ND): Define.
683 * arc-tbl.h (dbnz): New instruction.
684 (prealloc): Allow it for ARC EM.
687 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
689 * aarch64-opc.c (print_immediate_offset_address): Print spaces
690 after commas in addresses.
691 (aarch64_print_operand): Likewise.
693 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
695 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
696 rather than "should be" or "expected to be" in error messages.
698 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
700 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
701 (print_mnemonic_name): ...here.
702 (print_comment): New function.
703 (print_aarch64_insn): Call it.
704 * aarch64-opc.c (aarch64_conds): Add SVE names.
705 (aarch64_print_operand): Print alternative condition names in
708 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
710 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
711 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
712 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
713 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
714 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
715 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
716 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
717 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
718 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
719 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
720 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
721 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
722 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
723 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
724 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
725 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
726 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
727 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
728 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
729 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
730 (OP_SVE_XWU, OP_SVE_XXU): New macros.
731 (aarch64_feature_sve): New variable.
733 (_SVE_INSN): Likewise.
734 (aarch64_opcode_table): Add SVE instructions.
735 * aarch64-opc.h (extract_fields): Declare.
736 * aarch64-opc-2.c: Regenerate.
737 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
738 * aarch64-asm-2.c: Regenerate.
739 * aarch64-dis.c (extract_fields): Make global.
740 (do_misc_decoding): Handle the new SVE aarch64_ops.
741 * aarch64-dis-2.c: Regenerate.
743 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
745 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
746 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
748 * aarch64-opc.c (fields): Add corresponding entries.
749 * aarch64-asm.c (aarch64_get_variant): New function.
750 (aarch64_encode_variant_using_iclass): Likewise.
751 (aarch64_opcode_encode): Call it.
752 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
753 (aarch64_opcode_decode): Call it.
755 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
757 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
758 and FP register operands.
759 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
760 (FLD_SVE_Vn): New aarch64_field_kinds.
761 * aarch64-opc.c (fields): Add corresponding entries.
762 (aarch64_print_operand): Handle the new SVE core and FP register
764 * aarch64-opc-2.c: Regenerate.
765 * aarch64-asm-2.c: Likewise.
766 * aarch64-dis-2.c: Likewise.
768 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
770 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
772 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
773 * aarch64-opc.c (fields): Add corresponding entry.
774 (operand_general_constraint_met_p): Handle the new SVE FP immediate
776 (aarch64_print_operand): Likewise.
777 * aarch64-opc-2.c: Regenerate.
778 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
779 (ins_sve_float_zero_one): New inserters.
780 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
781 (aarch64_ins_sve_float_half_two): Likewise.
782 (aarch64_ins_sve_float_zero_one): Likewise.
783 * aarch64-asm-2.c: Regenerate.
784 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
785 (ext_sve_float_zero_one): New extractors.
786 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
787 (aarch64_ext_sve_float_half_two): Likewise.
788 (aarch64_ext_sve_float_zero_one): Likewise.
789 * aarch64-dis-2.c: Regenerate.
791 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
793 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
794 integer immediate operands.
795 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
796 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
797 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
798 * aarch64-opc.c (fields): Add corresponding entries.
799 (operand_general_constraint_met_p): Handle the new SVE integer
801 (aarch64_print_operand): Likewise.
802 (aarch64_sve_dupm_mov_immediate_p): New function.
803 * aarch64-opc-2.c: Regenerate.
804 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
805 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
806 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
807 (aarch64_ins_limm): ...here.
808 (aarch64_ins_inv_limm): New function.
809 (aarch64_ins_sve_aimm): Likewise.
810 (aarch64_ins_sve_asimm): Likewise.
811 (aarch64_ins_sve_limm_mov): Likewise.
812 (aarch64_ins_sve_shlimm): Likewise.
813 (aarch64_ins_sve_shrimm): Likewise.
814 * aarch64-asm-2.c: Regenerate.
815 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
816 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
817 * aarch64-dis.c (decode_limm): New function, split out from...
818 (aarch64_ext_limm): ...here.
819 (aarch64_ext_inv_limm): New function.
820 (decode_sve_aimm): Likewise.
821 (aarch64_ext_sve_aimm): Likewise.
822 (aarch64_ext_sve_asimm): Likewise.
823 (aarch64_ext_sve_limm_mov): Likewise.
824 (aarch64_top_bit): Likewise.
825 (aarch64_ext_sve_shlimm): Likewise.
826 (aarch64_ext_sve_shrimm): Likewise.
827 * aarch64-dis-2.c: Regenerate.
829 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
831 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
833 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
834 the AARCH64_MOD_MUL_VL entry.
835 (value_aligned_p): Cope with non-power-of-two alignments.
836 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
837 (print_immediate_offset_address): Likewise.
838 (aarch64_print_operand): Likewise.
839 * aarch64-opc-2.c: Regenerate.
840 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
841 (ins_sve_addr_ri_s9xvl): New inserters.
842 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
843 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
844 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
845 * aarch64-asm-2.c: Regenerate.
846 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
847 (ext_sve_addr_ri_s9xvl): New extractors.
848 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
849 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
850 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
851 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
852 * aarch64-dis-2.c: Regenerate.
854 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
856 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
858 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
859 (FLD_SVE_xs_22): New aarch64_field_kinds.
860 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
861 (get_operand_specific_data): New function.
862 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
863 FLD_SVE_xs_14 and FLD_SVE_xs_22.
864 (operand_general_constraint_met_p): Handle the new SVE address
866 (sve_reg): New array.
867 (get_addr_sve_reg_name): New function.
868 (aarch64_print_operand): Handle the new SVE address operands.
869 * aarch64-opc-2.c: Regenerate.
870 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
871 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
872 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
873 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
874 (aarch64_ins_sve_addr_rr_lsl): Likewise.
875 (aarch64_ins_sve_addr_rz_xtw): Likewise.
876 (aarch64_ins_sve_addr_zi_u5): Likewise.
877 (aarch64_ins_sve_addr_zz): Likewise.
878 (aarch64_ins_sve_addr_zz_lsl): Likewise.
879 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
880 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
881 * aarch64-asm-2.c: Regenerate.
882 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
883 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
884 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
885 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
886 (aarch64_ext_sve_addr_ri_u6): Likewise.
887 (aarch64_ext_sve_addr_rr_lsl): Likewise.
888 (aarch64_ext_sve_addr_rz_xtw): Likewise.
889 (aarch64_ext_sve_addr_zi_u5): Likewise.
890 (aarch64_ext_sve_addr_zz): Likewise.
891 (aarch64_ext_sve_addr_zz_lsl): Likewise.
892 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
893 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
894 * aarch64-dis-2.c: Regenerate.
896 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
898 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
899 AARCH64_OPND_SVE_PATTERN_SCALED.
900 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
901 * aarch64-opc.c (fields): Add a corresponding entry.
902 (set_multiplier_out_of_range_error): New function.
903 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
904 (operand_general_constraint_met_p): Handle
905 AARCH64_OPND_SVE_PATTERN_SCALED.
906 (print_register_offset_address): Use PRIi64 to print the
908 (aarch64_print_operand): Likewise. Handle
909 AARCH64_OPND_SVE_PATTERN_SCALED.
910 * aarch64-opc-2.c: Regenerate.
911 * aarch64-asm.h (ins_sve_scale): New inserter.
912 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
913 * aarch64-asm-2.c: Regenerate.
914 * aarch64-dis.h (ext_sve_scale): New inserter.
915 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
916 * aarch64-dis-2.c: Regenerate.
918 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
920 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
921 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
922 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
923 (FLD_SVE_prfop): Likewise.
924 * aarch64-opc.c: Include libiberty.h.
925 (aarch64_sve_pattern_array): New variable.
926 (aarch64_sve_prfop_array): Likewise.
927 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
928 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
929 AARCH64_OPND_SVE_PRFOP.
930 * aarch64-asm-2.c: Regenerate.
931 * aarch64-dis-2.c: Likewise.
932 * aarch64-opc-2.c: Likewise.
934 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
936 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
937 AARCH64_OPND_QLF_P_[ZM].
938 (aarch64_print_operand): Print /z and /m where appropriate.
940 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
942 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
943 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
944 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
945 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
946 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
947 * aarch64-opc.c (fields): Add corresponding entries here.
948 (operand_general_constraint_met_p): Check that SVE register lists
949 have the correct length. Check the ranges of SVE index registers.
950 Check for cases where p8-p15 are used in 3-bit predicate fields.
951 (aarch64_print_operand): Handle the new SVE operands.
952 * aarch64-opc-2.c: Regenerate.
953 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
954 * aarch64-asm.c (aarch64_ins_sve_index): New function.
955 (aarch64_ins_sve_reglist): Likewise.
956 * aarch64-asm-2.c: Regenerate.
957 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
958 * aarch64-dis.c (aarch64_ext_sve_index): New function.
959 (aarch64_ext_sve_reglist): Likewise.
960 * aarch64-dis-2.c: Regenerate.
962 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
964 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
965 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
966 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
967 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
970 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
972 * aarch64-opc.c (get_offset_int_reg_name): New function.
973 (print_immediate_offset_address): Likewise.
974 (print_register_offset_address): Take the base and offset
975 registers as parameters.
976 (aarch64_print_operand): Update caller accordingly. Use
977 print_immediate_offset_address.
979 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
981 * aarch64-opc.c (BANK): New macro.
982 (R32, R64): Take a register number as argument
985 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
987 * aarch64-opc.c (print_register_list): Add a prefix parameter.
988 (aarch64_print_operand): Update accordingly.
990 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
992 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
994 * aarch64-asm.h (ins_fpimm): New inserter.
995 * aarch64-asm.c (aarch64_ins_fpimm): New function.
996 * aarch64-asm-2.c: Regenerate.
997 * aarch64-dis.h (ext_fpimm): New extractor.
998 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
999 (aarch64_ext_fpimm): New function.
1000 * aarch64-dis-2.c: Regenerate.
1002 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1004 * aarch64-asm.c: Include libiberty.h.
1005 (insert_fields): New function.
1006 (aarch64_ins_imm): Use it.
1007 * aarch64-dis.c (extract_fields): New function.
1008 (aarch64_ext_imm): Use it.
1010 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1012 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1013 with an esize parameter.
1014 (operand_general_constraint_met_p): Update accordingly.
1015 Fix misindented code.
1016 * aarch64-asm.c (aarch64_ins_limm): Update call to
1017 aarch64_logical_immediate_p.
1019 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1021 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1023 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1025 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1027 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1029 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1031 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1033 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1034 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1035 xor3>: Delete mnemonics.
1036 <cp_abort>: Rename mnemonic from ...
1037 <cpabort>: ...to this.
1038 <setb>: Change to a X form instruction.
1039 <sync>: Change to 1 operand form.
1040 <copy>: Delete mnemonic.
1041 <copy_first>: Rename mnemonic from ...
1043 <paste, paste.>: Delete mnemonics.
1044 <paste_last>: Rename mnemonic from ...
1045 <paste.>: ...to this.
1047 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1049 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1051 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1053 * s390-mkopc.c (main): Support alternate arch strings.
1055 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1057 * s390-opc.txt: Fix kmctr instruction type.
1059 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1061 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1062 * i386-init.h: Regenerated.
1064 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1066 * opcodes/arc-dis.c (print_insn_arc): Changed.
1068 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1070 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1073 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1075 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1076 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1077 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1079 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1081 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1082 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1083 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1084 PREFIX_MOD_3_0FAE_REG_4.
1085 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1086 PREFIX_MOD_3_0FAE_REG_4.
1087 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1088 (cpu_flags): Add CpuPTWRITE.
1089 * i386-opc.h (CpuPTWRITE): New.
1090 (i386_cpu_flags): Add cpuptwrite.
1091 * i386-opc.tbl: Add ptwrite instruction.
1092 * i386-init.h: Regenerated.
1093 * i386-tbl.h: Likewise.
1095 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1097 * arc-dis.h: Wrap around in extern "C".
1099 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1101 * aarch64-tbl.h (V8_2_INSN): New macro.
1102 (aarch64_opcode_table): Use it.
1104 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1106 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1107 CORE_INSN, __FP_INSN and SIMD_INSN.
1109 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1111 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1112 (aarch64_opcode_table): Update uses accordingly.
1114 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1115 Kwok Cheung Yeung <kcy@codesourcery.com>
1118 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1119 'e_cmplwi' to 'e_cmpli' instead.
1120 (OPVUPRT, OPVUPRT_MASK): Define.
1121 (powerpc_opcodes): Add E200Z4 insns.
1122 (vle_opcodes): Add context save/restore insns.
1124 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1126 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1127 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1130 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1132 * arc-nps400-tbl.h: Change block comments to GNU format.
1133 * arc-dis.c: Add new globals addrtypenames,
1134 addrtypenames_max, and addtypeunknown.
1135 (get_addrtype): New function.
1136 (print_insn_arc): Print colons and address types when
1138 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1139 define insert and extract functions for all address types.
1140 (arc_operands): Add operands for colon and all address
1142 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1143 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1144 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1145 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1146 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1147 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1149 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1151 * configure: Regenerated.
1153 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1155 * arc-dis.c (skipclass): New structure.
1156 (decodelist): New variable.
1157 (is_compatible_p): New function.
1158 (new_element): Likewise.
1159 (skip_class_p): Likewise.
1160 (find_format_from_table): Use skip_class_p function.
1161 (find_format): Decode first the extension instructions.
1162 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1164 (parse_option): New function.
1165 (parse_disassembler_options): Likewise.
1166 (print_arc_disassembler_options): Likewise.
1167 (print_insn_arc): Use parse_disassembler_options function. Proper
1168 select ARCv2 cpu variant.
1169 * disassemble.c (disassembler_usage): Add ARC disassembler
1172 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1174 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1175 annotation from the "nal" entry and reorder it beyond "bltzal".
1177 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1179 * sparc-opc.c (ldtxa): New macro.
1180 (sparc_opcodes): Use the macro defined above to add entries for
1181 the LDTXA instructions.
1182 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1185 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1187 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1190 2016-07-01 Jan Beulich <jbeulich@suse.com>
1192 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1193 (movzb): Adjust to cover all permitted suffixes.
1195 * i386-tbl.h: Re-generate.
1197 2016-07-01 Jan Beulich <jbeulich@suse.com>
1199 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1200 (lgdt): Remove Tbyte from non-64-bit variant.
1201 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1202 xsaves64, xsavec64): Remove Disp16.
1203 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1204 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1206 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1207 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1208 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1210 * i386-tbl.h: Re-generate.
1212 2016-07-01 Jan Beulich <jbeulich@suse.com>
1214 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1215 * i386-tbl.h: Re-generate.
1217 2016-06-30 Yao Qi <yao.qi@linaro.org>
1219 * arm-dis.c (print_insn): Fix typo in comment.
1221 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1223 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1224 range of ldst_elemlist operands.
1225 (print_register_list): Use PRIi64 to print the index.
1226 (aarch64_print_operand): Likewise.
1228 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1230 * mcore-opc.h: Remove sentinal.
1231 * mcore-dis.c (print_insn_mcore): Adjust.
1233 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1235 * arc-opc.c: Correct description of availability of NPS400
1238 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1240 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1241 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1242 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1243 xor3>: New mnemonics.
1244 <setb>: Change to a VX form instruction.
1245 (insert_sh6): Add support for rldixor.
1246 (extract_sh6): Likewise.
1248 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1250 * arc-ext.h: Wrap in extern C.
1252 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1254 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1255 Use same method for determining instruction length on ARC700 and
1257 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1258 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1259 with the NPS400 subclass.
1260 * arc-opc.c: Likewise.
1262 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1264 * sparc-opc.c (rdasr): New macro.
1270 (sparc_opcodes): Use the macros above to fix and expand the
1271 definition of read/write instructions from/to
1272 asr/privileged/hyperprivileged instructions.
1273 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1274 %hva_mask_nz. Prefer softint_set and softint_clear over
1275 set_softint and clear_softint.
1276 (print_insn_sparc): Support %ver in Rd.
1278 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1280 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1281 architecture according to the hardware capabilities they require.
1283 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1285 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1286 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1287 bfd_mach_sparc_v9{c,d,e,v,m}.
1288 * sparc-opc.c (MASK_V9C): Define.
1289 (MASK_V9D): Likewise.
1290 (MASK_V9E): Likewise.
1291 (MASK_V9V): Likewise.
1292 (MASK_V9M): Likewise.
1293 (v6): Add MASK_V9{C,D,E,V,M}.
1294 (v6notlet): Likewise.
1298 (v9andleon): Likewise.
1306 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1308 2016-06-15 Nick Clifton <nickc@redhat.com>
1310 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1311 constants to match expected behaviour.
1312 (nds32_parse_opcode): Likewise. Also for whitespace.
1314 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1316 * arc-opc.c (extract_rhv1): Extract value from insn.
1318 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1320 * arc-nps400-tbl.h: Add ldbit instruction.
1321 * arc-opc.c: Add flag classes required for ldbit.
1323 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1325 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1326 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1327 support the above instructions.
1329 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1331 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1332 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1333 csma, cbba, zncv, and hofs.
1334 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1335 support the above instructions.
1337 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1339 * arc-nps400-tbl.h: Add andab and orab instructions.
1341 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1343 * arc-nps400-tbl.h: Add addl-like instructions.
1345 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1347 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1349 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1351 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1354 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1356 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1358 (init_disasm): Handle new command line option "insnlength".
1359 (print_s390_disassembler_options): Mention new option in help
1361 (print_insn_s390): Use the encoded insn length when dumping
1362 unknown instructions.
1364 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1366 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1367 to the address and set as symbol address for LDS/ STS immediate operands.
1369 2016-06-07 Alan Modra <amodra@gmail.com>
1371 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1372 cpu for "vle" to e500.
1373 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1374 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1375 (PPCNONE): Delete, substitute throughout.
1376 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1377 except for major opcode 4 and 31.
1378 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1380 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1382 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1383 ARM_EXT_RAS in relevant entries.
1385 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1388 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1391 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1394 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1395 (indir_v_mode): New.
1396 Add comments for '&'.
1397 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1398 (putop): Handle '&'.
1399 (intel_operand_size): Handle indir_v_mode.
1400 (OP_E_register): Likewise.
1401 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1402 64-bit indirect call/jmp for AMD64.
1403 * i386-tbl.h: Regenerated
1405 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1407 * arc-dis.c (struct arc_operand_iterator): New structure.
1408 (find_format_from_table): All the old content from find_format,
1409 with some minor adjustments, and parameter renaming.
1410 (find_format_long_instructions): New function.
1411 (find_format): Rewritten.
1412 (arc_insn_length): Add LSB parameter.
1413 (extract_operand_value): New function.
1414 (operand_iterator_next): New function.
1415 (print_insn_arc): Use new functions to find opcode, and iterator
1417 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1418 (extract_nps_3bit_dst_short): New function.
1419 (insert_nps_3bit_src2_short): New function.
1420 (extract_nps_3bit_src2_short): New function.
1421 (insert_nps_bitop1_size): New function.
1422 (extract_nps_bitop1_size): New function.
1423 (insert_nps_bitop2_size): New function.
1424 (extract_nps_bitop2_size): New function.
1425 (insert_nps_bitop_mod4_msb): New function.
1426 (extract_nps_bitop_mod4_msb): New function.
1427 (insert_nps_bitop_mod4_lsb): New function.
1428 (extract_nps_bitop_mod4_lsb): New function.
1429 (insert_nps_bitop_dst_pos3_pos4): New function.
1430 (extract_nps_bitop_dst_pos3_pos4): New function.
1431 (insert_nps_bitop_ins_ext): New function.
1432 (extract_nps_bitop_ins_ext): New function.
1433 (arc_operands): Add new operands.
1434 (arc_long_opcodes): New global array.
1435 (arc_num_long_opcodes): New global.
1436 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1438 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1440 * nds32-asm.h: Add extern "C".
1441 * sh-opc.h: Likewise.
1443 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1445 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1446 0,b,limm to the rflt instruction.
1448 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1450 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1453 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1456 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1457 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1458 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1459 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1460 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1461 * i386-init.h: Regenerated.
1463 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1466 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1467 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1468 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1469 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1470 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1471 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1472 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1473 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1474 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1475 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1476 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1477 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1478 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1479 CpuRegMask for AVX512.
1480 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1482 (set_bitfield_from_cpu_flag_init): New function.
1483 (set_bitfield): Remove const on f. Call
1484 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1485 * i386-opc.h (CpuRegMMX): New.
1486 (CpuRegXMM): Likewise.
1487 (CpuRegYMM): Likewise.
1488 (CpuRegZMM): Likewise.
1489 (CpuRegMask): Likewise.
1490 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1492 * i386-init.h: Regenerated.
1493 * i386-tbl.h: Likewise.
1495 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1498 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1499 (opcode_modifiers): Add AMD64 and Intel64.
1500 (main): Properly verify CpuMax.
1501 * i386-opc.h (CpuAMD64): Removed.
1502 (CpuIntel64): Likewise.
1503 (CpuMax): Set to CpuNo64.
1504 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1506 (Intel64): Likewise.
1507 (i386_opcode_modifier): Add amd64 and intel64.
1508 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1510 * i386-init.h: Regenerated.
1511 * i386-tbl.h: Likewise.
1513 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1516 * i386-gen.c (main): Fail if CpuMax is incorrect.
1517 * i386-opc.h (CpuMax): Set to CpuIntel64.
1518 * i386-tbl.h: Regenerated.
1520 2016-05-27 Nick Clifton <nickc@redhat.com>
1523 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1524 (msp430dis_opcode_unsigned): New function.
1525 (msp430dis_opcode_signed): New function.
1526 (msp430_singleoperand): Use the new opcode reading functions.
1527 Only disassenmble bytes if they were successfully read.
1528 (msp430_doubleoperand): Likewise.
1529 (msp430_branchinstr): Likewise.
1530 (msp430x_callx_instr): Likewise.
1531 (print_insn_msp430): Check that it is safe to read bytes before
1532 attempting disassembly. Use the new opcode reading functions.
1534 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1536 * ppc-opc.c (CY): New define. Document it.
1537 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1539 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1541 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1542 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1543 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1544 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1546 * i386-init.h: Regenerated.
1548 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1551 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1552 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1553 * i386-init.h: Regenerated.
1555 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1557 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1558 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1559 * i386-init.h: Regenerated.
1561 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1563 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1565 (print_insn_arc): Set insn_type information.
1566 * arc-opc.c (C_CC): Add F_CLASS_COND.
1567 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1568 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1569 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1570 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1571 (brne, brne_s, jeq_s, jne_s): Likewise.
1573 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1575 * arc-tbl.h (neg): New instruction variant.
1577 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1579 * arc-dis.c (find_format, find_format, get_auxreg)
1580 (print_insn_arc): Changed.
1581 * arc-ext.h (INSERT_XOP): Likewise.
1583 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1585 * tic54x-dis.c (sprint_mmr): Adjust.
1586 * tic54x-opc.c: Likewise.
1588 2016-05-19 Alan Modra <amodra@gmail.com>
1590 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1592 2016-05-19 Alan Modra <amodra@gmail.com>
1594 * ppc-opc.c: Formatting.
1595 (NSISIGNOPT): Define.
1596 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1598 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1600 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1601 replacing references to `micromips_ase' throughout.
1602 (_print_insn_mips): Don't use file-level microMIPS annotation to
1603 determine the disassembly mode with the symbol table.
1605 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1607 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1609 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1611 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1613 * mips-opc.c (D34): New macro.
1614 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1616 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1618 * i386-dis.c (prefix_table): Add RDPID instruction.
1619 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1620 (cpu_flags): Add RDPID bitfield.
1621 * i386-opc.h (enum): Add RDPID element.
1622 (i386_cpu_flags): Add RDPID field.
1623 * i386-opc.tbl: Add RDPID instruction.
1624 * i386-init.h: Regenerate.
1625 * i386-tbl.h: Regenerate.
1627 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1629 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1630 branch type of a symbol.
1631 (print_insn): Likewise.
1633 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1635 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1636 Mainline Security Extensions instructions.
1637 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1638 Extensions instructions.
1639 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1641 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1644 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1646 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1648 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1650 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1651 (arcExtMap_genOpcode): Likewise.
1652 * arc-opc.c (arg_32bit_rc): Define new variable.
1653 (arg_32bit_u6): Likewise.
1654 (arg_32bit_limm): Likewise.
1656 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1658 * aarch64-gen.c (VERIFIER): Define.
1659 * aarch64-opc.c (VERIFIER): Define.
1660 (verify_ldpsw): Use static linkage.
1661 * aarch64-opc.h (verify_ldpsw): Remove.
1662 * aarch64-tbl.h: Use VERIFIER for verifiers.
1664 2016-04-28 Nick Clifton <nickc@redhat.com>
1667 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1668 * aarch64-opc.c (verify_ldpsw): New function.
1669 * aarch64-opc.h (verify_ldpsw): New prototype.
1670 * aarch64-tbl.h: Add initialiser for verifier field.
1671 (LDPSW): Set verifier to verify_ldpsw.
1673 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1677 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1678 smaller than address size.
1680 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1682 * alpha-dis.c: Regenerate.
1683 * crx-dis.c: Likewise.
1684 * disassemble.c: Likewise.
1685 * epiphany-opc.c: Likewise.
1686 * fr30-opc.c: Likewise.
1687 * frv-opc.c: Likewise.
1688 * ip2k-opc.c: Likewise.
1689 * iq2000-opc.c: Likewise.
1690 * lm32-opc.c: Likewise.
1691 * lm32-opinst.c: Likewise.
1692 * m32c-opc.c: Likewise.
1693 * m32r-opc.c: Likewise.
1694 * m32r-opinst.c: Likewise.
1695 * mep-opc.c: Likewise.
1696 * mt-opc.c: Likewise.
1697 * or1k-opc.c: Likewise.
1698 * or1k-opinst.c: Likewise.
1699 * tic80-opc.c: Likewise.
1700 * xc16x-opc.c: Likewise.
1701 * xstormy16-opc.c: Likewise.
1703 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1705 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1706 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1707 calcsd, and calcxd instructions.
1708 * arc-opc.c (insert_nps_bitop_size): Delete.
1709 (extract_nps_bitop_size): Delete.
1710 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1711 (extract_nps_qcmp_m3): Define.
1712 (extract_nps_qcmp_m2): Define.
1713 (extract_nps_qcmp_m1): Define.
1714 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1715 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1716 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1717 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1718 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1721 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1723 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1725 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1727 * Makefile.in: Regenerated with automake 1.11.6.
1728 * aclocal.m4: Likewise.
1730 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1732 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1734 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1735 (extract_nps_cmem_uimm16): New function.
1736 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1738 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1740 * arc-dis.c (arc_insn_length): New function.
1741 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1742 (find_format): Change insnLen parameter to unsigned.
1744 2016-04-13 Nick Clifton <nickc@redhat.com>
1747 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1748 the LD.B and LD.BU instructions.
1750 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1752 * arc-dis.c (find_format): Check for extension flags.
1753 (print_flags): New function.
1754 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1756 * arc-ext.c (arcExtMap_coreRegName): Use
1757 LAST_EXTENSION_CORE_REGISTER.
1758 (arcExtMap_coreReadWrite): Likewise.
1759 (dump_ARC_extmap): Update printing.
1760 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1761 (arc_aux_regs): Add cpu field.
1762 * arc-regs.h: Add cpu field, lower case name aux registers.
1764 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1766 * arc-tbl.h: Add rtsc, sleep with no arguments.
1768 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1770 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1772 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1773 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1774 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1775 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1776 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1777 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1778 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1779 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1780 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1781 (arc_opcode arc_opcodes): Null terminate the array.
1782 (arc_num_opcodes): Remove.
1783 * arc-ext.h (INSERT_XOP): Define.
1784 (extInstruction_t): Likewise.
1785 (arcExtMap_instName): Delete.
1786 (arcExtMap_insn): New function.
1787 (arcExtMap_genOpcode): Likewise.
1788 * arc-ext.c (ExtInstruction): Remove.
1789 (create_map): Zero initialize instruction fields.
1790 (arcExtMap_instName): Remove.
1791 (arcExtMap_insn): New function.
1792 (dump_ARC_extmap): More info while debuging.
1793 (arcExtMap_genOpcode): New function.
1794 * arc-dis.c (find_format): New function.
1795 (print_insn_arc): Use find_format.
1796 (arc_get_disassembler): Enable dump_ARC_extmap only when
1799 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1801 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1802 instruction bits out.
1804 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1806 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1807 * arc-opc.c (arc_flag_operands): Add new flags.
1808 (arc_flag_classes): Add new classes.
1810 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1812 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1814 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1816 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1817 encode1, rflt, crc16, and crc32 instructions.
1818 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1819 (arc_flag_classes): Add C_NPS_R.
1820 (insert_nps_bitop_size_2b): New function.
1821 (extract_nps_bitop_size_2b): Likewise.
1822 (insert_nps_bitop_uimm8): Likewise.
1823 (extract_nps_bitop_uimm8): Likewise.
1824 (arc_operands): Add new operand entries.
1826 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1828 * arc-regs.h: Add a new subclass field. Add double assist
1829 accumulator register values.
1830 * arc-tbl.h: Use DPA subclass to mark the double assist
1831 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1832 * arc-opc.c (RSP): Define instead of SP.
1833 (arc_aux_regs): Add the subclass field.
1835 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1837 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1839 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1841 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1844 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1846 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1847 issues. No functional changes.
1849 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1851 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1852 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1853 (RTT): Remove duplicate.
1854 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1855 (PCT_CONFIG*): Remove.
1856 (D1L, D1H, D2H, D2L): Define.
1858 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1860 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1862 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1864 * arc-tbl.h (invld07): Remove.
1865 * arc-ext-tbl.h: New file.
1866 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1867 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1869 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1871 Fix -Wstack-usage warnings.
1872 * aarch64-dis.c (print_operands): Substitute size.
1873 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1875 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1877 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1878 to get a proper diagnostic when an invalid ASR register is used.
1880 2016-03-22 Nick Clifton <nickc@redhat.com>
1882 * configure: Regenerate.
1884 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1886 * arc-nps400-tbl.h: New file.
1887 * arc-opc.c: Add top level comment.
1888 (insert_nps_3bit_dst): New function.
1889 (extract_nps_3bit_dst): New function.
1890 (insert_nps_3bit_src2): New function.
1891 (extract_nps_3bit_src2): New function.
1892 (insert_nps_bitop_size): New function.
1893 (extract_nps_bitop_size): New function.
1894 (arc_flag_operands): Add nps400 entries.
1895 (arc_flag_classes): Add nps400 entries.
1896 (arc_operands): Add nps400 entries.
1897 (arc_opcodes): Add nps400 include.
1899 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1901 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1902 the new class enum values.
1904 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1906 * arc-dis.c (print_insn_arc): Handle nps400.
1908 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1910 * arc-opc.c (BASE): Delete.
1912 2016-03-18 Nick Clifton <nickc@redhat.com>
1915 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1916 of MOV insn that aliases an ORR insn.
1918 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1920 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1922 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1924 * mcore-opc.h: Add const qualifiers.
1925 * microblaze-opc.h (struct op_code_struct): Likewise.
1926 * sh-opc.h: Likewise.
1927 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1928 (tic4x_print_op): Likewise.
1930 2016-03-02 Alan Modra <amodra@gmail.com>
1932 * or1k-desc.h: Regenerate.
1933 * fr30-ibld.c: Regenerate.
1934 * rl78-decode.c: Regenerate.
1936 2016-03-01 Nick Clifton <nickc@redhat.com>
1939 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1941 2016-02-24 Renlin Li <renlin.li@arm.com>
1943 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1944 (print_insn_coprocessor): Support fp16 instructions.
1946 2016-02-24 Renlin Li <renlin.li@arm.com>
1948 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1949 vminnm, vrint(mpna).
1951 2016-02-24 Renlin Li <renlin.li@arm.com>
1953 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1954 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1956 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1958 * i386-dis.c (print_insn): Parenthesize expression to prevent
1959 truncated addresses.
1962 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1963 Janek van Oirschot <jvanoirs@synopsys.com>
1965 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1968 2016-02-04 Nick Clifton <nickc@redhat.com>
1971 * msp430-dis.c (print_insn_msp430): Add a special case for
1972 decoding an RRC instruction with the ZC bit set in the extension
1975 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1977 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1978 * epiphany-ibld.c: Regenerate.
1979 * fr30-ibld.c: Regenerate.
1980 * frv-ibld.c: Regenerate.
1981 * ip2k-ibld.c: Regenerate.
1982 * iq2000-ibld.c: Regenerate.
1983 * lm32-ibld.c: Regenerate.
1984 * m32c-ibld.c: Regenerate.
1985 * m32r-ibld.c: Regenerate.
1986 * mep-ibld.c: Regenerate.
1987 * mt-ibld.c: Regenerate.
1988 * or1k-ibld.c: Regenerate.
1989 * xc16x-ibld.c: Regenerate.
1990 * xstormy16-ibld.c: Regenerate.
1992 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1994 * epiphany-dis.c: Regenerated from latest cpu files.
1996 2016-02-01 Michael McConville <mmcco@mykolab.com>
1998 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2001 2016-01-25 Renlin Li <renlin.li@arm.com>
2003 * arm-dis.c (mapping_symbol_for_insn): New function.
2004 (find_ifthen_state): Call mapping_symbol_for_insn().
2006 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
2008 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2009 of MSR UAO immediate operand.
2011 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2013 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2014 instruction support.
2016 2016-01-17 Alan Modra <amodra@gmail.com>
2018 * configure: Regenerate.
2020 2016-01-14 Nick Clifton <nickc@redhat.com>
2022 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2023 instructions that can support stack pointer operations.
2024 * rl78-decode.c: Regenerate.
2025 * rl78-dis.c: Fix display of stack pointer in MOVW based
2028 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2030 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2031 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2032 erxtatus_el1 and erxaddr_el1.
2034 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2036 * arm-dis.c (arm_opcodes): Add "esb".
2037 (thumb_opcodes): Likewise.
2039 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2041 * ppc-opc.c <xscmpnedp>: Delete.
2042 <xvcmpnedp>: Likewise.
2043 <xvcmpnedp.>: Likewise.
2044 <xvcmpnesp>: Likewise.
2045 <xvcmpnesp.>: Likewise.
2047 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2050 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2053 2016-01-01 Alan Modra <amodra@gmail.com>
2055 Update year range in copyright notice of all files.
2057 For older changes see ChangeLog-2015
2059 Copyright (C) 2016 Free Software Foundation, Inc.
2061 Copying and distribution of this file, with or without modification,
2062 are permitted in any medium without royalty provided the copyright
2063 notice and this notice are preserved.
2069 version-control: never
projects / deliverable / binutils-gdb.git / blob