opcodes/ChangeLog

   1 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
   2
   3         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
   4         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
   5         aarch64_feature_f64mm): New feature sets.
   6         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
   7         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
   8         instructions.
   9         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
  10         macros.
  11         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
  12         (OP_SVE_QQQ): New qualifier.
  13         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
  14         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
  15         the movprfx constraint.
  16         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
  17         (aarch64_opcode_table): Define new instructions smmla,
  18         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
  19         uzip{1/2}, trn{1/2}.
  20         * aarch64-opc.c (operand_general_constraint_met_p): Handle
  21         AARCH64_OPND_SVE_ADDR_RI_S4x32.
  22         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
  23         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
  24         Account for new instructions.
  25         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
  26         S4x32 operand.
  27         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
  28
  29 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  30 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  31
  32         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
  33         Armv8.6-A.
  34         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
  35         (neon_opcodes): Add bfloat SIMD instructions.
  36         (print_insn_coprocessor): Add new control character %b to print
  37         condition code without checking cp_num.
  38         (print_insn_neon): Account for BFloat16 instructions that have no
  39         special top-byte handling.
  40
  41 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  42 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  43
  44         * arm-dis.c (print_insn_coprocessor,
  45         print_insn_generic_coprocessor): Create wrapper functions around
  46         the implementation of the print_insn_coprocessor control codes.
  47         (print_insn_coprocessor_1): Original print_insn_coprocessor
  48         function that now takes which array to look at as an argument.
  49         (print_insn_arm): Use both print_insn_coprocessor and
  50         print_insn_generic_coprocessor.
  51         (print_insn_thumb32): As above.
  52
  53 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  54 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  55
  56         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
  57         in reglane special case.
  58         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
  59         aarch64_find_next_opcode): Account for new instructions.
  60         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
  61         in reglane special case.
  62         * aarch64-opc.c (struct operand_qualifier_data): Add data for
  63         new AARCH64_OPND_QLF_S_2H qualifier.
  64         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
  65         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
  66         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
  67         sets.
  68         (BFLOAT_SVE, BFLOAT): New feature set macros.
  69         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
  70         instructions.
  71         (aarch64_opcode_table): Define new instructions bfdot,
  72         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
  73         bfcvtn2, bfcvt.
  74
  75 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  76 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  77
  78         * aarch64-tbl.h (ARMV8_6): New macro.
  79
  80 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  81
  82         * i386-dis.c (prefix_table): Add mcommit.
  83         (rm_table): Add rdpru.
  84         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
  85         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
  86         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
  87         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
  88         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
  89         * i386-opc.tbl (mcommit, rdpru): New.
  90         * i386-init.h, i386-tbl.h: Re-generate.
  91
  92 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-dis.c (OP_Mwait): Drop local variable "names", use
  95         "names32" instead.
  96         (OP_Monitor): Drop local variable "op1_names", re-purpose
  97         "names" for it instead, and replace former "names" uses by
  98         "names32" ones.
  99
 100 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 101
 102         PR/gas 25167
 103         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 104         operand-less forms.
 105         * opcodes/i386-tbl.h: Re-generate.
 106
 107 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-dis.c (OP_Mwaitx): Delete.
 110         (prefix_table): Use OP_Mwait for mwaitx entry.
 111         (OP_Mwait): Also handle mwaitx.
 112
 113 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 116         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 117         (prefix_table): Add respective entries.
 118         (rm_table): Link to those entries.
 119
 120 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 123         (REG_0F1C_P_0_MOD_0): ... this.
 124         (REG_0F1E_MOD_3): Rename to ...
 125         (REG_0F1E_P_1_MOD_3): ... this.
 126         (RM_0F01_REG_5): Rename to ...
 127         (RM_0F01_REG_5_MOD_3): ... this.
 128         (RM_0F01_REG_7): Rename to ...
 129         (RM_0F01_REG_7_MOD_3): ... this.
 130         (RM_0F1E_MOD_3_REG_7): Rename to ...
 131         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 132         (RM_0FAE_REG_6): Rename to ...
 133         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 134         (RM_0FAE_REG_7): Rename to ...
 135         (RM_0FAE_REG_7_MOD_3): ... this.
 136         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 137         (PREFIX_0F01_REG_5_MOD_0): ... this.
 138         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 139         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 140         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 141         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 142         (PREFIX_0FAE_REG_0): Rename to ...
 143         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 144         (PREFIX_0FAE_REG_1): Rename to ...
 145         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 146         (PREFIX_0FAE_REG_2): Rename to ...
 147         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 148         (PREFIX_0FAE_REG_3): Rename to ...
 149         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 150         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 151         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 152         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 153         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 154         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 155         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 156         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 157         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 158         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 159         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 160         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 161         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 162         (PREFIX_0FAE_REG_7): Rename to ...
 163         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 164         (PREFIX_MOD_0_0FC3): Rename to ...
 165         (PREFIX_0FC3_MOD_0): ... this.
 166         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 167         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 168         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 169         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 170         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 171         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 172         (reg_table, prefix_table, mod_table, rm_table): Adjust
 173         accordingly.
 174
 175 2019-11-04  Nick Clifton  <nickc@redhat.com>
 176
 177         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 178         of a v850 system register.  Move the v850_sreg_names array into
 179         this function.
 180         (get_v850_reg_name): Likewise for ordinary register names.
 181         (get_v850_vreg_name): Likewise for vector register names.
 182         (get_v850_cc_name): Likewise for condition codes.
 183         * get_v850_float_cc_name): Likewise for floating point condition
 184         codes.
 185         (get_v850_cacheop_name): Likewise for cache-ops.
 186         (get_v850_prefop_name): Likewise for pref-ops.
 187         (disassemble): Use the new accessor functions.
 188
 189 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 190
 191         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 192         immediate for the writeback form of ldraa/ldrab if it is 0.
 193         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 194         * aarch64-opc-2.c: Regenerated.
 195
 196 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-gen.c (operand_type_shorthands): Delete.
 199         (operand_type_init): Expand previous shorthands.
 200         (set_bitfield_from_shorthand): Rename back to ...
 201         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 202         of operand_type_init[].
 203         (set_bitfield): Adjust call to the above function.
 204         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 205         RegXMM, RegYMM, RegZMM): Define.
 206         * i386-reg.tbl: Expand prior shorthands.
 207
 208 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 209
 210         * i386-gen.c (output_i386_opcode): Change order of fields
 211         emitted to output.
 212         * i386-opc.h (struct insn_template): Move operands field.
 213         Convert extension_opcode field to unsigned short.
 214         * i386-tbl.h: Re-generate.
 215
 216 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 219         of W.
 220         * i386-opc.h (W): Extend comment.
 221         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 222         general purpose variants not allowing for byte operands.
 223         * i386-tbl.h: Re-generate.
 224
 225 2019-10-29  Nick Clifton  <nickc@redhat.com>
 226
 227         * tic30-dis.c (print_branch): Correct size of operand array.
 228
 229 2019-10-29  Nick Clifton  <nickc@redhat.com>
 230
 231         * d30v-dis.c (print_insn): Check that operand index is valid
 232         before attempting to access the operands array.
 233
 234 2019-10-29  Nick Clifton  <nickc@redhat.com>
 235
 236         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 237         locating the bit to be tested.
 238
 239 2019-10-29  Nick Clifton  <nickc@redhat.com>
 240
 241         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 242         values.
 243         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 244         (print_insn_s12z):  Check for illegal size values.
 245
 246 2019-10-28  Nick Clifton  <nickc@redhat.com>
 247
 248         * csky-dis.c (csky_chars_to_number): Check for a negative
 249         count. Use an unsigned integer to construct the return value.
 250
 251 2019-10-28  Nick Clifton  <nickc@redhat.com>
 252
 253         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 254         operand buffer.  Set value to 15 not 13.
 255         (get_register_operand): Use OPERAND_BUFFER_LEN.
 256         (get_indirect_operand): Likewise.
 257         (print_two_operand): Likewise.
 258         (print_three_operand): Likewise.
 259         (print_oar_insn): Likewise.
 260
 261 2019-10-28  Nick Clifton  <nickc@redhat.com>
 262
 263         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 264         (bit_extract_simple): Likewise.
 265         (bit_copy): Likewise.
 266         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 267         index_offset array are not accessed.
 268
 269 2019-10-28  Nick Clifton  <nickc@redhat.com>
 270
 271         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 272         operand.
 273
 274 2019-10-25  Nick Clifton  <nickc@redhat.com>
 275
 276         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 277         access to opcodes.op array element.
 278
 279 2019-10-23  Nick Clifton  <nickc@redhat.com>
 280
 281         * rx-dis.c (get_register_name): Fix spelling typo in error
 282         message.
 283         (get_condition_name, get_flag_name, get_double_register_name)
 284         (get_double_register_high_name, get_double_register_low_name)
 285         (get_double_control_register_name, get_double_condition_name)
 286         (get_opsize_name, get_size_name): Likewise.
 287
 288 2019-10-22  Nick Clifton  <nickc@redhat.com>
 289
 290         * rx-dis.c (get_size_name): New function.  Provides safe
 291         access to name array.
 292         (get_opsize_name): Likewise.
 293         (print_insn_rx): Use the accessor functions.
 294
 295 2019-10-16  Nick Clifton  <nickc@redhat.com>
 296
 297         * rx-dis.c (get_register_name): New function.  Provides safe
 298         access to name array.
 299         (get_condition_name, get_flag_name, get_double_register_name)
 300         (get_double_register_high_name, get_double_register_low_name)
 301         (get_double_control_register_name, get_double_condition_name):
 302         Likewise.
 303         (print_insn_rx): Use the accessor functions.
 304
 305 2019-10-09  Nick Clifton  <nickc@redhat.com>
 306
 307         PR 25041
 308         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 309         instructions.
 310
 311 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 312
 313         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 314         (cmpsd): Likewise. Move EsSeg to other operand.
 315         * opcodes/i386-tbl.h: Re-generate.
 316
 317 2019-09-23  Alan Modra  <amodra@gmail.com>
 318
 319         * m68k-dis.c: Include cpu-m68k.h
 320
 321 2019-09-23  Alan Modra  <amodra@gmail.com>
 322
 323         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 324         "elf/mips.h" earlier.
 325
 326 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 327
 328         PR gas/25012
 329         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 330         with SReg operand.
 331         * i386-tbl.h: Re-generate.
 332
 333 2019-09-18  Alan Modra  <amodra@gmail.com>
 334
 335         * arc-ext.c: Update throughout for bfd section macro changes.
 336
 337 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 338
 339         * Makefile.in: Re-generate.
 340         * configure: Re-generate.
 341
 342 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 343
 344         * riscv-opc.c (riscv_opcodes): Change subset field
 345         to insn_class field for all instructions.
 346         (riscv_insn_types): Likewise.
 347
 348 2019-09-16  Phil Blundell  <pb@pbcl.net>
 349
 350         * configure: Regenerated.
 351
 352 2019-09-10  Miod Vallat  <miod@online.fr>
 353
 354         PR 24982
 355         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 356
 357 2019-09-09  Phil Blundell  <pb@pbcl.net>
 358
 359         binutils 2.33 branch created.
 360
 361 2019-09-03  Nick Clifton  <nickc@redhat.com>
 362
 363         PR 24961
 364         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 365         greater than zero before indexing via (bufcnt -1).
 366
 367 2019-09-03  Nick Clifton  <nickc@redhat.com>
 368
 369         PR 24958
 370         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 371         (MAX_SPEC_REG_NAME_LEN): Define.
 372         (struct mmix_dis_info): Use defined constants for array lengths.
 373         (get_reg_name): New function.
 374         (get_sprec_reg_name): New function.
 375         (print_insn_mmix): Use new functions.
 376
 377 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 378
 379         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 380         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 381         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 382
 383 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 384
 385         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 386         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 387         (aarch64_sys_reg_supported_p): Update checks for the above.
 388
 389 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 390
 391         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 392         cases MVE_SQRSHRL and MVE_UQRSHLL.
 393         (print_insn_mve): Add case for specifier 'k' to check
 394         specific bit of the instruction.
 395
 396 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 397
 398         PR 24854
 399         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 400         encountering an unknown machine type.
 401         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 402         cases return -1 rather than calling abort.
 403
 404 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 405
 406         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 407         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 408         IgnoreSize.
 409         * i386-tbl.h: Re-generate.
 410
 411 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 412
 413         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 414         instructions.
 415
 416 2019-07-30  Mel Chen <mel.chen@sifive.com>
 417
 418         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 419         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 420
 421         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 422         fscsr.
 423
 424 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 425
 426         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 427         and MPY class instructions.
 428         (parse_option): Add nps400 option.
 429         (print_arc_disassembler_options): Add nps400 info.
 430
 431 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 432
 433         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 434         (bspop): Likewise.
 435         (modapp): Likewise.
 436         * arc-opc.c (RAD_CHK): Add.
 437         * arc-tbl.h: Regenerate.
 438
 439 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 440
 441         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 442         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 443
 444 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 445
 446         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 447         instructions as UNPREDICTABLE.
 448
 449 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 450
 451         * bpf-desc.c: Regenerated.
 452
 453 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-gen.c (static_assert): Define.
 456         (main): Use it.
 457         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 458         (Opcode_Modifier_Num): ... this.
 459         (Mem): Delete.
 460
 461 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 462
 463         * i386-gen.c (operand_types): Move RegMem ...
 464         (opcode_modifiers): ... here.
 465         * i386-opc.h (RegMem): Move to opcode modifer enum.
 466         (union i386_operand_type): Move regmem field ...
 467         (struct i386_opcode_modifier): ... here.
 468         * i386-opc.tbl (RegMem): Define.
 469         (mov, movq): Move RegMem on segment, control, debug, and test
 470         register flavors.
 471         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 472         to non-SSE2AVX flavor.
 473         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 474         Move RegMem on register only flavors. Drop IgnoreSize from
 475         legacy encoding flavors.
 476         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 477         flavors.
 478         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 479         register only flavors.
 480         (vmovd): Move RegMem and drop IgnoreSize on register only
 481         flavor. Change opcode and operand order to store form.
 482         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 483
 484 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 485
 486         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 487         entries.
 488         * i386-opc.h (SReg2, SReg3): Replace by ...
 489         (SReg): ... this.
 490         (union i386_operand_type): Replace sreg fields.
 491         * i386-opc.tbl (mov, ): Use SReg.
 492         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 493         register flavors.
 494         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 495         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 496
 497 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 498
 499         * bpf-desc.c: Regenerate.
 500         * bpf-opc.c: Likewise.
 501         * bpf-opc.h: Likewise.
 502
 503 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 504
 505         * bpf-desc.c: Regenerate.
 506         * bpf-opc.c: Likewise.
 507
 508 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 509
 510         * arm-dis.c (print_insn_coprocessor): Rename index to
 511         index_operand.
 512
 513 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 514
 515         * riscv-opc.c (riscv_insn_types): Add r4 type.
 516
 517         * riscv-opc.c (riscv_insn_types): Add b and j type.
 518
 519         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 520         format for sb type and correct s type.
 521
 522 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 523
 524         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 525         SVE FMOV alias of FCPY.
 526
 527 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 528
 529         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 530         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 531
 532 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 533
 534         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 535         registers in an instruction prefixed by MOVPRFX.
 536
 537 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 538
 539         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 540         sve_size_13 icode to account for variant behaviour of
 541         pmull{t,b}.
 542         * aarch64-dis-2.c: Regenerate.
 543         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 544         sve_size_13 icode to account for variant behaviour of
 545         pmull{t,b}.
 546         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 547         (OP_SVE_VVV_Q_D): Add new qualifier.
 548         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 549         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 550         AES and those not.
 551
 552 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 553
 554         * opcodes/i386-gen.c (operand_type_init): Remove
 555         OPERAND_TYPE_VEC_IMM4 entry.
 556         (operand_types): Remove Vec_Imm4.
 557         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 558         (union i386_operand_type): Remove vec_imm4.
 559         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 560         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 561
 562 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 563
 564         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 565         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 566         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 567         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 568         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 569         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 570         * i386-tbl.h: Re-generate.
 571
 572 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 573
 574         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 575         register operands.
 576         * i386-tbl.h: Re-generate.
 577
 578 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-opc.tbl (C): New.
 581         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 582         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 583         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 584         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 585         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 586         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 587         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 588         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 589         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 590         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 591         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 592         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 593         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 594         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 595         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 596         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 597         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 598         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 599         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 600         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 601         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 602         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 603         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 604         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 605         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 606         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 607         flavors.
 608         * i386-tbl.h: Re-generate.
 609
 610 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 611
 612         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 613         register operands.
 614         * i386-tbl.h: Re-generate.
 615
 616 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 617
 618         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 619         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 620         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 621         * i386-tbl.h: Re-generate.
 622
 623 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 624
 625         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 626         Disp8MemShift from register only templates.
 627         * i386-tbl.h: Re-generate.
 628
 629 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 630
 631         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 632         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 633         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 634         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 635         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 636         EVEX_W_0F11_P_3_M_1): Delete.
 637         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 638         EVEX_W_0F11_P_3): New.
 639         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 640         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 641         MOD_EVEX_0F11_PREFIX_3 table entries.
 642         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 643         PREFIX_EVEX_0F11 table entries.
 644         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 645         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 646         EVEX_W_0F11_P_3_M_{0,1} table entries.
 647
 648 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 649
 650         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 651         Delete.
 652
 653 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 654
 655         PR binutils/24719
 656         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 657         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 658         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 659         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 660         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 661         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 662         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 663         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 664         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 665         PREFIX_EVEX_0F38C6_REG_6 entries.
 666         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 667         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 668         EVEX_W_0F38C7_R_6_P_2 entries.
 669         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 670         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 671         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 672         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 673         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 674         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 675         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 676
 677 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 678
 679         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 680         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 681         VEX_LEN_0F2D_P_3): Delete.
 682         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 683         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 684         (prefix_table): ... here.
 685
 686 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 687
 688         * i386-dis.c (Iq): Delete.
 689         (Id): New.
 690         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 691         TBM insns.
 692         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 693         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 694         (OP_E_memory): Also honor needindex when deciding whether an
 695         address size prefix needs printing.
 696         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 697
 698 2019-06-26  Jim Wilson  <jimw@sifive.com>
 699
 700         PR binutils/24739
 701         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 702         Set info->display_endian to info->endian_code.
 703
 704 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 705
 706         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 707         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 708         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 709         OPERAND_TYPE_ACC64 entries.
 710         * i386-init.h: Re-generate.
 711
 712 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 715         Delete.
 716         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 717         of dqa_mode.
 718         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 719         entries here.
 720         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 721         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 722
 723 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 724
 725         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 726         variables.
 727
 728 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 729
 730         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 731         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 732         movnti.
 733         * i386-opc.tbl (movnti): Add IgnoreSize.
 734         * i386-tbl.h: Re-generate.
 735
 736 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 737
 738         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 739         * i386-tbl.h: Re-generate.
 740
 741 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 742
 743         * i386-dis-evex.h: Break into ...
 744         * i386-dis-evex-len.h: New file.
 745         * i386-dis-evex-mod.h: Likewise.
 746         * i386-dis-evex-prefix.h: Likewise.
 747         * i386-dis-evex-reg.h: Likewise.
 748         * i386-dis-evex-w.h: Likewise.
 749         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 750         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 751         i386-dis-evex-mod.h.
 752
 753 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 754
 755         PR binutils/24700
 756         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 757         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 758         EVEX_W_0F385B_P_2.
 759         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 760         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 761         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 762         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 763         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 764         EVEX_LEN_0F385B_P_2_W_1.
 765         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 766         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 767         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 768         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 769         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 770         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 771         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 772         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 773         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 774         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 775
 776 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 777
 778         PR binutils/24691
 779         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 780         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 781         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 782         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 783         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 784         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 785         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 786         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 787         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 788         EVEX_LEN_0F3A43_P_2_W_1.
 789         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 790         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 791         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 792         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 793         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 794         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 795         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 796         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 797         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 798         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 799         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 800         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 801
 802 2019-06-14  Nick Clifton  <nickc@redhat.com>
 803
 804         * po/fr.po; Updated French translation.
 805
 806 2019-06-13  Stafford Horne  <shorne@gmail.com>
 807
 808         * or1k-asm.c: Regenerated.
 809         * or1k-desc.c: Regenerated.
 810         * or1k-desc.h: Regenerated.
 811         * or1k-dis.c: Regenerated.
 812         * or1k-ibld.c: Regenerated.
 813         * or1k-opc.c: Regenerated.
 814         * or1k-opc.h: Regenerated.
 815         * or1k-opinst.c: Regenerated.
 816
 817 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 818
 819         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 820
 821 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 822
 823         PR binutils/24633
 824         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 825         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 826         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 827         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 828         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 829         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 830         EVEX_LEN_0F3A1B_P_2_W_1.
 831         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 832         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 833         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 834         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 835         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 836         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 837         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 838         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 839
 840 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 841
 842         PR binutils/24626
 843         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 844         EVEX.vvvv when disassembling VEX and EVEX instructions.
 845         (OP_VEX): Set vex.register_specifier to 0 after readding
 846         vex.register_specifier.
 847         (OP_Vex_2src_1): Likewise.
 848         (OP_Vex_2src_2): Likewise.
 849         (OP_LWP_E): Likewise.
 850         (OP_EX_Vex): Don't check vex.register_specifier.
 851         (OP_XMM_Vex): Likewise.
 852
 853 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 854             Lili Cui  <lili.cui@intel.com>
 855
 856         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 857         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 858         instructions.
 859         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 860         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 861         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 862         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 863         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 864         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 865         * i386-init.h: Regenerated.
 866         * i386-tbl.h: Likewise.
 867
 868 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 869             Lili Cui  <lili.cui@intel.com>
 870
 871         * doc/c-i386.texi: Document enqcmd.
 872         * testsuite/gas/i386/enqcmd-intel.d: New file.
 873         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 874         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 875         * testsuite/gas/i386/enqcmd.d: Likewise.
 876         * testsuite/gas/i386/enqcmd.s: Likewise.
 877         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 878         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 879         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 880         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 881         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 882         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 883         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 884         and x86-64-enqcmd.
 885
 886 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 887
 888         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 889
 890 2019-06-03  Alan Modra  <amodra@gmail.com>
 891
 892         * ppc-dis.c (prefix_opcd_indices): Correct size.
 893
 894 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 895
 896         PR gas/24625
 897         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 898         Disp8ShiftVL.
 899         * i386-tbl.h: Regenerated.
 900
 901 2019-05-24  Alan Modra  <amodra@gmail.com>
 902
 903         * po/POTFILES.in: Regenerate.
 904
 905 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 906             Alan Modra  <amodra@gmail.com>
 907
 908         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 909         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 910         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 911         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 912         XTOP>): Define and add entries.
 913         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 914         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 915         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 916         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 917
 918 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 919             Alan Modra  <amodra@gmail.com>
 920
 921         * ppc-dis.c (ppc_opts): Add "future" entry.
 922         (PREFIX_OPCD_SEGS): Define.
 923         (prefix_opcd_indices): New array.
 924         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 925         (lookup_prefix): New function.
 926         (print_insn_powerpc): Handle 64-bit prefix instructions.
 927         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 928         (PMRR, POWERXX): Define.
 929         (prefix_opcodes): New instruction table.
 930         (prefix_num_opcodes): New constant.
 931
 932 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 933
 934         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 935         * configure: Regenerated.
 936         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 937         and cpu/bpf.opc.
 938         (HFILES): Add bpf-desc.h and bpf-opc.h.
 939         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 940         bpf-ibld.c and bpf-opc.c.
 941         (BPF_DEPS): Define.
 942         * Makefile.in: Regenerated.
 943         * disassemble.c (ARCH_bpf): Define.
 944         (disassembler): Add case for bfd_arch_bpf.
 945         (disassemble_init_for_target): Likewise.
 946         (enum epbf_isa_attr): Define.
 947         * disassemble.h: extern print_insn_bpf.
 948         * bpf-asm.c: Generated.
 949         * bpf-opc.h: Likewise.
 950         * bpf-opc.c: Likewise.
 951         * bpf-ibld.c: Likewise.
 952         * bpf-dis.c: Likewise.
 953         * bpf-desc.h: Likewise.
 954         * bpf-desc.c: Likewise.
 955
 956 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 957
 958         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 959         and VMSR with the new operands.
 960
 961 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 962
 963         * arm-dis.c (enum mve_instructions): New enum
 964         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 965         and cneg.
 966         (mve_opcodes): New instructions as above.
 967         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 968         csneg and csel.
 969         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 970
 971 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 972
 973         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 974         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 975         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 976         uqshl, urshrl and urshr.
 977         (is_mve_okay_in_it): Add new instructions to TRUE list.
 978         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 979         (print_insn_mve): Updated to accept new %j,
 980         %<bitfield>m and %<bitfield>n patterns.
 981
 982 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 983
 984         * mips-opc.c (mips_builtin_opcodes): Change source register
 985         constraint for DAUI.
 986
 987 2019-05-20  Nick Clifton  <nickc@redhat.com>
 988
 989         * po/fr.po: Updated French translation.
 990
 991 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 992             Michael Collison <michael.collison@arm.com>
 993
 994         * arm-dis.c (thumb32_opcodes): Add new instructions.
 995         (enum mve_instructions): Likewise.
 996         (enum mve_undefined): Add new reasons.
 997         (is_mve_encoding_conflict): Handle new instructions.
 998         (is_mve_undefined): Likewise.
 999         (is_mve_unpredictable): Likewise.
1000         (print_mve_undefined): Likewise.
1001         (print_mve_size): Likewise.
1002
1003 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1004             Michael Collison <michael.collison@arm.com>
1005
1006         * arm-dis.c (thumb32_opcodes): Add new instructions.
1007         (enum mve_instructions): Likewise.
1008         (is_mve_encoding_conflict): Handle new instructions.
1009         (is_mve_undefined): Likewise.
1010         (is_mve_unpredictable): Likewise.
1011         (print_mve_size): Likewise.
1012
1013 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1014             Michael Collison <michael.collison@arm.com>
1015
1016         * arm-dis.c (thumb32_opcodes): Add new instructions.
1017         (enum mve_instructions): Likewise.
1018         (is_mve_encoding_conflict): Likewise.
1019         (is_mve_unpredictable): Likewise.
1020         (print_mve_size): Likewise.
1021
1022 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1023             Michael Collison <michael.collison@arm.com>
1024
1025         * arm-dis.c (thumb32_opcodes): Add new instructions.
1026         (enum mve_instructions): Likewise.
1027         (is_mve_encoding_conflict): Handle new instructions.
1028         (is_mve_undefined): Likewise.
1029         (is_mve_unpredictable): Likewise.
1030         (print_mve_size): Likewise.
1031
1032 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1033             Michael Collison <michael.collison@arm.com>
1034
1035         * arm-dis.c (thumb32_opcodes): Add new instructions.
1036         (enum mve_instructions): Likewise.
1037         (is_mve_encoding_conflict): Handle new instructions.
1038         (is_mve_undefined): Likewise.
1039         (is_mve_unpredictable): Likewise.
1040         (print_mve_size): Likewise.
1041         (print_insn_mve): Likewise.
1042
1043 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1044             Michael Collison <michael.collison@arm.com>
1045
1046         * arm-dis.c (thumb32_opcodes): Add new instructions.
1047         (print_insn_thumb32): Handle new instructions.
1048
1049 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1050             Michael Collison <michael.collison@arm.com>
1051
1052         * arm-dis.c (enum mve_instructions): Add new instructions.
1053         (enum mve_undefined): Add new reasons.
1054         (is_mve_encoding_conflict): Handle new instructions.
1055         (is_mve_undefined): Likewise.
1056         (is_mve_unpredictable): Likewise.
1057         (print_mve_undefined): Likewise.
1058         (print_mve_size): Likewise.
1059         (print_mve_shift_n): Likewise.
1060         (print_insn_mve): Likewise.
1061
1062 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1063             Michael Collison <michael.collison@arm.com>
1064
1065         * arm-dis.c (enum mve_instructions): Add new instructions.
1066         (is_mve_encoding_conflict): Handle new instructions.
1067         (is_mve_unpredictable): Likewise.
1068         (print_mve_rotate): Likewise.
1069         (print_mve_size): Likewise.
1070         (print_insn_mve): Likewise.
1071
1072 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1073             Michael Collison <michael.collison@arm.com>
1074
1075         * arm-dis.c (enum mve_instructions): Add new instructions.
1076         (is_mve_encoding_conflict): Handle new instructions.
1077         (is_mve_unpredictable): Likewise.
1078         (print_mve_size): Likewise.
1079         (print_insn_mve): Likewise.
1080
1081 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1082             Michael Collison <michael.collison@arm.com>
1083
1084         * arm-dis.c (enum mve_instructions): Add new instructions.
1085         (enum mve_undefined): Add new reasons.
1086         (is_mve_encoding_conflict): Handle new instructions.
1087         (is_mve_undefined): Likewise.
1088         (is_mve_unpredictable): Likewise.
1089         (print_mve_undefined): Likewise.
1090         (print_mve_size): Likewise.
1091         (print_insn_mve): Likewise.
1092
1093 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1094             Michael Collison <michael.collison@arm.com>
1095
1096         * arm-dis.c (enum mve_instructions): Add new instructions.
1097         (is_mve_encoding_conflict): Handle new instructions.
1098         (is_mve_undefined): Likewise.
1099         (is_mve_unpredictable): Likewise.
1100         (print_mve_size): Likewise.
1101         (print_insn_mve): Likewise.
1102
1103 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1104             Michael Collison <michael.collison@arm.com>
1105
1106         * arm-dis.c (enum mve_instructions): Add new instructions.
1107         (enum mve_unpredictable): Add new reasons.
1108         (enum mve_undefined): Likewise.
1109         (is_mve_okay_in_it): Handle new isntructions.
1110         (is_mve_encoding_conflict): Likewise.
1111         (is_mve_undefined): Likewise.
1112         (is_mve_unpredictable): Likewise.
1113         (print_mve_vmov_index): Likewise.
1114         (print_simd_imm8): Likewise.
1115         (print_mve_undefined): Likewise.
1116         (print_mve_unpredictable): Likewise.
1117         (print_mve_size): Likewise.
1118         (print_insn_mve): Likewise.
1119
1120 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1121             Michael Collison <michael.collison@arm.com>
1122
1123         * arm-dis.c (enum mve_instructions): Add new instructions.
1124         (enum mve_unpredictable): Add new reasons.
1125         (enum mve_undefined): Likewise.
1126         (is_mve_encoding_conflict): Handle new instructions.
1127         (is_mve_undefined): Likewise.
1128         (is_mve_unpredictable): Likewise.
1129         (print_mve_undefined): Likewise.
1130         (print_mve_unpredictable): Likewise.
1131         (print_mve_rounding_mode): Likewise.
1132         (print_mve_vcvt_size): Likewise.
1133         (print_mve_size): Likewise.
1134         (print_insn_mve): Likewise.
1135
1136 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1137             Michael Collison <michael.collison@arm.com>
1138
1139         * arm-dis.c (enum mve_instructions): Add new instructions.
1140         (enum mve_unpredictable): Add new reasons.
1141         (enum mve_undefined): Likewise.
1142         (is_mve_undefined): Handle new instructions.
1143         (is_mve_unpredictable): Likewise.
1144         (print_mve_undefined): Likewise.
1145         (print_mve_unpredictable): Likewise.
1146         (print_mve_size): Likewise.
1147         (print_insn_mve): Likewise.
1148
1149 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1150             Michael Collison <michael.collison@arm.com>
1151
1152         * arm-dis.c (enum mve_instructions): Add new instructions.
1153         (enum mve_undefined): Add new reasons.
1154         (insns): Add new instructions.
1155         (is_mve_encoding_conflict):
1156         (print_mve_vld_str_addr): New print function.
1157         (is_mve_undefined): Handle new instructions.
1158         (is_mve_unpredictable): Likewise.
1159         (print_mve_undefined): Likewise.
1160         (print_mve_size): Likewise.
1161         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1162         (print_insn_mve):  Handle new operands.
1163
1164 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1165             Michael Collison <michael.collison@arm.com>
1166
1167         * arm-dis.c (enum mve_instructions): Add new instructions.
1168         (enum mve_unpredictable): Add new reasons.
1169         (is_mve_encoding_conflict): Handle new instructions.
1170         (is_mve_unpredictable): Likewise.
1171         (mve_opcodes): Add new instructions.
1172         (print_mve_unpredictable): Handle new reasons.
1173         (print_mve_register_blocks): New print function.
1174         (print_mve_size): Handle new instructions.
1175         (print_insn_mve): Likewise.
1176
1177 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1178             Michael Collison <michael.collison@arm.com>
1179
1180         * arm-dis.c (enum mve_instructions): Add new instructions.
1181         (enum mve_unpredictable): Add new reasons.
1182         (enum mve_undefined): Likewise.
1183         (is_mve_encoding_conflict): Handle new instructions.
1184         (is_mve_undefined): Likewise.
1185         (is_mve_unpredictable): Likewise.
1186         (coprocessor_opcodes): Move NEON VDUP from here...
1187         (neon_opcodes): ... to here.
1188         (mve_opcodes): Add new instructions.
1189         (print_mve_undefined):  Handle new reasons.
1190         (print_mve_unpredictable): Likewise.
1191         (print_mve_size): Handle new instructions.
1192         (print_insn_neon): Handle vdup.
1193         (print_insn_mve): Handle new operands.
1194
1195 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1196             Michael Collison <michael.collison@arm.com>
1197
1198         * arm-dis.c (enum mve_instructions): Add new instructions.
1199         (enum mve_unpredictable): Add new values.
1200         (mve_opcodes): Add new instructions.
1201         (vec_condnames): New array with vector conditions.
1202         (mve_predicatenames): New array with predicate suffixes.
1203         (mve_vec_sizename): New array with vector sizes.
1204         (enum vpt_pred_state): New enum with vector predication states.
1205         (struct vpt_block): New struct type for vpt blocks.
1206         (vpt_block_state): Global struct to keep track of state.
1207         (mve_extract_pred_mask): New helper function.
1208         (num_instructions_vpt_block): Likewise.
1209         (mark_outside_vpt_block): Likewise.
1210         (mark_inside_vpt_block): Likewise.
1211         (invert_next_predicate_state): Likewise.
1212         (update_next_predicate_state): Likewise.
1213         (update_vpt_block_state): Likewise.
1214         (is_vpt_instruction): Likewise.
1215         (is_mve_encoding_conflict): Add entries for new instructions.
1216         (is_mve_unpredictable): Likewise.
1217         (print_mve_unpredictable): Handle new cases.
1218         (print_instruction_predicate): Likewise.
1219         (print_mve_size): New function.
1220         (print_vec_condition): New function.
1221         (print_insn_mve): Handle vpt blocks and new print operands.
1222
1223 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1224
1225         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1226         8, 14 and 15 for Armv8.1-M Mainline.
1227
1228 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1229             Michael Collison <michael.collison@arm.com>
1230
1231         * arm-dis.c (enum mve_instructions): New enum.
1232         (enum mve_unpredictable): Likewise.
1233         (enum mve_undefined): Likewise.
1234         (struct mopcode32): New struct.
1235         (is_mve_okay_in_it): New function.
1236         (is_mve_architecture): Likewise.
1237         (arm_decode_field): Likewise.
1238         (arm_decode_field_multiple): Likewise.
1239         (is_mve_encoding_conflict): Likewise.
1240         (is_mve_undefined): Likewise.
1241         (is_mve_unpredictable): Likewise.
1242         (print_mve_undefined): Likewise.
1243         (print_mve_unpredictable): Likewise.
1244         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1245         (print_insn_mve): New function.
1246         (print_insn_thumb32): Handle MVE architecture.
1247         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1248
1249 2019-05-10  Nick Clifton  <nickc@redhat.com>
1250
1251         PR 24538
1252         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1253         end of the table prematurely.
1254
1255 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1256
1257         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1258         macros for R6.
1259
1260 2019-05-11  Alan Modra  <amodra@gmail.com>
1261
1262         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1263         when -Mraw is in effect.
1264
1265 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1266
1267         * aarch64-dis-2.c: Regenerate.
1268         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1269         (OP_SVE_BBB): New variant set.
1270         (OP_SVE_DDDD): New variant set.
1271         (OP_SVE_HHH): New variant set.
1272         (OP_SVE_HHHU): New variant set.
1273         (OP_SVE_SSS): New variant set.
1274         (OP_SVE_SSSU): New variant set.
1275         (OP_SVE_SHH): New variant set.
1276         (OP_SVE_SBBU): New variant set.
1277         (OP_SVE_DSS): New variant set.
1278         (OP_SVE_DHHU): New variant set.
1279         (OP_SVE_VMV_HSD_BHS): New variant set.
1280         (OP_SVE_VVU_HSD_BHS): New variant set.
1281         (OP_SVE_VVVU_SD_BH): New variant set.
1282         (OP_SVE_VVVU_BHSD): New variant set.
1283         (OP_SVE_VVV_QHD_DBS): New variant set.
1284         (OP_SVE_VVV_HSD_BHS): New variant set.
1285         (OP_SVE_VVV_HSD_BHS2): New variant set.
1286         (OP_SVE_VVV_BHS_HSD): New variant set.
1287         (OP_SVE_VV_BHS_HSD): New variant set.
1288         (OP_SVE_VVV_SD): New variant set.
1289         (OP_SVE_VVU_BHS_HSD): New variant set.
1290         (OP_SVE_VZVV_SD): New variant set.
1291         (OP_SVE_VZVV_BH): New variant set.
1292         (OP_SVE_VZV_SD): New variant set.
1293         (aarch64_opcode_table): Add sve2 instructions.
1294
1295 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1296
1297         * aarch64-asm-2.c: Regenerated.
1298         * aarch64-dis-2.c: Regenerated.
1299         * aarch64-opc-2.c: Regenerated.
1300         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1301         for SVE_SHLIMM_UNPRED_22.
1302         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1303         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1304         operand.
1305
1306 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1307
1308         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1309         sve_size_tsz_bhs iclass encode.
1310         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1311         sve_size_tsz_bhs iclass decode.
1312
1313 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1314
1315         * aarch64-asm-2.c: Regenerated.
1316         * aarch64-dis-2.c: Regenerated.
1317         * aarch64-opc-2.c: Regenerated.
1318         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1319         for SVE_Zm4_11_INDEX.
1320         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1321         (fields): Handle SVE_i2h field.
1322         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1323         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1324
1325 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1326
1327         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1328         sve_shift_tsz_bhsd iclass encode.
1329         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1330         sve_shift_tsz_bhsd iclass decode.
1331
1332 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1333
1334         * aarch64-asm-2.c: Regenerated.
1335         * aarch64-dis-2.c: Regenerated.
1336         * aarch64-opc-2.c: Regenerated.
1337         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1338         (aarch64_encode_variant_using_iclass): Handle
1339         sve_shift_tsz_hsd iclass encode.
1340         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1341         sve_shift_tsz_hsd iclass decode.
1342         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1343         for SVE_SHRIMM_UNPRED_22.
1344         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1345         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1346         operand.
1347
1348 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1349
1350         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1351         sve_size_013 iclass encode.
1352         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1353         sve_size_013 iclass decode.
1354
1355 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1356
1357         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1358         sve_size_bh iclass encode.
1359         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1360         sve_size_bh iclass decode.
1361
1362 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1363
1364         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1365         sve_size_sd2 iclass encode.
1366         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1367         sve_size_sd2 iclass decode.
1368         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1369         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1370
1371 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1372
1373         * aarch64-asm-2.c: Regenerated.
1374         * aarch64-dis-2.c: Regenerated.
1375         * aarch64-opc-2.c: Regenerated.
1376         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1377         for SVE_ADDR_ZX.
1378         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1379         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1380
1381 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1382
1383         * aarch64-asm-2.c: Regenerated.
1384         * aarch64-dis-2.c: Regenerated.
1385         * aarch64-opc-2.c: Regenerated.
1386         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1387         for SVE_Zm3_11_INDEX.
1388         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1389         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1390         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1391         fields.
1392         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1393
1394 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1395
1396         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1397         sve_size_hsd2 iclass encode.
1398         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1399         sve_size_hsd2 iclass decode.
1400         * aarch64-opc.c (fields): Handle SVE_size field.
1401         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1402
1403 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1404
1405         * aarch64-asm-2.c: Regenerated.
1406         * aarch64-dis-2.c: Regenerated.
1407         * aarch64-opc-2.c: Regenerated.
1408         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1409         for SVE_IMM_ROT3.
1410         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1411         (fields): Handle SVE_rot3 field.
1412         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1413         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1414
1415 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1416
1417         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1418         instructions.
1419
1420 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1421
1422         * aarch64-tbl.h
1423         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1424         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1425         aarch64_feature_sve2bitperm): New feature sets.
1426         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1427         for feature set addresses.
1428         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1429         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1430
1431 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1432             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1433
1434         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1435         argument and set ASE_EVA_R6 appropriately.
1436         (set_default_mips_dis_options): Pass ISA to above.
1437         (parse_mips_dis_option): Likewise.
1438         * mips-opc.c (EVAR6): New macro.
1439         (mips_builtin_opcodes): Add llwpe, scwpe.
1440
1441 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1442
1443         * aarch64-asm-2.c: Regenerated.
1444         * aarch64-dis-2.c: Regenerated.
1445         * aarch64-opc-2.c: Regenerated.
1446         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1447         AARCH64_OPND_TME_UIMM16.
1448         (aarch64_print_operand): Likewise.
1449         * aarch64-tbl.h (QL_IMM_NIL): New.
1450         (TME): New.
1451         (_TME_INSN): New.
1452         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1453
1454 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1455
1456         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1457
1458 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1459             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1460
1461         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1462
1463 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1464
1465         * s12z-opc.h: Add extern "C" bracketing to help
1466         users who wish to use this interface in c++ code.
1467
1468 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1469
1470         * s12z-opc.c (bm_decode): Handle bit map operations with the
1471         "reserved0" mode.
1472
1473 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1474
1475         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1476         specifier.  Add entries for VLDR and VSTR of system registers.
1477         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1478         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1479         of %J and %K format specifier.
1480
1481 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1482
1483         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1484         Add new entries for VSCCLRM instruction.
1485         (print_insn_coprocessor): Handle new %C format control code.
1486
1487 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1488
1489         * arm-dis.c (enum isa): New enum.
1490         (struct sopcode32): New structure.
1491         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1492         set isa field of all current entries to ANY.
1493         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1494         Only match an entry if its isa field allows the current mode.
1495
1496 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1497
1498         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1499         CLRM.
1500         (print_insn_thumb32): Add logic to print %n CLRM register list.
1501
1502 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1503
1504         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1505         and %Q patterns.
1506
1507 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1508
1509         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1510         (print_insn_thumb32): Edit the switch case for %Z.
1511
1512 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1513
1514         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1515
1516 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1517
1518         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1519
1520 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1521
1522         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1523
1524 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1525
1526         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1527         Arm register with r13 and r15 unpredictable.
1528         (thumb32_opcodes): New instructions for bfx and bflx.
1529
1530 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1531
1532         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1533
1534 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1535
1536         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1537
1538 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1539
1540         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1541
1542 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1543
1544         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1545
1546 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1547
1548         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1549         "optr". ("operator" is a reserved word in c++).
1550
1551 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1552
1553         * aarch64-opc.c (aarch64_print_operand): Add case for
1554         AARCH64_OPND_Rt_SP.
1555         (verify_constraints): Likewise.
1556         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1557         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1558         to accept Rt|SP as first operand.
1559         (AARCH64_OPERANDS): Add new Rt_SP.
1560         * aarch64-asm-2.c: Regenerated.
1561         * aarch64-dis-2.c: Regenerated.
1562         * aarch64-opc-2.c: Regenerated.
1563
1564 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1565
1566         * aarch64-asm-2.c: Regenerated.
1567         * aarch64-dis-2.c: Likewise.
1568         * aarch64-opc-2.c: Likewise.
1569         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1570
1571 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1572
1573         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1574
1575 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1576
1577         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1578         * i386-init.h: Regenerated.
1579
1580 2019-04-07  Alan Modra  <amodra@gmail.com>
1581
1582         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1583         op_separator to control printing of spaces, comma and parens
1584         rather than need_comma, need_paren and spaces vars.
1585
1586 2019-04-07  Alan Modra  <amodra@gmail.com>
1587
1588         PR 24421
1589         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1590         (print_insn_neon, print_insn_arm): Likewise.
1591
1592 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1593
1594         * i386-dis-evex.h (evex_table): Updated to support BF16
1595         instructions.
1596         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1597         and EVEX_W_0F3872_P_3.
1598         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1599         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1600         * i386-opc.h (enum): Add CpuAVX512_BF16.
1601         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1602         * i386-opc.tbl: Add AVX512 BF16 instructions.
1603         * i386-init.h: Regenerated.
1604         * i386-tbl.h: Likewise.
1605
1606 2019-04-05  Alan Modra  <amodra@gmail.com>
1607
1608         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1609         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1610         to favour printing of "-" branch hint when using the "y" bit.
1611         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1612
1613 2019-04-05  Alan Modra  <amodra@gmail.com>
1614
1615         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1616         opcode until first operand is output.
1617
1618 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1619
1620         PR gas/24349
1621         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1622         (valid_bo_post_v2): Add support for 'at' branch hints.
1623         (insert_bo): Only error on branch on ctr.
1624         (get_bo_hint_mask): New function.
1625         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1626         for inserting 'at' branch hints.
1627         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1628         for extracting 'at' branch hints.
1629         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1630         (BOE): Delete operand.
1631         (BOM, BOP): New operands.
1632         (RM): Update value.
1633         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1634         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1635         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1636         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1637         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1638         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1639         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1640         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1641         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1642         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1643         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1644         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1645         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1646         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1647         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1648         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1649         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1650         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1651         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1652         bttarl+>: New extended mnemonics.
1653
1654 2019-03-28  Alan Modra  <amodra@gmail.com>
1655
1656         PR 24390
1657         * ppc-opc.c (BTF): Define.
1658         (powerpc_opcodes): Use for mtfsb*.
1659         * ppc-dis.c (print_insn_powerpc): Print fields with both
1660         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1661
1662 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1663
1664         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1665         (mapping_symbol_for_insn): Implement new algorithm.
1666         (print_insn): Remove duplicate code.
1667
1668 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1669
1670         * aarch64-dis.c (print_insn_aarch64):
1671         Implement override.
1672
1673 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1674
1675         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1676         order.
1677
1678 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1679
1680         * aarch64-dis.c (last_stop_offset): New.
1681         (print_insn_aarch64): Use stop_offset.
1682
1683 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1684
1685         PR gas/24359
1686         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1687         CPU_ANY_AVX2_FLAGS.
1688         * i386-init.h: Regenerated.
1689
1690 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1691
1692         PR gas/24348
1693         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1694         vmovdqu16, vmovdqu32 and vmovdqu64.
1695         * i386-tbl.h: Regenerated.
1696
1697 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1698
1699         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1700         from vstrszb, vstrszh, and vstrszf.
1701
1702 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1703
1704         * s390-opc.txt: Add instruction descriptions.
1705
1706 2019-02-08  Jim Wilson  <jimw@sifive.com>
1707
1708         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1709         <bne>: Likewise.
1710
1711 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1712
1713         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1714
1715 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1716
1717         PR binutils/23212
1718         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1719         * aarch64-opc.c (verify_elem_sd): New.
1720         (fields): Add FLD_sz entr.
1721         * aarch64-tbl.h (_SIMD_INSN): New.
1722         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1723         fmulx scalar and vector by element isns.
1724
1725 2019-02-07  Nick Clifton  <nickc@redhat.com>
1726
1727         * po/sv.po: Updated Swedish translation.
1728
1729 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1730
1731         * s390-mkopc.c (main): Accept arch13 as cpu string.
1732         * s390-opc.c: Add new instruction formats and instruction opcode
1733         masks.
1734         * s390-opc.txt: Add new arch13 instructions.
1735
1736 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1737
1738         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1739         (aarch64_opcode): Change encoding for stg, stzg
1740         st2g and st2zg.
1741         * aarch64-asm-2.c: Regenerated.
1742         * aarch64-dis-2.c: Regenerated.
1743         * aarch64-opc-2.c: Regenerated.
1744
1745 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1746
1747         * aarch64-asm-2.c: Regenerated.
1748         * aarch64-dis-2.c: Likewise.
1749         * aarch64-opc-2.c: Likewise.
1750         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1751
1752 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1753             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1754
1755         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1756         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1757         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1758         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1759         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1760         case for ldstgv_indexed.
1761         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1762         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1763         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1764         * aarch64-asm-2.c: Regenerated.
1765         * aarch64-dis-2.c: Regenerated.
1766         * aarch64-opc-2.c: Regenerated.
1767
1768 2019-01-23  Nick Clifton  <nickc@redhat.com>
1769
1770         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1771
1772 2019-01-21  Nick Clifton  <nickc@redhat.com>
1773
1774         * po/de.po: Updated German translation.
1775         * po/uk.po: Updated Ukranian translation.
1776
1777 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1778         * mips-dis.c (mips_arch_choices): Fix typo in
1779         gs464, gs464e and gs264e descriptors.
1780
1781 2019-01-19  Nick Clifton  <nickc@redhat.com>
1782
1783         * configure: Regenerate.
1784         * po/opcodes.pot: Regenerate.
1785
1786 2018-06-24  Nick Clifton  <nickc@redhat.com>
1787
1788         2.32 branch created.
1789
1790 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1791
1792         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1793         if it is null.
1794         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1795         zero.
1796
1797 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1798
1799         * configure: Regenerate.
1800
1801 2019-01-07  Alan Modra  <amodra@gmail.com>
1802
1803         * configure: Regenerate.
1804         * po/POTFILES.in: Regenerate.
1805
1806 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1807
1808         * s12z-opc.c: New file.
1809         * s12z-opc.h: New file.
1810         * s12z-dis.c: Removed all code not directly related to display
1811         of instructions.  Used the interface provided by the new files
1812         instead.
1813         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1814         * Makefile.in: Regenerate.
1815         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1816         * configure: Regenerate.
1817
1818 2019-01-01  Alan Modra  <amodra@gmail.com>
1819
1820         Update year range in copyright notice of all files.
1821
1822 For older changes see ChangeLog-2018
1823 \f
1824 Copyright (C) 2019 Free Software Foundation, Inc.
1825
1826 Copying and distribution of this file, with or without modification,
1827 are permitted in any medium without royalty provided the copyright
1828 notice and this notice are preserved.
1829
1830 Local Variables:
1831 mode: change-log
1832 left-margin: 8
1833 fill-column: 74
1834 version-control: never
1835 End: