1 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
3 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
4 adjustment for PC-relative operations following MIPS16e compact
5 jumps or undefined RR/J(AL)R(C) encodings.
7 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
9 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
10 variable to `reglane_index'.
12 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
14 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
16 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
18 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
20 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
22 * mips16-opc.c (mips16_opcodes): Update comment naming structure
25 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
27 * mips-dis.c (print_mips_disassembler_options): Reformat output.
29 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
31 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
32 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
34 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
36 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
38 2016-12-01 Nick Clifton <nickc@redhat.com>
41 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
44 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
46 * arc-opc.c (insert_ra_chk): New function.
47 (insert_rb_chk): Likewise.
48 (insert_rad): Update text error message.
49 (insert_rcd): Likewise.
50 (insert_rhv2): Likewise.
51 (insert_r0): Likewise.
52 (insert_r1): Likewise.
53 (insert_r2): Likewise.
54 (insert_r3): Likewise.
55 (insert_sp): Likewise.
56 (insert_gp): Likewise.
57 (insert_pcl): Likewise.
58 (insert_blink): Likewise.
59 (insert_ilink1): Likewise.
60 (insert_ilink2): Likewise.
61 (insert_ras): Likewise.
62 (insert_rbs): Likewise.
63 (insert_rcs): Likewise.
64 (insert_simm3s): Likewise.
65 (insert_rrange): Likewise.
66 (insert_fpel): Likewise.
67 (insert_blinkel): Likewise.
68 (insert_pcel): Likewise.
69 (insert_nps_3bit_dst): Likewise.
70 (insert_nps_3bit_dst_short): Likewise.
71 (insert_nps_3bit_src2_short): Likewise.
72 (insert_nps_bitop_size_2b): Likewise.
73 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
78 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
79 * arc-tbl.h (div, divu): All instructions are DIVREM class.
80 Change first insn argument to check for LP_COUNT usage.
82 (ld, ldd): All instructions are LOAD class. Change first insn
83 argument to check for LP_COUNT usage.
84 (st, std): All instructions are STORE class.
85 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
86 Change first insn argument to check for LP_COUNT usage.
87 (mov): All instructions are MOVE class. Change first insn
88 argument to check for LP_COUNT usage.
90 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
92 * arc-dis.c (is_compatible_p): Remove function.
93 (skip_this_opcode): Don't add any decoding class to decode list.
95 (find_format_from_table): Go through all opcodes, and warn if we
96 use a guessed mnemonic.
98 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
99 Amit Pawar <amit.pawar@amd.com>
102 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
105 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
107 * configure: Regenerate.
109 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
111 * sparc-opc.c (HWS_V8): Definition moved from
112 gas/config/tc-sparc.c.
122 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
125 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
127 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
130 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
132 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
133 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
134 (aarch64_opcode_table): Add fcmla and fcadd.
135 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
136 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
137 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
138 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
139 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
140 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
141 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
142 (operand_general_constraint_met_p): Rotate and index range check.
143 (aarch64_print_operand): Handle rotate operand.
144 * aarch64-asm-2.c: Regenerate.
145 * aarch64-dis-2.c: Likewise.
146 * aarch64-opc-2.c: Likewise.
148 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
150 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
151 * aarch64-asm-2.c: Regenerate.
152 * aarch64-dis-2.c: Regenerate.
153 * aarch64-opc-2.c: Regenerate.
155 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
157 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
158 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
159 * aarch64-asm-2.c: Regenerate.
160 * aarch64-dis-2.c: Regenerate.
161 * aarch64-opc-2.c: Regenerate.
163 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
165 * aarch64-tbl.h (QL_X1NIL): New.
166 (arch64_opcode_table): Add ldraa, ldrab.
167 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
168 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
169 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
170 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
171 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
172 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
173 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
174 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
175 (aarch64_print_operand): Likewise.
176 * aarch64-asm-2.c: Regenerate.
177 * aarch64-dis-2.c: Regenerate.
178 * aarch64-opc-2.c: Regenerate.
180 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
182 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
183 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
184 * aarch64-asm-2.c: Regenerate.
185 * aarch64-dis-2.c: Regenerate.
186 * aarch64-opc-2.c: Regenerate.
188 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
190 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
191 (AARCH64_OPERANDS): Add Rm_SP.
192 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
193 * aarch64-asm-2.c: Regenerate.
194 * aarch64-dis-2.c: Regenerate.
195 * aarch64-opc-2.c: Regenerate.
197 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
199 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
200 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
201 autdzb, xpaci, xpacd.
202 * aarch64-asm-2.c: Regenerate.
203 * aarch64-dis-2.c: Regenerate.
204 * aarch64-opc-2.c: Regenerate.
206 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
208 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
209 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
210 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
211 (aarch64_sys_reg_supported_p): Add feature test for new registers.
213 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
215 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
216 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
217 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
219 * aarch64-asm-2.c: Regenerate.
220 * aarch64-dis-2.c: Regenerate.
222 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
224 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
226 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
229 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
230 * i386-dis.c (EdqwS): Removed.
231 (dqw_swap_mode): Likewise.
232 (intel_operand_size): Don't check dqw_swap_mode.
233 (OP_E_register): Likewise.
234 (OP_E_memory): Likewise.
237 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
238 * i386-tbl.h: Regerated.
240 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
242 * i386-opc.tbl: Merge AVX512F vmovq.
243 * i386-tbl.h: Regerated.
245 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
248 * i386-dis.c (THREE_BYTE_0F7A): Removed.
249 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
250 (three_byte_table): Remove THREE_BYTE_0F7A.
252 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
255 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
256 (FGRPd9_4): Replace 1 with 2.
257 (FGRPd9_5): Replace 2 with 3.
258 (FGRPd9_6): Replace 3 with 4.
259 (FGRPd9_7): Replace 4 with 5.
260 (FGRPda_5): Replace 5 with 6.
261 (FGRPdb_4): Replace 6 with 7.
262 (FGRPde_3): Replace 7 with 8.
263 (FGRPdf_4): Replace 8 with 9.
264 (fgrps): Add an entry for Bad_Opcode.
266 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
268 * arc-opc.c (arc_flag_operands): Add F_DI14.
269 (arc_flag_classes): Add C_DI14.
270 * arc-nps400-tbl.h: Add new exc instructions.
272 2016-11-03 Graham Markall <graham.markall@embecosm.com>
274 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
276 * arc-nps-400-tbl.h: Add dcmac instruction.
277 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
278 (insert_nps_rbdouble_64): Added.
279 (extract_nps_rbdouble_64): Added.
280 (insert_nps_proto_size): Added.
281 (extract_nps_proto_size): Added.
283 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
285 * arc-dis.c (struct arc_operand_iterator): Remove all fields
286 relating to long instruction processing, add new limm field.
287 (OPCODE): Rename to...
288 (OPCODE_32BIT_INSN): ...this.
290 (skip_this_opcode): Handle different instruction lengths, update
292 (special_flag_p): Update parameter type.
293 (find_format_from_table): Update for more instruction lengths.
294 (find_format_long_instructions): Delete.
295 (find_format): Update for more instruction lengths.
296 (arc_insn_length): Likewise.
297 (extract_operand_value): Update for more instruction lengths.
298 (operand_iterator_next): Remove code relating to long
300 (arc_opcode_to_insn_type): New function.
301 (print_insn_arc):Update for more instructions lengths.
302 * arc-ext.c (extInstruction_t): Change argument type.
303 * arc-ext.h (extInstruction_t): Change argument type.
304 * arc-fxi.h: Change type unsigned to unsigned long long
305 extensively throughout.
306 * arc-nps400-tbl.h: Add long instructions taken from
307 arc_long_opcodes table in arc-opc.c.
308 * arc-opc.c: Update parameter types on insert/extract handlers.
309 (arc_long_opcodes): Delete.
310 (arc_num_long_opcodes): Delete.
311 (arc_opcode_len): Update for more instruction lengths.
313 2016-11-03 Graham Markall <graham.markall@embecosm.com>
315 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
317 2016-11-03 Graham Markall <graham.markall@embecosm.com>
319 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
321 (find_format_long_instructions): Likewise.
322 * arc-opc.c (arc_opcode_len): New function.
324 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
326 * arc-nps400-tbl.h: Fix some instruction masks.
328 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
330 * i386-dis.c (REG_82): Removed.
331 (X86_64_82_REG_0): Likewise.
332 (X86_64_82_REG_1): Likewise.
333 (X86_64_82_REG_2): Likewise.
334 (X86_64_82_REG_3): Likewise.
335 (X86_64_82_REG_4): Likewise.
336 (X86_64_82_REG_5): Likewise.
337 (X86_64_82_REG_6): Likewise.
338 (X86_64_82_REG_7): Likewise.
340 (dis386): Use X86_64_82 instead of REG_82.
341 (reg_table): Remove REG_82.
342 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
343 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
344 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
347 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
350 * i386-dis.c (REG_82): New.
351 (X86_64_82_REG_0): Likewise.
352 (X86_64_82_REG_1): Likewise.
353 (X86_64_82_REG_2): Likewise.
354 (X86_64_82_REG_3): Likewise.
355 (X86_64_82_REG_4): Likewise.
356 (X86_64_82_REG_5): Likewise.
357 (X86_64_82_REG_6): Likewise.
358 (X86_64_82_REG_7): Likewise.
359 (dis386): Use REG_82.
360 (reg_table): Add REG_82.
361 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
362 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
363 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
365 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
367 * i386-dis.c (REG_82): Renamed to ...
370 (reg_table): Likewise.
372 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
374 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
375 * i386-dis-evex.h (evex_table): Updated.
376 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
377 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
378 (cpu_flags): Add CpuAVX512_4VNNIW.
379 * i386-opc.h (enum): (AVX512_4VNNIW): New.
380 (i386_cpu_flags): Add cpuavx512_4vnniw.
381 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
382 * i386-init.h: Regenerate.
385 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
387 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
388 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
389 * i386-dis-evex.h (evex_table): Updated.
390 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
391 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
392 (cpu_flags): Add CpuAVX512_4FMAPS.
393 (opcode_modifiers): Add ImplicitQuadGroup modifier.
394 * i386-opc.h (AVX512_4FMAP): New.
395 (i386_cpu_flags): Add cpuavx512_4fmaps.
396 (ImplicitQuadGroup): New.
397 (i386_opcode_modifier): Add implicitquadgroup.
398 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
399 * i386-init.h: Regenerate.
402 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
403 Andrew Waterman <andrew@sifive.com>
405 Add support for RISC-V architecture.
406 * configure.ac: Add entry for bfd_riscv_arch.
407 * configure: Regenerate.
408 * disassemble.c (disassembler): Add support for riscv.
409 (disassembler_usage): Likewise.
410 * riscv-dis.c: New file.
411 * riscv-opc.c: New file.
413 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
415 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
416 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
417 (rm_table): Update the RM_0FAE_REG_7 entry.
418 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
419 (cpu_flags): Remove CpuPCOMMIT.
420 * i386-opc.h (CpuPCOMMIT): Removed.
421 (i386_cpu_flags): Remove cpupcommit.
422 * i386-opc.tbl: Remove pcommit.
423 * i386-init.h: Regenerated.
424 * i386-tbl.h: Likewise.
426 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
429 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
430 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
431 32-bit mode. Don't check vex.register_specifier in 32-bit
433 (OP_VEX): Check for invalid mask registers.
435 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
438 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
441 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
444 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
446 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
448 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
449 local variable to `index_regno'.
451 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
453 * arc-tbl.h: Removed any "inv.+" instructions from the table.
455 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
457 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
460 2016-10-11 Jiong Wang <jiong.wang@arm.com>
463 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
465 2016-10-07 Jiong Wang <jiong.wang@arm.com>
468 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
471 2016-10-07 Alan Modra <amodra@gmail.com>
473 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
475 2016-10-06 Alan Modra <amodra@gmail.com>
477 * aarch64-opc.c: Spell fall through comments consistently.
478 * i386-dis.c: Likewise.
479 * aarch64-dis.c: Add missing fall through comments.
480 * aarch64-opc.c: Likewise.
481 * arc-dis.c: Likewise.
482 * arm-dis.c: Likewise.
483 * i386-dis.c: Likewise.
484 * m68k-dis.c: Likewise.
485 * mep-asm.c: Likewise.
486 * ns32k-dis.c: Likewise.
487 * sh-dis.c: Likewise.
488 * tic4x-dis.c: Likewise.
489 * tic6x-dis.c: Likewise.
490 * vax-dis.c: Likewise.
492 2016-10-06 Alan Modra <amodra@gmail.com>
494 * arc-ext.c (create_map): Add missing break.
495 * msp430-decode.opc (encode_as): Likewise.
496 * msp430-decode.c: Regenerate.
498 2016-10-06 Alan Modra <amodra@gmail.com>
500 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
501 * crx-dis.c (print_insn_crx): Likewise.
503 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
506 * i386-dis.c (putop): Don't assign alt twice.
508 2016-09-29 Jiong Wang <jiong.wang@arm.com>
511 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
513 2016-09-29 Alan Modra <amodra@gmail.com>
515 * ppc-opc.c (L): Make compulsory.
516 (LOPT): New, optional form of L.
517 (HTM_R): Define as LOPT.
519 (L32OPT): New, optional for 32-bit L.
520 (L2OPT): New, 2-bit L for dcbf.
523 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
524 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
526 <tlbiel, tlbie>: Use LOPT.
527 <wclr, wclrall>: Use L2.
529 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
531 * Makefile.in: Regenerate.
532 * configure: Likewise.
534 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
536 * arc-ext-tbl.h (EXTINSN2OPF): Define.
537 (EXTINSN2OP): Use EXTINSN2OPF.
538 (bspeekm, bspop, modapp): New extension instructions.
539 * arc-opc.c (F_DNZ_ND): Define.
544 * arc-tbl.h (dbnz): New instruction.
545 (prealloc): Allow it for ARC EM.
548 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
550 * aarch64-opc.c (print_immediate_offset_address): Print spaces
551 after commas in addresses.
552 (aarch64_print_operand): Likewise.
554 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
556 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
557 rather than "should be" or "expected to be" in error messages.
559 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
561 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
562 (print_mnemonic_name): ...here.
563 (print_comment): New function.
564 (print_aarch64_insn): Call it.
565 * aarch64-opc.c (aarch64_conds): Add SVE names.
566 (aarch64_print_operand): Print alternative condition names in
569 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
571 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
572 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
573 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
574 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
575 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
576 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
577 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
578 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
579 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
580 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
581 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
582 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
583 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
584 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
585 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
586 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
587 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
588 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
589 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
590 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
591 (OP_SVE_XWU, OP_SVE_XXU): New macros.
592 (aarch64_feature_sve): New variable.
594 (_SVE_INSN): Likewise.
595 (aarch64_opcode_table): Add SVE instructions.
596 * aarch64-opc.h (extract_fields): Declare.
597 * aarch64-opc-2.c: Regenerate.
598 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
599 * aarch64-asm-2.c: Regenerate.
600 * aarch64-dis.c (extract_fields): Make global.
601 (do_misc_decoding): Handle the new SVE aarch64_ops.
602 * aarch64-dis-2.c: Regenerate.
604 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
606 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
607 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
609 * aarch64-opc.c (fields): Add corresponding entries.
610 * aarch64-asm.c (aarch64_get_variant): New function.
611 (aarch64_encode_variant_using_iclass): Likewise.
612 (aarch64_opcode_encode): Call it.
613 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
614 (aarch64_opcode_decode): Call it.
616 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
618 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
619 and FP register operands.
620 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
621 (FLD_SVE_Vn): New aarch64_field_kinds.
622 * aarch64-opc.c (fields): Add corresponding entries.
623 (aarch64_print_operand): Handle the new SVE core and FP register
625 * aarch64-opc-2.c: Regenerate.
626 * aarch64-asm-2.c: Likewise.
627 * aarch64-dis-2.c: Likewise.
629 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
631 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
633 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
634 * aarch64-opc.c (fields): Add corresponding entry.
635 (operand_general_constraint_met_p): Handle the new SVE FP immediate
637 (aarch64_print_operand): Likewise.
638 * aarch64-opc-2.c: Regenerate.
639 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
640 (ins_sve_float_zero_one): New inserters.
641 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
642 (aarch64_ins_sve_float_half_two): Likewise.
643 (aarch64_ins_sve_float_zero_one): Likewise.
644 * aarch64-asm-2.c: Regenerate.
645 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
646 (ext_sve_float_zero_one): New extractors.
647 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
648 (aarch64_ext_sve_float_half_two): Likewise.
649 (aarch64_ext_sve_float_zero_one): Likewise.
650 * aarch64-dis-2.c: Regenerate.
652 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
654 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
655 integer immediate operands.
656 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
657 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
658 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
659 * aarch64-opc.c (fields): Add corresponding entries.
660 (operand_general_constraint_met_p): Handle the new SVE integer
662 (aarch64_print_operand): Likewise.
663 (aarch64_sve_dupm_mov_immediate_p): New function.
664 * aarch64-opc-2.c: Regenerate.
665 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
666 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
667 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
668 (aarch64_ins_limm): ...here.
669 (aarch64_ins_inv_limm): New function.
670 (aarch64_ins_sve_aimm): Likewise.
671 (aarch64_ins_sve_asimm): Likewise.
672 (aarch64_ins_sve_limm_mov): Likewise.
673 (aarch64_ins_sve_shlimm): Likewise.
674 (aarch64_ins_sve_shrimm): Likewise.
675 * aarch64-asm-2.c: Regenerate.
676 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
677 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
678 * aarch64-dis.c (decode_limm): New function, split out from...
679 (aarch64_ext_limm): ...here.
680 (aarch64_ext_inv_limm): New function.
681 (decode_sve_aimm): Likewise.
682 (aarch64_ext_sve_aimm): Likewise.
683 (aarch64_ext_sve_asimm): Likewise.
684 (aarch64_ext_sve_limm_mov): Likewise.
685 (aarch64_top_bit): Likewise.
686 (aarch64_ext_sve_shlimm): Likewise.
687 (aarch64_ext_sve_shrimm): Likewise.
688 * aarch64-dis-2.c: Regenerate.
690 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
692 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
694 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
695 the AARCH64_MOD_MUL_VL entry.
696 (value_aligned_p): Cope with non-power-of-two alignments.
697 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
698 (print_immediate_offset_address): Likewise.
699 (aarch64_print_operand): Likewise.
700 * aarch64-opc-2.c: Regenerate.
701 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
702 (ins_sve_addr_ri_s9xvl): New inserters.
703 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
704 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
705 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
706 * aarch64-asm-2.c: Regenerate.
707 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
708 (ext_sve_addr_ri_s9xvl): New extractors.
709 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
710 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
711 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
712 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
713 * aarch64-dis-2.c: Regenerate.
715 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
717 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
719 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
720 (FLD_SVE_xs_22): New aarch64_field_kinds.
721 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
722 (get_operand_specific_data): New function.
723 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
724 FLD_SVE_xs_14 and FLD_SVE_xs_22.
725 (operand_general_constraint_met_p): Handle the new SVE address
727 (sve_reg): New array.
728 (get_addr_sve_reg_name): New function.
729 (aarch64_print_operand): Handle the new SVE address operands.
730 * aarch64-opc-2.c: Regenerate.
731 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
732 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
733 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
734 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
735 (aarch64_ins_sve_addr_rr_lsl): Likewise.
736 (aarch64_ins_sve_addr_rz_xtw): Likewise.
737 (aarch64_ins_sve_addr_zi_u5): Likewise.
738 (aarch64_ins_sve_addr_zz): Likewise.
739 (aarch64_ins_sve_addr_zz_lsl): Likewise.
740 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
741 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
742 * aarch64-asm-2.c: Regenerate.
743 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
744 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
745 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
746 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
747 (aarch64_ext_sve_addr_ri_u6): Likewise.
748 (aarch64_ext_sve_addr_rr_lsl): Likewise.
749 (aarch64_ext_sve_addr_rz_xtw): Likewise.
750 (aarch64_ext_sve_addr_zi_u5): Likewise.
751 (aarch64_ext_sve_addr_zz): Likewise.
752 (aarch64_ext_sve_addr_zz_lsl): Likewise.
753 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
754 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
755 * aarch64-dis-2.c: Regenerate.
757 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
759 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
760 AARCH64_OPND_SVE_PATTERN_SCALED.
761 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
762 * aarch64-opc.c (fields): Add a corresponding entry.
763 (set_multiplier_out_of_range_error): New function.
764 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
765 (operand_general_constraint_met_p): Handle
766 AARCH64_OPND_SVE_PATTERN_SCALED.
767 (print_register_offset_address): Use PRIi64 to print the
769 (aarch64_print_operand): Likewise. Handle
770 AARCH64_OPND_SVE_PATTERN_SCALED.
771 * aarch64-opc-2.c: Regenerate.
772 * aarch64-asm.h (ins_sve_scale): New inserter.
773 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
774 * aarch64-asm-2.c: Regenerate.
775 * aarch64-dis.h (ext_sve_scale): New inserter.
776 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
777 * aarch64-dis-2.c: Regenerate.
779 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
781 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
782 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
783 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
784 (FLD_SVE_prfop): Likewise.
785 * aarch64-opc.c: Include libiberty.h.
786 (aarch64_sve_pattern_array): New variable.
787 (aarch64_sve_prfop_array): Likewise.
788 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
789 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
790 AARCH64_OPND_SVE_PRFOP.
791 * aarch64-asm-2.c: Regenerate.
792 * aarch64-dis-2.c: Likewise.
793 * aarch64-opc-2.c: Likewise.
795 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
797 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
798 AARCH64_OPND_QLF_P_[ZM].
799 (aarch64_print_operand): Print /z and /m where appropriate.
801 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
803 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
804 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
805 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
806 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
807 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
808 * aarch64-opc.c (fields): Add corresponding entries here.
809 (operand_general_constraint_met_p): Check that SVE register lists
810 have the correct length. Check the ranges of SVE index registers.
811 Check for cases where p8-p15 are used in 3-bit predicate fields.
812 (aarch64_print_operand): Handle the new SVE operands.
813 * aarch64-opc-2.c: Regenerate.
814 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
815 * aarch64-asm.c (aarch64_ins_sve_index): New function.
816 (aarch64_ins_sve_reglist): Likewise.
817 * aarch64-asm-2.c: Regenerate.
818 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
819 * aarch64-dis.c (aarch64_ext_sve_index): New function.
820 (aarch64_ext_sve_reglist): Likewise.
821 * aarch64-dis-2.c: Regenerate.
823 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
825 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
826 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
827 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
828 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
831 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
833 * aarch64-opc.c (get_offset_int_reg_name): New function.
834 (print_immediate_offset_address): Likewise.
835 (print_register_offset_address): Take the base and offset
836 registers as parameters.
837 (aarch64_print_operand): Update caller accordingly. Use
838 print_immediate_offset_address.
840 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
842 * aarch64-opc.c (BANK): New macro.
843 (R32, R64): Take a register number as argument
846 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
848 * aarch64-opc.c (print_register_list): Add a prefix parameter.
849 (aarch64_print_operand): Update accordingly.
851 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
853 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
855 * aarch64-asm.h (ins_fpimm): New inserter.
856 * aarch64-asm.c (aarch64_ins_fpimm): New function.
857 * aarch64-asm-2.c: Regenerate.
858 * aarch64-dis.h (ext_fpimm): New extractor.
859 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
860 (aarch64_ext_fpimm): New function.
861 * aarch64-dis-2.c: Regenerate.
863 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
865 * aarch64-asm.c: Include libiberty.h.
866 (insert_fields): New function.
867 (aarch64_ins_imm): Use it.
868 * aarch64-dis.c (extract_fields): New function.
869 (aarch64_ext_imm): Use it.
871 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
873 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
874 with an esize parameter.
875 (operand_general_constraint_met_p): Update accordingly.
876 Fix misindented code.
877 * aarch64-asm.c (aarch64_ins_limm): Update call to
878 aarch64_logical_immediate_p.
880 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
882 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
884 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
886 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
888 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
890 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
892 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
894 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
895 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
896 xor3>: Delete mnemonics.
897 <cp_abort>: Rename mnemonic from ...
898 <cpabort>: ...to this.
899 <setb>: Change to a X form instruction.
900 <sync>: Change to 1 operand form.
901 <copy>: Delete mnemonic.
902 <copy_first>: Rename mnemonic from ...
904 <paste, paste.>: Delete mnemonics.
905 <paste_last>: Rename mnemonic from ...
906 <paste.>: ...to this.
908 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
910 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
912 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
914 * s390-mkopc.c (main): Support alternate arch strings.
916 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
918 * s390-opc.txt: Fix kmctr instruction type.
920 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
922 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
923 * i386-init.h: Regenerated.
925 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
927 * opcodes/arc-dis.c (print_insn_arc): Changed.
929 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
931 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
934 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
936 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
937 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
938 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
940 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
942 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
943 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
944 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
945 PREFIX_MOD_3_0FAE_REG_4.
946 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
947 PREFIX_MOD_3_0FAE_REG_4.
948 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
949 (cpu_flags): Add CpuPTWRITE.
950 * i386-opc.h (CpuPTWRITE): New.
951 (i386_cpu_flags): Add cpuptwrite.
952 * i386-opc.tbl: Add ptwrite instruction.
953 * i386-init.h: Regenerated.
954 * i386-tbl.h: Likewise.
956 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
958 * arc-dis.h: Wrap around in extern "C".
960 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
962 * aarch64-tbl.h (V8_2_INSN): New macro.
963 (aarch64_opcode_table): Use it.
965 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
967 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
968 CORE_INSN, __FP_INSN and SIMD_INSN.
970 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
972 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
973 (aarch64_opcode_table): Update uses accordingly.
975 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
976 Kwok Cheung Yeung <kcy@codesourcery.com>
979 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
980 'e_cmplwi' to 'e_cmpli' instead.
981 (OPVUPRT, OPVUPRT_MASK): Define.
982 (powerpc_opcodes): Add E200Z4 insns.
983 (vle_opcodes): Add context save/restore insns.
985 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
987 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
988 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
991 2016-07-27 Graham Markall <graham.markall@embecosm.com>
993 * arc-nps400-tbl.h: Change block comments to GNU format.
994 * arc-dis.c: Add new globals addrtypenames,
995 addrtypenames_max, and addtypeunknown.
996 (get_addrtype): New function.
997 (print_insn_arc): Print colons and address types when
999 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1000 define insert and extract functions for all address types.
1001 (arc_operands): Add operands for colon and all address
1003 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1004 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1005 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1006 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1007 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1008 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1010 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1012 * configure: Regenerated.
1014 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1016 * arc-dis.c (skipclass): New structure.
1017 (decodelist): New variable.
1018 (is_compatible_p): New function.
1019 (new_element): Likewise.
1020 (skip_class_p): Likewise.
1021 (find_format_from_table): Use skip_class_p function.
1022 (find_format): Decode first the extension instructions.
1023 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1025 (parse_option): New function.
1026 (parse_disassembler_options): Likewise.
1027 (print_arc_disassembler_options): Likewise.
1028 (print_insn_arc): Use parse_disassembler_options function. Proper
1029 select ARCv2 cpu variant.
1030 * disassemble.c (disassembler_usage): Add ARC disassembler
1033 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1035 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1036 annotation from the "nal" entry and reorder it beyond "bltzal".
1038 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1040 * sparc-opc.c (ldtxa): New macro.
1041 (sparc_opcodes): Use the macro defined above to add entries for
1042 the LDTXA instructions.
1043 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1046 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1048 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1051 2016-07-01 Jan Beulich <jbeulich@suse.com>
1053 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1054 (movzb): Adjust to cover all permitted suffixes.
1056 * i386-tbl.h: Re-generate.
1058 2016-07-01 Jan Beulich <jbeulich@suse.com>
1060 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1061 (lgdt): Remove Tbyte from non-64-bit variant.
1062 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1063 xsaves64, xsavec64): Remove Disp16.
1064 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1065 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1067 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1068 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1069 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1071 * i386-tbl.h: Re-generate.
1073 2016-07-01 Jan Beulich <jbeulich@suse.com>
1075 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1076 * i386-tbl.h: Re-generate.
1078 2016-06-30 Yao Qi <yao.qi@linaro.org>
1080 * arm-dis.c (print_insn): Fix typo in comment.
1082 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1084 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1085 range of ldst_elemlist operands.
1086 (print_register_list): Use PRIi64 to print the index.
1087 (aarch64_print_operand): Likewise.
1089 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1091 * mcore-opc.h: Remove sentinal.
1092 * mcore-dis.c (print_insn_mcore): Adjust.
1094 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1096 * arc-opc.c: Correct description of availability of NPS400
1099 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1101 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1102 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1103 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1104 xor3>: New mnemonics.
1105 <setb>: Change to a VX form instruction.
1106 (insert_sh6): Add support for rldixor.
1107 (extract_sh6): Likewise.
1109 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1111 * arc-ext.h: Wrap in extern C.
1113 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1115 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1116 Use same method for determining instruction length on ARC700 and
1118 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1119 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1120 with the NPS400 subclass.
1121 * arc-opc.c: Likewise.
1123 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1125 * sparc-opc.c (rdasr): New macro.
1131 (sparc_opcodes): Use the macros above to fix and expand the
1132 definition of read/write instructions from/to
1133 asr/privileged/hyperprivileged instructions.
1134 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1135 %hva_mask_nz. Prefer softint_set and softint_clear over
1136 set_softint and clear_softint.
1137 (print_insn_sparc): Support %ver in Rd.
1139 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1141 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1142 architecture according to the hardware capabilities they require.
1144 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1146 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1147 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1148 bfd_mach_sparc_v9{c,d,e,v,m}.
1149 * sparc-opc.c (MASK_V9C): Define.
1150 (MASK_V9D): Likewise.
1151 (MASK_V9E): Likewise.
1152 (MASK_V9V): Likewise.
1153 (MASK_V9M): Likewise.
1154 (v6): Add MASK_V9{C,D,E,V,M}.
1155 (v6notlet): Likewise.
1159 (v9andleon): Likewise.
1167 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1169 2016-06-15 Nick Clifton <nickc@redhat.com>
1171 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1172 constants to match expected behaviour.
1173 (nds32_parse_opcode): Likewise. Also for whitespace.
1175 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1177 * arc-opc.c (extract_rhv1): Extract value from insn.
1179 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1181 * arc-nps400-tbl.h: Add ldbit instruction.
1182 * arc-opc.c: Add flag classes required for ldbit.
1184 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1186 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1187 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1188 support the above instructions.
1190 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1192 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1193 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1194 csma, cbba, zncv, and hofs.
1195 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1196 support the above instructions.
1198 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1200 * arc-nps400-tbl.h: Add andab and orab instructions.
1202 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1204 * arc-nps400-tbl.h: Add addl-like instructions.
1206 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1208 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1210 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1212 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1215 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1217 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1219 (init_disasm): Handle new command line option "insnlength".
1220 (print_s390_disassembler_options): Mention new option in help
1222 (print_insn_s390): Use the encoded insn length when dumping
1223 unknown instructions.
1225 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1227 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1228 to the address and set as symbol address for LDS/ STS immediate operands.
1230 2016-06-07 Alan Modra <amodra@gmail.com>
1232 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1233 cpu for "vle" to e500.
1234 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1235 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1236 (PPCNONE): Delete, substitute throughout.
1237 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1238 except for major opcode 4 and 31.
1239 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1241 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1243 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1244 ARM_EXT_RAS in relevant entries.
1246 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1249 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1252 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1255 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1256 (indir_v_mode): New.
1257 Add comments for '&'.
1258 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1259 (putop): Handle '&'.
1260 (intel_operand_size): Handle indir_v_mode.
1261 (OP_E_register): Likewise.
1262 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1263 64-bit indirect call/jmp for AMD64.
1264 * i386-tbl.h: Regenerated
1266 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1268 * arc-dis.c (struct arc_operand_iterator): New structure.
1269 (find_format_from_table): All the old content from find_format,
1270 with some minor adjustments, and parameter renaming.
1271 (find_format_long_instructions): New function.
1272 (find_format): Rewritten.
1273 (arc_insn_length): Add LSB parameter.
1274 (extract_operand_value): New function.
1275 (operand_iterator_next): New function.
1276 (print_insn_arc): Use new functions to find opcode, and iterator
1278 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1279 (extract_nps_3bit_dst_short): New function.
1280 (insert_nps_3bit_src2_short): New function.
1281 (extract_nps_3bit_src2_short): New function.
1282 (insert_nps_bitop1_size): New function.
1283 (extract_nps_bitop1_size): New function.
1284 (insert_nps_bitop2_size): New function.
1285 (extract_nps_bitop2_size): New function.
1286 (insert_nps_bitop_mod4_msb): New function.
1287 (extract_nps_bitop_mod4_msb): New function.
1288 (insert_nps_bitop_mod4_lsb): New function.
1289 (extract_nps_bitop_mod4_lsb): New function.
1290 (insert_nps_bitop_dst_pos3_pos4): New function.
1291 (extract_nps_bitop_dst_pos3_pos4): New function.
1292 (insert_nps_bitop_ins_ext): New function.
1293 (extract_nps_bitop_ins_ext): New function.
1294 (arc_operands): Add new operands.
1295 (arc_long_opcodes): New global array.
1296 (arc_num_long_opcodes): New global.
1297 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1299 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1301 * nds32-asm.h: Add extern "C".
1302 * sh-opc.h: Likewise.
1304 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1306 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1307 0,b,limm to the rflt instruction.
1309 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1311 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1314 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1317 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1318 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1319 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1320 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1321 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1322 * i386-init.h: Regenerated.
1324 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1327 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1328 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1329 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1330 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1331 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1332 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1333 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1334 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1335 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1336 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1337 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1338 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1339 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1340 CpuRegMask for AVX512.
1341 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1343 (set_bitfield_from_cpu_flag_init): New function.
1344 (set_bitfield): Remove const on f. Call
1345 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1346 * i386-opc.h (CpuRegMMX): New.
1347 (CpuRegXMM): Likewise.
1348 (CpuRegYMM): Likewise.
1349 (CpuRegZMM): Likewise.
1350 (CpuRegMask): Likewise.
1351 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1353 * i386-init.h: Regenerated.
1354 * i386-tbl.h: Likewise.
1356 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1359 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1360 (opcode_modifiers): Add AMD64 and Intel64.
1361 (main): Properly verify CpuMax.
1362 * i386-opc.h (CpuAMD64): Removed.
1363 (CpuIntel64): Likewise.
1364 (CpuMax): Set to CpuNo64.
1365 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1367 (Intel64): Likewise.
1368 (i386_opcode_modifier): Add amd64 and intel64.
1369 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1371 * i386-init.h: Regenerated.
1372 * i386-tbl.h: Likewise.
1374 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1377 * i386-gen.c (main): Fail if CpuMax is incorrect.
1378 * i386-opc.h (CpuMax): Set to CpuIntel64.
1379 * i386-tbl.h: Regenerated.
1381 2016-05-27 Nick Clifton <nickc@redhat.com>
1384 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1385 (msp430dis_opcode_unsigned): New function.
1386 (msp430dis_opcode_signed): New function.
1387 (msp430_singleoperand): Use the new opcode reading functions.
1388 Only disassenmble bytes if they were successfully read.
1389 (msp430_doubleoperand): Likewise.
1390 (msp430_branchinstr): Likewise.
1391 (msp430x_callx_instr): Likewise.
1392 (print_insn_msp430): Check that it is safe to read bytes before
1393 attempting disassembly. Use the new opcode reading functions.
1395 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1397 * ppc-opc.c (CY): New define. Document it.
1398 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1400 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1402 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1403 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1404 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1405 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1407 * i386-init.h: Regenerated.
1409 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1412 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1413 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1414 * i386-init.h: Regenerated.
1416 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1418 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1419 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1420 * i386-init.h: Regenerated.
1422 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1424 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1426 (print_insn_arc): Set insn_type information.
1427 * arc-opc.c (C_CC): Add F_CLASS_COND.
1428 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1429 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1430 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1431 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1432 (brne, brne_s, jeq_s, jne_s): Likewise.
1434 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1436 * arc-tbl.h (neg): New instruction variant.
1438 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1440 * arc-dis.c (find_format, find_format, get_auxreg)
1441 (print_insn_arc): Changed.
1442 * arc-ext.h (INSERT_XOP): Likewise.
1444 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1446 * tic54x-dis.c (sprint_mmr): Adjust.
1447 * tic54x-opc.c: Likewise.
1449 2016-05-19 Alan Modra <amodra@gmail.com>
1451 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1453 2016-05-19 Alan Modra <amodra@gmail.com>
1455 * ppc-opc.c: Formatting.
1456 (NSISIGNOPT): Define.
1457 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1459 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1461 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1462 replacing references to `micromips_ase' throughout.
1463 (_print_insn_mips): Don't use file-level microMIPS annotation to
1464 determine the disassembly mode with the symbol table.
1466 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1468 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1470 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1472 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1474 * mips-opc.c (D34): New macro.
1475 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1477 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1479 * i386-dis.c (prefix_table): Add RDPID instruction.
1480 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1481 (cpu_flags): Add RDPID bitfield.
1482 * i386-opc.h (enum): Add RDPID element.
1483 (i386_cpu_flags): Add RDPID field.
1484 * i386-opc.tbl: Add RDPID instruction.
1485 * i386-init.h: Regenerate.
1486 * i386-tbl.h: Regenerate.
1488 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1490 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1491 branch type of a symbol.
1492 (print_insn): Likewise.
1494 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1496 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1497 Mainline Security Extensions instructions.
1498 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1499 Extensions instructions.
1500 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1502 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1505 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1507 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1509 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1511 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1512 (arcExtMap_genOpcode): Likewise.
1513 * arc-opc.c (arg_32bit_rc): Define new variable.
1514 (arg_32bit_u6): Likewise.
1515 (arg_32bit_limm): Likewise.
1517 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1519 * aarch64-gen.c (VERIFIER): Define.
1520 * aarch64-opc.c (VERIFIER): Define.
1521 (verify_ldpsw): Use static linkage.
1522 * aarch64-opc.h (verify_ldpsw): Remove.
1523 * aarch64-tbl.h: Use VERIFIER for verifiers.
1525 2016-04-28 Nick Clifton <nickc@redhat.com>
1528 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1529 * aarch64-opc.c (verify_ldpsw): New function.
1530 * aarch64-opc.h (verify_ldpsw): New prototype.
1531 * aarch64-tbl.h: Add initialiser for verifier field.
1532 (LDPSW): Set verifier to verify_ldpsw.
1534 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1538 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1539 smaller than address size.
1541 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1543 * alpha-dis.c: Regenerate.
1544 * crx-dis.c: Likewise.
1545 * disassemble.c: Likewise.
1546 * epiphany-opc.c: Likewise.
1547 * fr30-opc.c: Likewise.
1548 * frv-opc.c: Likewise.
1549 * ip2k-opc.c: Likewise.
1550 * iq2000-opc.c: Likewise.
1551 * lm32-opc.c: Likewise.
1552 * lm32-opinst.c: Likewise.
1553 * m32c-opc.c: Likewise.
1554 * m32r-opc.c: Likewise.
1555 * m32r-opinst.c: Likewise.
1556 * mep-opc.c: Likewise.
1557 * mt-opc.c: Likewise.
1558 * or1k-opc.c: Likewise.
1559 * or1k-opinst.c: Likewise.
1560 * tic80-opc.c: Likewise.
1561 * xc16x-opc.c: Likewise.
1562 * xstormy16-opc.c: Likewise.
1564 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1566 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1567 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1568 calcsd, and calcxd instructions.
1569 * arc-opc.c (insert_nps_bitop_size): Delete.
1570 (extract_nps_bitop_size): Delete.
1571 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1572 (extract_nps_qcmp_m3): Define.
1573 (extract_nps_qcmp_m2): Define.
1574 (extract_nps_qcmp_m1): Define.
1575 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1576 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1577 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1578 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1579 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1582 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1584 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1586 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1588 * Makefile.in: Regenerated with automake 1.11.6.
1589 * aclocal.m4: Likewise.
1591 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1593 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1595 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1596 (extract_nps_cmem_uimm16): New function.
1597 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1599 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1601 * arc-dis.c (arc_insn_length): New function.
1602 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1603 (find_format): Change insnLen parameter to unsigned.
1605 2016-04-13 Nick Clifton <nickc@redhat.com>
1608 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1609 the LD.B and LD.BU instructions.
1611 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1613 * arc-dis.c (find_format): Check for extension flags.
1614 (print_flags): New function.
1615 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1617 * arc-ext.c (arcExtMap_coreRegName): Use
1618 LAST_EXTENSION_CORE_REGISTER.
1619 (arcExtMap_coreReadWrite): Likewise.
1620 (dump_ARC_extmap): Update printing.
1621 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1622 (arc_aux_regs): Add cpu field.
1623 * arc-regs.h: Add cpu field, lower case name aux registers.
1625 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1627 * arc-tbl.h: Add rtsc, sleep with no arguments.
1629 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1631 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1633 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1634 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1635 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1636 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1637 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1638 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1639 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1640 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1641 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1642 (arc_opcode arc_opcodes): Null terminate the array.
1643 (arc_num_opcodes): Remove.
1644 * arc-ext.h (INSERT_XOP): Define.
1645 (extInstruction_t): Likewise.
1646 (arcExtMap_instName): Delete.
1647 (arcExtMap_insn): New function.
1648 (arcExtMap_genOpcode): Likewise.
1649 * arc-ext.c (ExtInstruction): Remove.
1650 (create_map): Zero initialize instruction fields.
1651 (arcExtMap_instName): Remove.
1652 (arcExtMap_insn): New function.
1653 (dump_ARC_extmap): More info while debuging.
1654 (arcExtMap_genOpcode): New function.
1655 * arc-dis.c (find_format): New function.
1656 (print_insn_arc): Use find_format.
1657 (arc_get_disassembler): Enable dump_ARC_extmap only when
1660 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1662 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1663 instruction bits out.
1665 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1667 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1668 * arc-opc.c (arc_flag_operands): Add new flags.
1669 (arc_flag_classes): Add new classes.
1671 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1673 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1675 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1677 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1678 encode1, rflt, crc16, and crc32 instructions.
1679 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1680 (arc_flag_classes): Add C_NPS_R.
1681 (insert_nps_bitop_size_2b): New function.
1682 (extract_nps_bitop_size_2b): Likewise.
1683 (insert_nps_bitop_uimm8): Likewise.
1684 (extract_nps_bitop_uimm8): Likewise.
1685 (arc_operands): Add new operand entries.
1687 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1689 * arc-regs.h: Add a new subclass field. Add double assist
1690 accumulator register values.
1691 * arc-tbl.h: Use DPA subclass to mark the double assist
1692 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1693 * arc-opc.c (RSP): Define instead of SP.
1694 (arc_aux_regs): Add the subclass field.
1696 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1698 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1700 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1702 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1705 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1707 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1708 issues. No functional changes.
1710 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1712 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1713 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1714 (RTT): Remove duplicate.
1715 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1716 (PCT_CONFIG*): Remove.
1717 (D1L, D1H, D2H, D2L): Define.
1719 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1721 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1723 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1725 * arc-tbl.h (invld07): Remove.
1726 * arc-ext-tbl.h: New file.
1727 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1728 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1730 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1732 Fix -Wstack-usage warnings.
1733 * aarch64-dis.c (print_operands): Substitute size.
1734 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1736 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1738 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1739 to get a proper diagnostic when an invalid ASR register is used.
1741 2016-03-22 Nick Clifton <nickc@redhat.com>
1743 * configure: Regenerate.
1745 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1747 * arc-nps400-tbl.h: New file.
1748 * arc-opc.c: Add top level comment.
1749 (insert_nps_3bit_dst): New function.
1750 (extract_nps_3bit_dst): New function.
1751 (insert_nps_3bit_src2): New function.
1752 (extract_nps_3bit_src2): New function.
1753 (insert_nps_bitop_size): New function.
1754 (extract_nps_bitop_size): New function.
1755 (arc_flag_operands): Add nps400 entries.
1756 (arc_flag_classes): Add nps400 entries.
1757 (arc_operands): Add nps400 entries.
1758 (arc_opcodes): Add nps400 include.
1760 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1762 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1763 the new class enum values.
1765 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1767 * arc-dis.c (print_insn_arc): Handle nps400.
1769 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1771 * arc-opc.c (BASE): Delete.
1773 2016-03-18 Nick Clifton <nickc@redhat.com>
1776 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1777 of MOV insn that aliases an ORR insn.
1779 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1781 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1783 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1785 * mcore-opc.h: Add const qualifiers.
1786 * microblaze-opc.h (struct op_code_struct): Likewise.
1787 * sh-opc.h: Likewise.
1788 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1789 (tic4x_print_op): Likewise.
1791 2016-03-02 Alan Modra <amodra@gmail.com>
1793 * or1k-desc.h: Regenerate.
1794 * fr30-ibld.c: Regenerate.
1795 * rl78-decode.c: Regenerate.
1797 2016-03-01 Nick Clifton <nickc@redhat.com>
1800 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1802 2016-02-24 Renlin Li <renlin.li@arm.com>
1804 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1805 (print_insn_coprocessor): Support fp16 instructions.
1807 2016-02-24 Renlin Li <renlin.li@arm.com>
1809 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1810 vminnm, vrint(mpna).
1812 2016-02-24 Renlin Li <renlin.li@arm.com>
1814 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1815 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1817 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1819 * i386-dis.c (print_insn): Parenthesize expression to prevent
1820 truncated addresses.
1823 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1824 Janek van Oirschot <jvanoirs@synopsys.com>
1826 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1829 2016-02-04 Nick Clifton <nickc@redhat.com>
1832 * msp430-dis.c (print_insn_msp430): Add a special case for
1833 decoding an RRC instruction with the ZC bit set in the extension
1836 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1838 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1839 * epiphany-ibld.c: Regenerate.
1840 * fr30-ibld.c: Regenerate.
1841 * frv-ibld.c: Regenerate.
1842 * ip2k-ibld.c: Regenerate.
1843 * iq2000-ibld.c: Regenerate.
1844 * lm32-ibld.c: Regenerate.
1845 * m32c-ibld.c: Regenerate.
1846 * m32r-ibld.c: Regenerate.
1847 * mep-ibld.c: Regenerate.
1848 * mt-ibld.c: Regenerate.
1849 * or1k-ibld.c: Regenerate.
1850 * xc16x-ibld.c: Regenerate.
1851 * xstormy16-ibld.c: Regenerate.
1853 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1855 * epiphany-dis.c: Regenerated from latest cpu files.
1857 2016-02-01 Michael McConville <mmcco@mykolab.com>
1859 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1862 2016-01-25 Renlin Li <renlin.li@arm.com>
1864 * arm-dis.c (mapping_symbol_for_insn): New function.
1865 (find_ifthen_state): Call mapping_symbol_for_insn().
1867 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1869 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1870 of MSR UAO immediate operand.
1872 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1874 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1875 instruction support.
1877 2016-01-17 Alan Modra <amodra@gmail.com>
1879 * configure: Regenerate.
1881 2016-01-14 Nick Clifton <nickc@redhat.com>
1883 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1884 instructions that can support stack pointer operations.
1885 * rl78-decode.c: Regenerate.
1886 * rl78-dis.c: Fix display of stack pointer in MOVW based
1889 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1891 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1892 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1893 erxtatus_el1 and erxaddr_el1.
1895 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1897 * arm-dis.c (arm_opcodes): Add "esb".
1898 (thumb_opcodes): Likewise.
1900 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1902 * ppc-opc.c <xscmpnedp>: Delete.
1903 <xvcmpnedp>: Likewise.
1904 <xvcmpnedp.>: Likewise.
1905 <xvcmpnesp>: Likewise.
1906 <xvcmpnesp.>: Likewise.
1908 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1911 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1914 2016-01-01 Alan Modra <amodra@gmail.com>
1916 Update year range in copyright notice of all files.
1918 For older changes see ChangeLog-2015
1920 Copyright (C) 2016 Free Software Foundation, Inc.
1922 Copying and distribution of this file, with or without modification,
1923 are permitted in any medium without royalty provided the copyright
1924 notice and this notice are preserved.
1930 version-control: never