opcodes/ChangeLog

   1 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * configure: Regenerated.
   4
   5 2015-07-03  Alan Modra  <amodra@gmail.com>
   6
   7         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
   8         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
   9         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
  10
  11 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
  12             Cesar Philippidis  <cesar@codesourcery.com>
  13
  14         * nios2-dis.c (nios2_extract_opcode): New.
  15         (nios2_disassembler_state): New.
  16         (nios2_find_opcode_hash): Use mach parameter to select correct
  17         disassembler state.
  18         (nios2_print_insn_arg): Extend to support new R2 argument letters
  19         and formats.
  20         (print_insn_nios2): Check for 16-bit instruction at end of memory.
  21         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
  22         (NIOS2_NUM_OPCODES): Rename to...
  23         (NIOS2_NUM_R1_OPCODES): This.
  24         (nios2_r2_opcodes): New.
  25         (NIOS2_NUM_R2_OPCODES): New.
  26         (nios2_num_r2_opcodes): New.
  27         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
  28         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
  29         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
  30         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
  31         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
  32
  33 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
  34
  35         * i386-dis.c (OP_Mwaitx): New.
  36         (rm_table): Add monitorx/mwaitx.
  37         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
  38         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
  39         (operand_type_init): Add CpuMWAITX.
  40         * i386-opc.h (CpuMWAITX): New.
  41         (i386_cpu_flags): Add cpumwaitx.
  42         * i386-opc.tbl: Add monitorx and mwaitx.
  43         * i386-init.h: Regenerated.
  44         * i386-tbl.h: Likewise.
  45
  46 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
  47
  48         * ppc-opc.c (insert_ls): Test for invalid LS operands.
  49         (insert_esync): New function.
  50         (LS, WC): Use insert_ls.
  51         (ESYNC): Use insert_esync.
  52
  53 2015-06-22  Nick Clifton  <nickc@redhat.com>
  54
  55         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
  56         requested region lies beyond it.
  57         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
  58         looking for 32-bit insns.
  59         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
  60         data.
  61         * sh-dis.c (print_insn_sh): Likewise.
  62         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
  63         blocks of instructions.
  64         * vax-dis.c (print_insn_vax): Check that the requested address
  65         does not clash with the stop_vma.
  66
  67 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
  68
  69         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
  70         * ppc-opc.c (FXM4): Add non-zero optional value.
  71         (TBR): Likewise.
  72         (SXL): Likewise.
  73         (insert_fxm): Handle new default operand value.
  74         (extract_fxm): Likewise.
  75         (insert_tbr): Likewise.
  76         (extract_tbr): Likewise.
  77
  78 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
  79
  80         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
  81
  82 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  83
  84         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
  85
  86 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
  87
  88         * ppc-opc.c: Add comment accidentally removed by old commit.
  89         (MTMSRD_L): Delete.
  90
  91 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
  92
  93         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
  94
  95 2015-06-04  Nick Clifton  <nickc@redhat.com>
  96
  97         PR 18474
  98         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
  99
 100 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 101
 102         * arm-dis.c (arm_opcodes): Add "setpan".
 103         (thumb_opcodes): Add "setpan".
 104
 105 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 106
 107         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 108         macros.
 109
 110 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 111
 112         * aarch64-tbl.h (aarch64_feature_rdma): New.
 113         (RDMA): New.
 114         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 115         * aarch64-asm-2.c: Regenerate.
 116         * aarch64-dis-2.c: Regenerate.
 117         * aarch64-opc-2.c: Regenerate.
 118
 119 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 120
 121         * aarch64-tbl.h (aarch64_feature_lor): New.
 122         (LOR): New.
 123         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 124         "stllrb", "stllrh".
 125         * aarch64-asm-2.c: Regenerate.
 126         * aarch64-dis-2.c: Regenerate.
 127         * aarch64-opc-2.c: Regenerate.
 128
 129 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 130
 131         * aarch64-opc.c (F_ARCHEXT): New.
 132         (aarch64_sys_regs): Add "pan".
 133         (aarch64_sys_reg_supported_p): New.
 134         (aarch64_pstatefields): Add "pan".
 135         (aarch64_pstatefield_supported_p): New.
 136
 137 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-tbl.h: Regenerate.
 140
 141 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 142
 143         * i386-dis.c (print_insn): Swap rounding mode specifier and
 144         general purpose register in Intel mode.
 145
 146 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 147
 148         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 149         * i386-tbl.h: Regenerate.
 150
 151 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 152
 153         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 154         * i386-init.h: Regenerated.
 155
 156 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 157
 158         PR binutis/18386
 159         * i386-dis.c: Add comments for '@'.
 160         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 161         (enum x86_64_isa): New.
 162         (isa64): Likewise.
 163         (print_i386_disassembler_options): Add amd64 and intel64.
 164         (print_insn): Handle amd64 and intel64.
 165         (putop): Handle '@'.
 166         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 167         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 168         * i386-opc.h (AMD64): New.
 169         (CpuIntel64): Likewise.
 170         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 171         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 172         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 173         * i386-init.h: Regenerated.
 174         * i386-tbl.h: Likewise.
 175
 176 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 177
 178         * ppc-opc.c (IH) New define.
 179         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 180         <tlbie>: Add RS operand for POWER7.
 181         <slbia>: Add IH operand for POWER6.
 182
 183 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 184
 185         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 186         direct branch.
 187         (jmp): Likewise.
 188         * i386-tbl.h: Regenerated.
 189
 190 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 191
 192         * configure.ac: Support bfd_iamcu_arch.
 193         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 194         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 195         CPU_IAMCU_COMPAT_FLAGS.
 196         (cpu_flags): Add CpuIAMCU.
 197         * i386-opc.h (CpuIAMCU): New.
 198         (i386_cpu_flags): Add cpuiamcu.
 199         * configure: Regenerated.
 200         * i386-init.h: Likewise.
 201         * i386-tbl.h: Likewise.
 202
 203 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 204
 205         PR binutis/18386
 206         * i386-dis.c (X86_64_E8): New.
 207         (X86_64_E9): Likewise.
 208         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 209         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 210         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 211         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 212         (putop): Handle '^'.
 213         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 214         REX_W.
 215
 216 2015-04-30  DJ Delorie  <dj@redhat.com>
 217
 218         * disassemble.c (disassembler): Choose suitable disassembler based
 219         on E_ABI.
 220         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 221         it to decode mul/div insns.
 222         * rl78-decode.c: Regenerate.
 223         * rl78-dis.c (print_insn_rl78): Rename to...
 224         (print_insn_rl78_common): ...this, take ISA parameter.
 225         (print_insn_rl78): New.
 226         (print_insn_rl78_g10): New.
 227         (print_insn_rl78_g13): New.
 228         (print_insn_rl78_g14): New.
 229         (rl78_get_disassembler): New.
 230
 231 2015-04-29  Nick Clifton  <nickc@redhat.com>
 232
 233         * po/fr.po: Updated French translation.
 234
 235 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 236
 237         * ppc-opc.c (DCBT_EO): New define.
 238         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 239         <lharx>: Likewise.
 240         <stbcx.>: Likewise.
 241         <sthcx.>: Likewise.
 242         <waitrsv>: Do not enable for POWER7 and later.
 243         <waitimpl>: Likewise.
 244         <dcbt>: Default to the two operand form of the instruction for all
 245         "old" cpus.  For "new" cpus, use the operand ordering that matches
 246         whether the cpu is server or embedded.
 247         <dcbtst>: Likewise.
 248
 249 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 250
 251         * s390-opc.c: New instruction type VV0UU2.
 252         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 253         and WFC.
 254
 255 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 256
 257         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 258         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 259         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 260         (vfpclasspd, vfpclassps): Add %XZ.
 261
 262 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 263
 264         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 265         (PREFIX_UD_REPZ): Likewise.
 266         (PREFIX_UD_REPNZ): Likewise.
 267         (PREFIX_UD_DATA): Likewise.
 268         (PREFIX_UD_ADDR): Likewise.
 269         (PREFIX_UD_LOCK): Likewise.
 270
 271 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 272
 273         * i386-dis.c (prefix_requirement): Removed.
 274         (print_insn): Don't set prefix_requirement.  Check
 275         dp->prefix_requirement instead of prefix_requirement.
 276
 277 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 278
 279         PR binutils/17898
 280         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 281         (PREFIX_MOD_0_0FC7_REG_6): This.
 282         (PREFIX_MOD_3_0FC7_REG_6): New.
 283         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 284         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 285         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 286         PREFIX_MOD_3_0FC7_REG_7.
 287         (mod_table): Replace PREFIX_0FC7_REG_6 with
 288         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 289         PREFIX_MOD_3_0FC7_REG_7.
 290
 291 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 292
 293         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 294         (PREFIX_MANDATORY_REPNZ): Likewise.
 295         (PREFIX_MANDATORY_DATA): Likewise.
 296         (PREFIX_MANDATORY_ADDR): Likewise.
 297         (PREFIX_MANDATORY_LOCK): Likewise.
 298         (PREFIX_MANDATORY): Likewise.
 299         (PREFIX_UD_SHIFT): Set to 8
 300         (PREFIX_UD_REPZ): Updated.
 301         (PREFIX_UD_REPNZ): Likewise.
 302         (PREFIX_UD_DATA): Likewise.
 303         (PREFIX_UD_ADDR): Likewise.
 304         (PREFIX_UD_LOCK): Likewise.
 305         (PREFIX_IGNORED_SHIFT): New.
 306         (PREFIX_IGNORED_REPZ): Likewise.
 307         (PREFIX_IGNORED_REPNZ): Likewise.
 308         (PREFIX_IGNORED_DATA): Likewise.
 309         (PREFIX_IGNORED_ADDR): Likewise.
 310         (PREFIX_IGNORED_LOCK): Likewise.
 311         (PREFIX_OPCODE): Likewise.
 312         (PREFIX_IGNORED): Likewise.
 313         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 314         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 315         (three_byte_table): Likewise.
 316         (mod_table): Likewise.
 317         (mandatory_prefix): Renamed to ...
 318         (prefix_requirement): This.
 319         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 320         Update PREFIX_90 entry.
 321         (get_valid_dis386): Check prefix_requirement to see if a prefix
 322         should be ignored.
 323         (print_insn): Replace mandatory_prefix with prefix_requirement.
 324
 325 2015-04-15  Renlin Li  <renlin.li@arm.com>
 326
 327         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 328         use it for ssat and ssat16.
 329         (print_insn_thumb32): Add handle case for 'D' control code.
 330
 331 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 332             H.J. Lu  <hongjiu.lu@intel.com>
 333
 334         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 335         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 336         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 337         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 338         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 339         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 340         Fill prefix_requirement field.
 341         (struct dis386): Add prefix_requirement field.
 342         (dis386): Fill prefix_requirement field.
 343         (dis386_twobyte): Ditto.
 344         (twobyte_has_mandatory_prefix_: Remove.
 345         (reg_table): Fill prefix_requirement field.
 346         (prefix_table): Ditto.
 347         (x86_64_table): Ditto.
 348         (three_byte_table): Ditto.
 349         (xop_table): Ditto.
 350         (vex_table): Ditto.
 351         (vex_len_table): Ditto.
 352         (vex_w_table): Ditto.
 353         (mod_table): Ditto.
 354         (bad_opcode): Ditto.
 355         (print_insn): Use prefix_requirement.
 356         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 357         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 358         (float_reg): Ditto.
 359
 360 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 361
 362         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 363
 364 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 365
 366         * Makefile.in: Regenerated.
 367
 368 2015-03-25  Anton Blanchard  <anton@samba.org>
 369
 370         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 371         powerpc_opcd_indices and vle_opcd_indices once.
 372
 373 2015-03-25  Anton Blanchard  <anton@samba.org>
 374
 375         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 376
 377 2015-03-24  Terry Guo  <terry.guo@arm.com>
 378
 379         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 380         (opcode16): Likewise.
 381         (coprocessor_opcodes): Replace bit with feature struct.
 382         (neon_opcodes): Likewise.
 383         (arm_opcodes): Likewise.
 384         (thumb_opcodes): Likewise.
 385         (thumb32_opcodes): Likewise.
 386         (print_insn_coprocessor): Likewise.
 387         (print_insn_arm): Likewise.
 388         (select_arm_features): Follow new feature struct.
 389
 390 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 391
 392         * i386-dis.c (rm_table): Add clzero.
 393         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 394         Add CPU_CLZERO_FLAGS.
 395         (cpu_flags): Add CpuCLZERO.
 396         * i386-opc.h: Add CpuCLZERO.
 397         * i386-opc.tbl: Add clzero.
 398         * i386-init.h: Re-generated.
 399         * i386-tbl.h: Re-generated.
 400
 401 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 402
 403         * mips-opc.c (decode_mips_operand): Fix constraint issues
 404         with u and y operands.
 405
 406 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 407
 408         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 409
 410 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 411
 412         * s390-opc.c: Add new IBM z13 instructions.
 413         * s390-opc.txt: Likewise.
 414
 415 2015-03-10  Renlin Li  <renlin.li@arm.com>
 416
 417         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 418         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 419         related alias.
 420         * aarch64-asm-2.c: Regenerate.
 421         * aarch64-dis-2.c: Likewise.
 422         * aarch64-opc-2.c: Likewise.
 423
 424 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 425
 426         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 427
 428 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 429
 430         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 431         arch_sh_up.
 432         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 433         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 434
 435 2015-02-23  Vinay  <Vinay.G@kpit.com>
 436
 437         * rl78-decode.opc (MOV): Added space between two operands for
 438         'mov' instruction in index addressing mode.
 439         * rl78-decode.c: Regenerate.
 440
 441 2015-02-19  Pedro Alves  <palves@redhat.com>
 442
 443         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 444
 445 2015-02-10  Pedro Alves  <palves@redhat.com>
 446             Tom Tromey  <tromey@redhat.com>
 447
 448         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 449         microblaze_and, microblaze_xor.
 450         * microblaze-opc.h (opcodes): Adjust.
 451
 452 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 453
 454         * Makefile.am: Add FT32 files.
 455         * configure.ac: Handle FT32.
 456         * disassemble.c (disassembler): Call print_insn_ft32.
 457         * ft32-dis.c: New file.
 458         * ft32-opc.c: New file.
 459         * Makefile.in: Regenerate.
 460         * configure: Regenerate.
 461         * po/POTFILES.in: Regenerate.
 462
 463 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 464
 465         * nds32-asm.c (keyword_sr): Add new system registers.
 466
 467 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 468
 469         * s390-dis.c (s390_extract_operand): Support vector register
 470         operands.
 471         (s390_print_insn_with_opcode): Support new operands types and add
 472         new handling of optional operands.
 473         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 474         and include opcode/s390.h instead.
 475         (struct op_struct): New field `flags'.
 476         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 477         (dumpTable): Dump flags.
 478         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 479         string.
 480         * s390-opc.c: Add new operands types, instruction formats, and
 481         instruction masks.
 482         (s390_opformats): Add new formats for .insn.
 483         * s390-opc.txt: Add new instructions.
 484
 485 2015-01-01  Alan Modra  <amodra@gmail.com>
 486
 487         Update year range in copyright notice of all files.
 488
 489 For older changes see ChangeLog-2014
 490 \f
 491 Copyright (C) 2015 Free Software Foundation, Inc.
 492
 493 Copying and distribution of this file, with or without modification,
 494 are permitted in any medium without royalty provided the copyright
 495 notice and this notice are preserved.
 496
 497 Local Variables:
 498 mode: change-log
 499 left-margin: 8
 500 fill-column: 74
 501 version-control: never
 502 End: