1 2018-11-06 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
4 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
5 vcvtusi2ss, kmovd): Drop VexW=1.
6 * i386-tbl.h: Re-generate.
8 2018-11-06 Jan Beulich <jbeulich@suse.com>
10 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
11 EVex512, EVexLIG, EVexDYN): New.
12 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
13 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
14 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
15 of EVex=4 (aka EVexLIG).
16 * i386-tbl.h: Re-generate.
18 2018-11-06 Jan Beulich <jbeulich@suse.com>
20 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
21 (vpmaxub): Re-order attributes on AVX512BW flavor.
22 * i386-tbl.h: Re-generate.
24 2018-11-06 Jan Beulich <jbeulich@suse.com>
26 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
27 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
28 Vex=1 on AVX / AVX2 flavors.
29 (vpmaxub): Re-order attributes on AVX512BW flavor.
30 * i386-tbl.h: Re-generate.
32 2018-11-06 Jan Beulich <jbeulich@suse.com>
34 * i386-opc.tbl (VexW0, VexW1): New.
35 (vphadd*, vphsub*): Use VexW0 on XOP variants.
36 * i386-tbl.h: Re-generate.
38 2018-10-22 John Darrington <john@darrington.wattle.id.au>
40 * s12z-dis.c (decode_possible_symbol): Add fallback case.
43 2018-10-19 Tamar Christina <tamar.christina@arm.com>
45 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
46 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
47 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
49 2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
51 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
52 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
54 2018-10-10 Jan Beulich <jbeulich@suse.com>
56 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
58 * i386-opc.h (Size16, Size32, Size64): Delete.
60 (SIZE16, SIZE32, SIZE64): Define.
61 (struct i386_opcode_modifier): Drop size16, size32, and size64.
63 * i386-opc.tbl (Size16, Size32, Size64): Define.
64 * i386-tbl.h: Re-generate.
66 2018-10-09 Sudakshina Das <sudi.das@arm.com>
68 * aarch64-opc.c (operand_general_constraint_met_p): Add
69 SSBS in the check for one-bit immediate.
70 (aarch64_sys_regs): New entry for SSBS.
71 (aarch64_sys_reg_supported_p): New check for above.
72 (aarch64_pstatefields): New entry for SSBS.
73 (aarch64_pstatefield_supported_p): New check for above.
75 2018-10-09 Sudakshina Das <sudi.das@arm.com>
77 * aarch64-opc.c (aarch64_sys_regs): New entries for
78 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
79 (aarch64_sys_reg_supported_p): New checks for above.
81 2018-10-09 Sudakshina Das <sudi.das@arm.com>
83 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
84 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
85 with the hint immediate.
86 * aarch64-opc.c (aarch64_hint_options): New entries for
87 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
88 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
89 while checking for HINT_OPD_F_NOPRINT flag.
90 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
92 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
93 (aarch64_opcode_table): Add entry for BTI.
94 (AARCH64_OPERANDS): Add new description for BTI targets.
95 * aarch64-asm-2.c: Regenerate.
96 * aarch64-dis-2.c: Regenerate.
97 * aarch64-opc-2.c: Regenerate.
99 2018-10-09 Sudakshina Das <sudi.das@arm.com>
101 * aarch64-opc.c (aarch64_sys_regs): New entries for
103 (aarch64_sys_reg_supported_p): New check for above.
105 2018-10-09 Sudakshina Das <sudi.das@arm.com>
107 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
108 (aarch64_sys_ins_reg_supported_p): New check for above.
110 2018-10-09 Sudakshina Das <sudi.das@arm.com>
112 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
113 AARCH64_OPND_SYSREG_SR.
114 * aarch64-opc.c (aarch64_print_operand): Likewise.
115 (aarch64_sys_regs_sr): Define table.
116 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
117 AARCH64_FEATURE_PREDRES.
118 * aarch64-tbl.h (aarch64_feature_predres): New.
119 (PREDRES, PREDRES_INSN): New.
120 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
121 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
122 * aarch64-asm-2.c: Regenerate.
123 * aarch64-dis-2.c: Regenerate.
124 * aarch64-opc-2.c: Regenerate.
126 2018-10-09 Sudakshina Das <sudi.das@arm.com>
128 * aarch64-tbl.h (aarch64_feature_sb): New.
130 (aarch64_opcode_table): Add entry for sb.
131 * aarch64-asm-2.c: Regenerate.
132 * aarch64-dis-2.c: Regenerate.
133 * aarch64-opc-2.c: Regenerate.
135 2018-10-09 Sudakshina Das <sudi.das@arm.com>
137 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
138 (aarch64_feature_frintts): New.
139 (FLAGMANIP, FRINTTS): New.
140 (aarch64_opcode_table): Add entries for xaflag, axflag
141 and frint[32,64][x,z] instructions.
142 * aarch64-asm-2.c: Regenerate.
143 * aarch64-dis-2.c: Regenerate.
144 * aarch64-opc-2.c: Regenerate.
146 2018-10-09 Sudakshina Das <sudi.das@arm.com>
148 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
149 (ARMV8_5, V8_5_INSN): New.
151 2018-10-08 Tamar Christina <tamar.christina@arm.com>
153 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
155 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
157 * i386-dis.c (rm_table): Add enclv.
158 * i386-opc.tbl: Add enclv.
159 * i386-tbl.h: Regenerated.
161 2018-10-05 Sudakshina Das <sudi.das@arm.com>
163 * arm-dis.c (arm_opcodes): Add sb.
164 (thumb32_opcodes): Likewise.
166 2018-10-05 Richard Henderson <rth@twiddle.net>
167 Stafford Horne <shorne@gmail.com>
169 * or1k-desc.c: Regenerate.
170 * or1k-desc.h: Regenerate.
171 * or1k-opc.c: Regenerate.
172 * or1k-opc.h: Regenerate.
173 * or1k-opinst.c: Regenerate.
175 2018-10-05 Richard Henderson <rth@twiddle.net>
177 * or1k-asm.c: Regenerated.
178 * or1k-desc.c: Regenerated.
179 * or1k-desc.h: Regenerated.
180 * or1k-dis.c: Regenerated.
181 * or1k-ibld.c: Regenerated.
182 * or1k-opc.c: Regenerated.
183 * or1k-opc.h: Regenerated.
184 * or1k-opinst.c: Regenerated.
186 2018-10-05 Richard Henderson <rth@twiddle.net>
188 * or1k-asm.c: Regenerate.
190 2018-10-03 Tamar Christina <tamar.christina@arm.com>
192 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
193 * aarch64-dis.c (print_operands): Refactor to take notes.
194 (print_verifier_notes): New.
195 (print_aarch64_insn): Apply constraint verifier.
196 (print_insn_aarch64_word): Update call to print_aarch64_insn.
197 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
199 2018-10-03 Tamar Christina <tamar.christina@arm.com>
201 * aarch64-opc.c (init_insn_block): New.
202 (verify_constraints, aarch64_is_destructive_by_operands): New.
203 * aarch64-opc.h (verify_constraints): New.
205 2018-10-03 Tamar Christina <tamar.christina@arm.com>
207 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
208 * aarch64-opc.c (verify_ldpsw): Update arguments.
210 2018-10-03 Tamar Christina <tamar.christina@arm.com>
212 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
213 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
215 2018-10-03 Tamar Christina <tamar.christina@arm.com>
217 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
218 * aarch64-dis.c (insn_sequence): New.
220 2018-10-03 Tamar Christina <tamar.christina@arm.com>
222 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
223 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
224 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
225 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
228 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
230 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
232 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
233 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
234 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
235 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
236 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
237 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
238 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
240 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
242 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
244 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
246 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
247 are used when extracting signed fields and converting them to
248 potentially 64-bit types.
250 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
252 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
253 * Makefile.in: Re-generate.
254 * aclocal.m4: Re-generate.
255 * configure: Re-generate.
256 * configure.ac: Remove check for -Wno-missing-field-initializers.
257 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
258 (csky_v2_opcodes): Likewise.
260 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
262 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
264 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
266 * nds32-asm.c (operand_fields): Remove the unused fields.
267 (nds32_opcodes): Remove the unused instructions.
268 * nds32-dis.c (nds32_ex9_info): Removed.
269 (nds32_parse_opcode): Updated.
270 (print_insn_nds32): Likewise.
271 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
272 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
273 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
274 build_opcode_hash_table): New functions.
275 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
276 nds32_opcode_table): New.
277 (hw_ktabs): Declare it to a pointer rather than an array.
278 (build_hash_table): Removed.
279 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
280 SYN_ROPT and upadte HW_GPR and HW_INT.
281 * nds32-dis.c (keywords): Remove const.
282 (match_field): New function.
283 (nds32_parse_opcode): Updated.
284 * disassemble.c (disassemble_init_for_target):
285 Add disassemble_init_nds32.
286 * nds32-dis.c (eum map_type): New.
287 (nds32_private_data): Likewise.
288 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
289 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
290 (print_insn_nds32): Updated.
291 * nds32-asm.c (parse_aext_reg): Add new parameter.
292 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
295 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
296 (operand_fields): Add new fields.
297 (nds32_opcodes): Add new instructions.
298 (keyword_aridxi_mx): New keyword.
299 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
301 (ALU2_1, ALU2_2, ALU2_3): New macros.
302 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
304 2018-09-17 Kito Cheng <kito@andestech.com>
306 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
308 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
311 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
312 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
313 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
314 (EVEX_LEN_0F7E_P_1): Likewise.
315 (EVEX_LEN_0F7E_P_2): Likewise.
316 (EVEX_LEN_0FD6_P_2): Likewise.
317 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
318 (EVEX_LEN_TABLE): Likewise.
319 (EVEX_LEN_0F6E_P_2): New enum.
320 (EVEX_LEN_0F7E_P_1): Likewise.
321 (EVEX_LEN_0F7E_P_2): Likewise.
322 (EVEX_LEN_0FD6_P_2): Likewise.
323 (evex_len_table): New.
324 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
325 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
326 * i386-tbl.h: Regenerated.
328 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
331 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
332 VEX_LEN_0F7E_P_2 entries.
333 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
334 * i386-tbl.h: Regenerated.
336 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
338 * i386-dis.c (VZERO_Fixup): Removed.
340 (VEX_LEN_0F10_P_1): Likewise.
341 (VEX_LEN_0F10_P_3): Likewise.
342 (VEX_LEN_0F11_P_1): Likewise.
343 (VEX_LEN_0F11_P_3): Likewise.
344 (VEX_LEN_0F2E_P_0): Likewise.
345 (VEX_LEN_0F2E_P_2): Likewise.
346 (VEX_LEN_0F2F_P_0): Likewise.
347 (VEX_LEN_0F2F_P_2): Likewise.
348 (VEX_LEN_0F51_P_1): Likewise.
349 (VEX_LEN_0F51_P_3): Likewise.
350 (VEX_LEN_0F52_P_1): Likewise.
351 (VEX_LEN_0F53_P_1): Likewise.
352 (VEX_LEN_0F58_P_1): Likewise.
353 (VEX_LEN_0F58_P_3): Likewise.
354 (VEX_LEN_0F59_P_1): Likewise.
355 (VEX_LEN_0F59_P_3): Likewise.
356 (VEX_LEN_0F5A_P_1): Likewise.
357 (VEX_LEN_0F5A_P_3): Likewise.
358 (VEX_LEN_0F5C_P_1): Likewise.
359 (VEX_LEN_0F5C_P_3): Likewise.
360 (VEX_LEN_0F5D_P_1): Likewise.
361 (VEX_LEN_0F5D_P_3): Likewise.
362 (VEX_LEN_0F5E_P_1): Likewise.
363 (VEX_LEN_0F5E_P_3): Likewise.
364 (VEX_LEN_0F5F_P_1): Likewise.
365 (VEX_LEN_0F5F_P_3): Likewise.
366 (VEX_LEN_0FC2_P_1): Likewise.
367 (VEX_LEN_0FC2_P_3): Likewise.
368 (VEX_LEN_0F3A0A_P_2): Likewise.
369 (VEX_LEN_0F3A0B_P_2): Likewise.
370 (VEX_W_0F10_P_0): Likewise.
371 (VEX_W_0F10_P_1): Likewise.
372 (VEX_W_0F10_P_2): Likewise.
373 (VEX_W_0F10_P_3): Likewise.
374 (VEX_W_0F11_P_0): Likewise.
375 (VEX_W_0F11_P_1): Likewise.
376 (VEX_W_0F11_P_2): Likewise.
377 (VEX_W_0F11_P_3): Likewise.
378 (VEX_W_0F12_P_0_M_0): Likewise.
379 (VEX_W_0F12_P_0_M_1): Likewise.
380 (VEX_W_0F12_P_1): Likewise.
381 (VEX_W_0F12_P_2): Likewise.
382 (VEX_W_0F12_P_3): Likewise.
383 (VEX_W_0F13_M_0): Likewise.
384 (VEX_W_0F14): Likewise.
385 (VEX_W_0F15): Likewise.
386 (VEX_W_0F16_P_0_M_0): Likewise.
387 (VEX_W_0F16_P_0_M_1): Likewise.
388 (VEX_W_0F16_P_1): Likewise.
389 (VEX_W_0F16_P_2): Likewise.
390 (VEX_W_0F17_M_0): Likewise.
391 (VEX_W_0F28): Likewise.
392 (VEX_W_0F29): Likewise.
393 (VEX_W_0F2B_M_0): Likewise.
394 (VEX_W_0F2E_P_0): Likewise.
395 (VEX_W_0F2E_P_2): Likewise.
396 (VEX_W_0F2F_P_0): Likewise.
397 (VEX_W_0F2F_P_2): Likewise.
398 (VEX_W_0F50_M_0): Likewise.
399 (VEX_W_0F51_P_0): Likewise.
400 (VEX_W_0F51_P_1): Likewise.
401 (VEX_W_0F51_P_2): Likewise.
402 (VEX_W_0F51_P_3): Likewise.
403 (VEX_W_0F52_P_0): Likewise.
404 (VEX_W_0F52_P_1): Likewise.
405 (VEX_W_0F53_P_0): Likewise.
406 (VEX_W_0F53_P_1): Likewise.
407 (VEX_W_0F58_P_0): Likewise.
408 (VEX_W_0F58_P_1): Likewise.
409 (VEX_W_0F58_P_2): Likewise.
410 (VEX_W_0F58_P_3): Likewise.
411 (VEX_W_0F59_P_0): Likewise.
412 (VEX_W_0F59_P_1): Likewise.
413 (VEX_W_0F59_P_2): Likewise.
414 (VEX_W_0F59_P_3): Likewise.
415 (VEX_W_0F5A_P_0): Likewise.
416 (VEX_W_0F5A_P_1): Likewise.
417 (VEX_W_0F5A_P_3): Likewise.
418 (VEX_W_0F5B_P_0): Likewise.
419 (VEX_W_0F5B_P_1): Likewise.
420 (VEX_W_0F5B_P_2): Likewise.
421 (VEX_W_0F5C_P_0): Likewise.
422 (VEX_W_0F5C_P_1): Likewise.
423 (VEX_W_0F5C_P_2): Likewise.
424 (VEX_W_0F5C_P_3): Likewise.
425 (VEX_W_0F5D_P_0): Likewise.
426 (VEX_W_0F5D_P_1): Likewise.
427 (VEX_W_0F5D_P_2): Likewise.
428 (VEX_W_0F5D_P_3): Likewise.
429 (VEX_W_0F5E_P_0): Likewise.
430 (VEX_W_0F5E_P_1): Likewise.
431 (VEX_W_0F5E_P_2): Likewise.
432 (VEX_W_0F5E_P_3): Likewise.
433 (VEX_W_0F5F_P_0): Likewise.
434 (VEX_W_0F5F_P_1): Likewise.
435 (VEX_W_0F5F_P_2): Likewise.
436 (VEX_W_0F5F_P_3): Likewise.
437 (VEX_W_0F60_P_2): Likewise.
438 (VEX_W_0F61_P_2): Likewise.
439 (VEX_W_0F62_P_2): Likewise.
440 (VEX_W_0F63_P_2): Likewise.
441 (VEX_W_0F64_P_2): Likewise.
442 (VEX_W_0F65_P_2): Likewise.
443 (VEX_W_0F66_P_2): Likewise.
444 (VEX_W_0F67_P_2): Likewise.
445 (VEX_W_0F68_P_2): Likewise.
446 (VEX_W_0F69_P_2): Likewise.
447 (VEX_W_0F6A_P_2): Likewise.
448 (VEX_W_0F6B_P_2): Likewise.
449 (VEX_W_0F6C_P_2): Likewise.
450 (VEX_W_0F6D_P_2): Likewise.
451 (VEX_W_0F6F_P_1): Likewise.
452 (VEX_W_0F6F_P_2): Likewise.
453 (VEX_W_0F70_P_1): Likewise.
454 (VEX_W_0F70_P_2): Likewise.
455 (VEX_W_0F70_P_3): Likewise.
456 (VEX_W_0F71_R_2_P_2): Likewise.
457 (VEX_W_0F71_R_4_P_2): Likewise.
458 (VEX_W_0F71_R_6_P_2): Likewise.
459 (VEX_W_0F72_R_2_P_2): Likewise.
460 (VEX_W_0F72_R_4_P_2): Likewise.
461 (VEX_W_0F72_R_6_P_2): Likewise.
462 (VEX_W_0F73_R_2_P_2): Likewise.
463 (VEX_W_0F73_R_3_P_2): Likewise.
464 (VEX_W_0F73_R_6_P_2): Likewise.
465 (VEX_W_0F73_R_7_P_2): Likewise.
466 (VEX_W_0F74_P_2): Likewise.
467 (VEX_W_0F75_P_2): Likewise.
468 (VEX_W_0F76_P_2): Likewise.
469 (VEX_W_0F77_P_0): Likewise.
470 (VEX_W_0F7C_P_2): Likewise.
471 (VEX_W_0F7C_P_3): Likewise.
472 (VEX_W_0F7D_P_2): Likewise.
473 (VEX_W_0F7D_P_3): Likewise.
474 (VEX_W_0F7E_P_1): Likewise.
475 (VEX_W_0F7F_P_1): Likewise.
476 (VEX_W_0F7F_P_2): Likewise.
477 (VEX_W_0FAE_R_2_M_0): Likewise.
478 (VEX_W_0FAE_R_3_M_0): Likewise.
479 (VEX_W_0FC2_P_0): Likewise.
480 (VEX_W_0FC2_P_1): Likewise.
481 (VEX_W_0FC2_P_2): Likewise.
482 (VEX_W_0FC2_P_3): Likewise.
483 (VEX_W_0FD0_P_2): Likewise.
484 (VEX_W_0FD0_P_3): Likewise.
485 (VEX_W_0FD1_P_2): Likewise.
486 (VEX_W_0FD2_P_2): Likewise.
487 (VEX_W_0FD3_P_2): Likewise.
488 (VEX_W_0FD4_P_2): Likewise.
489 (VEX_W_0FD5_P_2): Likewise.
490 (VEX_W_0FD6_P_2): Likewise.
491 (VEX_W_0FD7_P_2_M_1): Likewise.
492 (VEX_W_0FD8_P_2): Likewise.
493 (VEX_W_0FD9_P_2): Likewise.
494 (VEX_W_0FDA_P_2): Likewise.
495 (VEX_W_0FDB_P_2): Likewise.
496 (VEX_W_0FDC_P_2): Likewise.
497 (VEX_W_0FDD_P_2): Likewise.
498 (VEX_W_0FDE_P_2): Likewise.
499 (VEX_W_0FDF_P_2): Likewise.
500 (VEX_W_0FE0_P_2): Likewise.
501 (VEX_W_0FE1_P_2): Likewise.
502 (VEX_W_0FE2_P_2): Likewise.
503 (VEX_W_0FE3_P_2): Likewise.
504 (VEX_W_0FE4_P_2): Likewise.
505 (VEX_W_0FE5_P_2): Likewise.
506 (VEX_W_0FE6_P_1): Likewise.
507 (VEX_W_0FE6_P_2): Likewise.
508 (VEX_W_0FE6_P_3): Likewise.
509 (VEX_W_0FE7_P_2_M_0): Likewise.
510 (VEX_W_0FE8_P_2): Likewise.
511 (VEX_W_0FE9_P_2): Likewise.
512 (VEX_W_0FEA_P_2): Likewise.
513 (VEX_W_0FEB_P_2): Likewise.
514 (VEX_W_0FEC_P_2): Likewise.
515 (VEX_W_0FED_P_2): Likewise.
516 (VEX_W_0FEE_P_2): Likewise.
517 (VEX_W_0FEF_P_2): Likewise.
518 (VEX_W_0FF0_P_3_M_0): Likewise.
519 (VEX_W_0FF1_P_2): Likewise.
520 (VEX_W_0FF2_P_2): Likewise.
521 (VEX_W_0FF3_P_2): Likewise.
522 (VEX_W_0FF4_P_2): Likewise.
523 (VEX_W_0FF5_P_2): Likewise.
524 (VEX_W_0FF6_P_2): Likewise.
525 (VEX_W_0FF7_P_2): Likewise.
526 (VEX_W_0FF8_P_2): Likewise.
527 (VEX_W_0FF9_P_2): Likewise.
528 (VEX_W_0FFA_P_2): Likewise.
529 (VEX_W_0FFB_P_2): Likewise.
530 (VEX_W_0FFC_P_2): Likewise.
531 (VEX_W_0FFD_P_2): Likewise.
532 (VEX_W_0FFE_P_2): Likewise.
533 (VEX_W_0F3800_P_2): Likewise.
534 (VEX_W_0F3801_P_2): Likewise.
535 (VEX_W_0F3802_P_2): Likewise.
536 (VEX_W_0F3803_P_2): Likewise.
537 (VEX_W_0F3804_P_2): Likewise.
538 (VEX_W_0F3805_P_2): Likewise.
539 (VEX_W_0F3806_P_2): Likewise.
540 (VEX_W_0F3807_P_2): Likewise.
541 (VEX_W_0F3808_P_2): Likewise.
542 (VEX_W_0F3809_P_2): Likewise.
543 (VEX_W_0F380A_P_2): Likewise.
544 (VEX_W_0F380B_P_2): Likewise.
545 (VEX_W_0F3817_P_2): Likewise.
546 (VEX_W_0F381C_P_2): Likewise.
547 (VEX_W_0F381D_P_2): Likewise.
548 (VEX_W_0F381E_P_2): Likewise.
549 (VEX_W_0F3820_P_2): Likewise.
550 (VEX_W_0F3821_P_2): Likewise.
551 (VEX_W_0F3822_P_2): Likewise.
552 (VEX_W_0F3823_P_2): Likewise.
553 (VEX_W_0F3824_P_2): Likewise.
554 (VEX_W_0F3825_P_2): Likewise.
555 (VEX_W_0F3828_P_2): Likewise.
556 (VEX_W_0F3829_P_2): Likewise.
557 (VEX_W_0F382A_P_2_M_0): Likewise.
558 (VEX_W_0F382B_P_2): Likewise.
559 (VEX_W_0F3830_P_2): Likewise.
560 (VEX_W_0F3831_P_2): Likewise.
561 (VEX_W_0F3832_P_2): Likewise.
562 (VEX_W_0F3833_P_2): Likewise.
563 (VEX_W_0F3834_P_2): Likewise.
564 (VEX_W_0F3835_P_2): Likewise.
565 (VEX_W_0F3837_P_2): Likewise.
566 (VEX_W_0F3838_P_2): Likewise.
567 (VEX_W_0F3839_P_2): Likewise.
568 (VEX_W_0F383A_P_2): Likewise.
569 (VEX_W_0F383B_P_2): Likewise.
570 (VEX_W_0F383C_P_2): Likewise.
571 (VEX_W_0F383D_P_2): Likewise.
572 (VEX_W_0F383E_P_2): Likewise.
573 (VEX_W_0F383F_P_2): Likewise.
574 (VEX_W_0F3840_P_2): Likewise.
575 (VEX_W_0F3841_P_2): Likewise.
576 (VEX_W_0F38DB_P_2): Likewise.
577 (VEX_W_0F3A08_P_2): Likewise.
578 (VEX_W_0F3A09_P_2): Likewise.
579 (VEX_W_0F3A0A_P_2): Likewise.
580 (VEX_W_0F3A0B_P_2): Likewise.
581 (VEX_W_0F3A0C_P_2): Likewise.
582 (VEX_W_0F3A0D_P_2): Likewise.
583 (VEX_W_0F3A0E_P_2): Likewise.
584 (VEX_W_0F3A0F_P_2): Likewise.
585 (VEX_W_0F3A21_P_2): Likewise.
586 (VEX_W_0F3A40_P_2): Likewise.
587 (VEX_W_0F3A41_P_2): Likewise.
588 (VEX_W_0F3A42_P_2): Likewise.
589 (VEX_W_0F3A62_P_2): Likewise.
590 (VEX_W_0F3A63_P_2): Likewise.
591 (VEX_W_0F3ADF_P_2): Likewise.
592 (VEX_LEN_0F77_P_0): New.
593 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
594 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
595 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
596 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
597 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
598 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
599 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
600 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
601 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
602 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
603 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
604 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
605 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
606 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
607 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
608 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
609 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
610 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
611 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
612 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
613 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
614 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
615 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
616 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
617 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
618 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
619 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
620 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
621 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
622 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
623 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
624 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
625 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
626 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
627 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
628 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
629 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
630 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
631 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
632 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
633 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
634 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
635 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
636 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
637 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
638 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
639 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
640 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
641 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
642 (vex_table): Update VEX 0F28 and 0F29 entries.
643 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
644 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
645 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
646 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
647 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
648 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
649 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
650 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
651 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
652 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
653 VEX_LEN_0F3A0B_P_2 entries.
654 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
655 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
656 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
657 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
658 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
659 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
660 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
661 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
662 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
663 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
664 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
665 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
666 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
667 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
668 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
669 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
670 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
671 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
672 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
673 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
674 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
675 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
676 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
677 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
678 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
679 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
680 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
681 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
682 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
683 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
684 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
685 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
686 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
687 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
688 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
689 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
690 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
691 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
692 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
693 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
694 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
695 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
696 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
697 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
698 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
699 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
700 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
701 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
702 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
703 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
704 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
705 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
706 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
707 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
708 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
709 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
710 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
711 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
712 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
713 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
714 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
715 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
716 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
717 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
718 VEX_W_0F3ADF_P_2 entries.
719 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
720 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
721 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
723 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
725 * i386-opc.tbl (VexWIG): New.
726 Replace VexW=3 with VexWIG.
728 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
730 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
731 * i386-tbl.h: Regenerated.
733 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
736 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
737 VEX_LEN_0FD6_P_2 entries.
738 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
739 * i386-tbl.h: Regenerated.
741 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
744 * i386-opc.h (VEXWIG): New.
745 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
746 * i386-tbl.h: Regenerated.
748 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
751 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
752 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
753 * i386-dis.c (EXxEVexR64): New.
754 (evex_rounding_64_mode): Likewise.
755 (OP_Rounding): Handle evex_rounding_64_mode.
757 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
760 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
761 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
762 * i386-dis.c (Edqa): New.
763 (dqa_mode): Likewise.
764 (intel_operand_size): Handle dqa_mode as m_mode.
765 (OP_E_register): Handle dqa_mode as dq_mode.
766 (OP_E_memory): Set shift for dqa_mode based on address_mode.
768 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
770 * i386-dis.c (OP_E_memory): Reformat.
772 2018-09-14 Jan Beulich <jbeulich@suse.com>
774 * i386-opc.tbl (crc32): Fold byte and word forms.
775 * i386-tbl.h: Re-generate.
777 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
779 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
780 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
781 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
782 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
783 * i386-tbl.h: Regenerated.
785 2018-09-13 Jan Beulich <jbeulich@suse.com>
787 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
789 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
790 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
791 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
792 * i386-tbl.h: Re-generate.
794 2018-09-13 Jan Beulich <jbeulich@suse.com>
796 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
798 * i386-tbl.h: Re-generate.
800 2018-09-13 Jan Beulich <jbeulich@suse.com>
802 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
804 * i386-tbl.h: Re-generate.
806 2018-09-13 Jan Beulich <jbeulich@suse.com>
808 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
810 * i386-tbl.h: Re-generate.
812 2018-09-13 Jan Beulich <jbeulich@suse.com>
814 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
816 * i386-tbl.h: Re-generate.
818 2018-09-13 Jan Beulich <jbeulich@suse.com>
820 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
822 * i386-tbl.h: Re-generate.
824 2018-09-13 Jan Beulich <jbeulich@suse.com>
826 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
828 * i386-tbl.h: Re-generate.
830 2018-09-13 Jan Beulich <jbeulich@suse.com>
832 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
833 * i386-tbl.h: Re-generate.
835 2018-09-13 Jan Beulich <jbeulich@suse.com>
837 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
838 * i386-tbl.h: Re-generate.
840 2018-09-13 Jan Beulich <jbeulich@suse.com>
842 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
844 * i386-tbl.h: Re-generate.
846 2018-09-13 Jan Beulich <jbeulich@suse.com>
848 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
850 * i386-tbl.h: Re-generate.
852 2018-09-13 Jan Beulich <jbeulich@suse.com>
854 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
855 * i386-tbl.h: Re-generate.
857 2018-09-13 Jan Beulich <jbeulich@suse.com>
859 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
860 * i386-tbl.h: Re-generate.
862 2018-09-13 Jan Beulich <jbeulich@suse.com>
864 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
865 * i386-tbl.h: Re-generate.
867 2018-09-13 Jan Beulich <jbeulich@suse.com>
869 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
871 * i386-tbl.h: Re-generate.
873 2018-09-13 Jan Beulich <jbeulich@suse.com>
875 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
877 * i386-tbl.h: Re-generate.
879 2018-09-13 Jan Beulich <jbeulich@suse.com>
881 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
883 * i386-tbl.h: Re-generate.
885 2018-09-13 Jan Beulich <jbeulich@suse.com>
887 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
888 * i386-tbl.h: Re-generate.
890 2018-09-13 Jan Beulich <jbeulich@suse.com>
892 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
893 * i386-tbl.h: Re-generate.
895 2018-09-13 Jan Beulich <jbeulich@suse.com>
897 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
898 * i386-tbl.h: Re-generate.
900 2018-09-13 Jan Beulich <jbeulich@suse.com>
902 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
903 (vpbroadcastw, rdpid): Drop NoRex64.
904 * i386-tbl.h: Re-generate.
906 2018-09-13 Jan Beulich <jbeulich@suse.com>
908 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
909 store templates, adding D.
910 * i386-tbl.h: Re-generate.
912 2018-09-13 Jan Beulich <jbeulich@suse.com>
914 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
915 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
916 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
917 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
918 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
919 Fold load and store templates where possible, adding D. Drop
920 IgnoreSize where it was pointlessly present. Drop redundant
922 * i386-tbl.h: Re-generate.
924 2018-09-13 Jan Beulich <jbeulich@suse.com>
926 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
927 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
928 (intel_operand_size): Handle v_bndmk_mode.
929 (OP_E_memory): Likewise. Produce (bad) when also riprel.
931 2018-09-08 John Darrington <john@darrington.wattle.id.au>
933 * disassemble.c (ARCH_s12z): Define if ARCH_all.
935 2018-08-31 Kito Cheng <kito@andestech.com>
937 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
938 compressed floating point instructions.
940 2018-08-30 Kito Cheng <kito@andestech.com>
942 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
943 riscv_opcode.xlen_requirement.
944 * riscv-opc.c (riscv_opcodes): Update for struct change.
946 2018-08-29 Martin Aberg <maberg@gaisler.com>
948 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
949 psr (PWRPSR) instruction.
951 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
953 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
955 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
957 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
959 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
961 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
962 loongson3a as an alias of gs464 for compatibility.
963 * mips-opc.c (mips_opcodes): Change Comments.
965 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
967 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
969 (print_mips_disassembler_options): Document -M loongson-ext.
970 * mips-opc.c (LEXT2): New macro.
971 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
973 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
975 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
977 (parse_mips_ase_option): Handle -M loongson-ext option.
978 (print_mips_disassembler_options): Document -M loongson-ext.
979 * mips-opc.c (IL3A): Delete.
980 * mips-opc.c (LEXT): New macro.
981 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
984 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
986 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
988 (parse_mips_ase_option): Handle -M loongson-cam option.
989 (print_mips_disassembler_options): Document -M loongson-cam.
990 * mips-opc.c (LCAM): New macro.
991 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
994 2018-08-21 Alan Modra <amodra@gmail.com>
996 * ppc-dis.c (operand_value_powerpc): Init "invalid".
997 (skip_optional_operands): Count optional operands, and update
998 ppc_optional_operand_value call.
999 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1000 (extract_vlensi): Likewise.
1001 (extract_fxm): Return default value for missing optional operand.
1002 (extract_ls, extract_raq, extract_tbr): Likewise.
1003 (insert_sxl, extract_sxl): New functions.
1004 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1005 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1006 flag and extra entry.
1007 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1010 2018-08-20 Alan Modra <amodra@gmail.com>
1012 * sh-opc.h (MASK): Simplify.
1014 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1016 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1017 BM_RESERVED0 or BM_RESERVED1
1018 (bm_rel_decode, bm_n_bytes): Ditto.
1020 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1024 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1026 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1027 address with the addr32 prefix and without base nor index
1030 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1032 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1033 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1034 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1035 (cpu_flags): Add CpuCMOV and CpuFXSR.
1036 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1037 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1038 * i386-init.h: Regenerated.
1039 * i386-tbl.h: Likewise.
1041 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1043 * arc-regs.h: Update auxiliary registers.
1045 2018-08-06 Jan Beulich <jbeulich@suse.com>
1047 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1048 (RegIP, RegIZ): Define.
1049 * i386-reg.tbl: Adjust comments.
1050 (rip): Use Qword instead of BaseIndex. Use RegIP.
1051 (eip): Use Dword instead of BaseIndex. Use RegIP.
1052 (riz): Add Qword. Use RegIZ.
1053 (eiz): Add Dword. Use RegIZ.
1054 * i386-tbl.h: Re-generate.
1056 2018-08-03 Jan Beulich <jbeulich@suse.com>
1058 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1059 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1060 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1061 * i386-tbl.h: Re-generate.
1063 2018-08-03 Jan Beulich <jbeulich@suse.com>
1065 * i386-gen.c (operand_types): Remove Mem field.
1066 * i386-opc.h (union i386_operand_type): Remove mem field.
1067 * i386-init.h, i386-tbl.h: Re-generate.
1069 2018-08-01 Alan Modra <amodra@gmail.com>
1071 * po/POTFILES.in: Regenerate.
1073 2018-07-31 Nick Clifton <nickc@redhat.com>
1075 * po/sv.po: Updated Swedish translation.
1077 2018-07-31 Jan Beulich <jbeulich@suse.com>
1079 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1080 * i386-init.h, i386-tbl.h: Re-generate.
1082 2018-07-31 Jan Beulich <jbeulich@suse.com>
1084 * i386-opc.h (ZEROING_MASKING) Rename to ...
1085 (DYNAMIC_MASKING): ... this. Adjust comment.
1086 * i386-opc.tbl (MaskingMorZ): Define.
1087 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1088 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1089 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1090 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1091 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1092 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1093 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1094 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1095 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1097 2018-07-31 Jan Beulich <jbeulich@suse.com>
1099 * i386-opc.tbl: Use element rather than vector size for AVX512*
1100 scatter/gather insns.
1101 * i386-tbl.h: Re-generate.
1103 2018-07-31 Jan Beulich <jbeulich@suse.com>
1105 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1106 (cpu_flags): Drop CpuVREX.
1107 * i386-opc.h (CpuVREX): Delete.
1108 (union i386_cpu_flags): Remove cpuvrex.
1109 * i386-init.h, i386-tbl.h: Re-generate.
1111 2018-07-30 Jim Wilson <jimw@sifive.com>
1113 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1115 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1117 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1119 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1120 * Makefile.in: Regenerated.
1121 * configure.ac: Add C-SKY.
1122 * configure: Regenerated.
1123 * csky-dis.c: New file.
1124 * csky-opc.h: New file.
1125 * disassemble.c (ARCH_csky): Define.
1126 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1127 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1129 2018-07-27 Alan Modra <amodra@gmail.com>
1131 * ppc-opc.c (insert_sprbat): Correct function parameter and
1133 (extract_sprbat): Likewise, variable too.
1135 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1136 Alan Modra <amodra@gmail.com>
1138 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1139 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1140 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1141 support disjointed BAT.
1142 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1143 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1144 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1146 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1147 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1149 * i386-gen.c (adjust_broadcast_modifier): New function.
1150 (process_i386_opcode_modifier): Add an argument for operands.
1151 Adjust the Broadcast value based on operands.
1152 (output_i386_opcode): Pass operand_types to
1153 process_i386_opcode_modifier.
1154 (process_i386_opcodes): Pass NULL as operands to
1155 process_i386_opcode_modifier.
1156 * i386-opc.h (BYTE_BROADCAST): New.
1157 (WORD_BROADCAST): Likewise.
1158 (DWORD_BROADCAST): Likewise.
1159 (QWORD_BROADCAST): Likewise.
1160 (i386_opcode_modifier): Expand broadcast to 3 bits.
1161 * i386-tbl.h: Regenerated.
1163 2018-07-24 Alan Modra <amodra@gmail.com>
1166 * or1k-desc.h: Regenerate.
1168 2018-07-24 Jan Beulich <jbeulich@suse.com>
1170 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1171 vcvtusi2ss, and vcvtusi2sd.
1172 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1173 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1174 * i386-tbl.h: Re-generate.
1176 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1178 * arc-opc.c (extract_w6): Fix extending the sign.
1180 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1182 * arc-tbl.h (vewt): Allow it for ARC EM family.
1184 2018-07-23 Alan Modra <amodra@gmail.com>
1187 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1188 opcode variants for mtspr/mfspr encodings.
1190 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1191 Maciej W. Rozycki <macro@mips.com>
1193 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1194 loongson3a descriptors.
1195 (parse_mips_ase_option): Handle -M loongson-mmi option.
1196 (print_mips_disassembler_options): Document -M loongson-mmi.
1197 * mips-opc.c (LMMI): New macro.
1198 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1201 2018-07-19 Jan Beulich <jbeulich@suse.com>
1203 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1204 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1205 IgnoreSize and [XYZ]MMword where applicable.
1206 * i386-tbl.h: Re-generate.
1208 2018-07-19 Jan Beulich <jbeulich@suse.com>
1210 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1211 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1212 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1213 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1214 * i386-tbl.h: Re-generate.
1216 2018-07-19 Jan Beulich <jbeulich@suse.com>
1218 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1219 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1220 VPCLMULQDQ templates into their respective AVX512VL counterparts
1221 where possible, using Disp8ShiftVL and CheckRegSize instead of
1222 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1223 * i386-tbl.h: Re-generate.
1225 2018-07-19 Jan Beulich <jbeulich@suse.com>
1227 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1228 AVX512VL counterparts where possible, using Disp8ShiftVL and
1229 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1230 IgnoreSize) as appropriate.
1231 * i386-tbl.h: Re-generate.
1233 2018-07-19 Jan Beulich <jbeulich@suse.com>
1235 * i386-opc.tbl: Fold AVX512BW templates into their respective
1236 AVX512VL counterparts where possible, using Disp8ShiftVL and
1237 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1238 IgnoreSize) as appropriate.
1239 * i386-tbl.h: Re-generate.
1241 2018-07-19 Jan Beulich <jbeulich@suse.com>
1243 * i386-opc.tbl: Fold AVX512CD templates into their respective
1244 AVX512VL counterparts where possible, using Disp8ShiftVL and
1245 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1246 IgnoreSize) as appropriate.
1247 * i386-tbl.h: Re-generate.
1249 2018-07-19 Jan Beulich <jbeulich@suse.com>
1251 * i386-opc.h (DISP8_SHIFT_VL): New.
1252 * i386-opc.tbl (Disp8ShiftVL): Define.
1253 (various): Fold AVX512VL templates into their respective
1254 AVX512F counterparts where possible, using Disp8ShiftVL and
1255 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1256 IgnoreSize) as appropriate.
1257 * i386-tbl.h: Re-generate.
1259 2018-07-19 Jan Beulich <jbeulich@suse.com>
1261 * Makefile.am: Change dependencies and rule for
1262 $(srcdir)/i386-init.h.
1263 * Makefile.in: Re-generate.
1264 * i386-gen.c (process_i386_opcodes): New local variable
1265 "marker". Drop opening of input file. Recognize marker and line
1267 * i386-opc.tbl (OPCODE_I386_H): Define.
1268 (i386-opc.h): Include it.
1271 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1274 * i386-opc.h (Byte): Update comments.
1280 (Xmmword): Likewise.
1281 (Ymmword): Likewise.
1282 (Zmmword): Likewise.
1283 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1285 * i386-tbl.h: Regenerated.
1287 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1289 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1290 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1291 * aarch64-asm-2.c: Regenerate.
1292 * aarch64-dis-2.c: Regenerate.
1293 * aarch64-opc-2.c: Regenerate.
1295 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1298 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1299 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1300 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1301 sqdmulh, sqrdmulh): Use Em16.
1303 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1305 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1306 csdb together with them.
1307 (thumb32_opcodes): Likewise.
1309 2018-07-11 Jan Beulich <jbeulich@suse.com>
1311 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1312 requiring 32-bit registers as operands 2 and 3. Improve
1314 (mwait, mwaitx): Fold templates. Improve comments.
1315 OPERAND_TYPE_INOUTPORTREG.
1316 * i386-tbl.h: Re-generate.
1318 2018-07-11 Jan Beulich <jbeulich@suse.com>
1320 * i386-gen.c (operand_type_init): Remove
1321 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1322 OPERAND_TYPE_INOUTPORTREG.
1323 * i386-init.h: Re-generate.
1325 2018-07-11 Jan Beulich <jbeulich@suse.com>
1327 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1328 (wrssq, wrussq): Add Qword.
1329 * i386-tbl.h: Re-generate.
1331 2018-07-11 Jan Beulich <jbeulich@suse.com>
1333 * i386-opc.h: Rename OTMax to OTNum.
1334 (OTNumOfUints): Adjust calculation.
1335 (OTUnused): Directly alias to OTNum.
1337 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1339 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1341 (lea_reg_xys): Likewise.
1342 (print_insn_loop_primitive): Rename `reg' local variable to
1345 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1348 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1350 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1353 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1354 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1356 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1359 * mips-dis.c (mips_option_arg_t): New enumeration.
1360 (mips_options): New variable.
1361 (disassembler_options_mips): New function.
1362 (print_mips_disassembler_options): Reimplement in terms of
1363 `disassembler_options_mips'.
1364 * arm-dis.c (disassembler_options_arm): Adapt to using the
1365 `disasm_options_and_args_t' structure.
1366 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1367 * s390-dis.c (disassembler_options_s390): Likewise.
1369 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1371 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1373 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1374 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1375 * testsuite/ld-arm/tls-longplt.d: Likewise.
1377 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1380 * aarch64-asm-2.c: Regenerate.
1381 * aarch64-dis-2.c: Likewise.
1382 * aarch64-opc-2.c: Likewise.
1383 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1384 * aarch64-opc.c (operand_general_constraint_met_p,
1385 aarch64_print_operand): Likewise.
1386 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1387 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1389 (AARCH64_OPERANDS): Add Em2.
1391 2018-06-26 Nick Clifton <nickc@redhat.com>
1393 * po/uk.po: Updated Ukranian translation.
1394 * po/de.po: Updated German translation.
1395 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1397 2018-06-26 Nick Clifton <nickc@redhat.com>
1399 * nfp-dis.c: Fix spelling mistake.
1401 2018-06-24 Nick Clifton <nickc@redhat.com>
1403 * configure: Regenerate.
1404 * po/opcodes.pot: Regenerate.
1406 2018-06-24 Nick Clifton <nickc@redhat.com>
1408 2.31 branch created.
1410 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1412 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1413 * aarch64-asm-2.c: Regenerate.
1414 * aarch64-dis-2.c: Likewise.
1416 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1418 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1419 `-M ginv' option description.
1421 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1424 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1427 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1429 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1430 * configure.ac: Remove AC_PREREQ.
1431 * Makefile.in: Re-generate.
1432 * aclocal.m4: Re-generate.
1433 * configure: Re-generate.
1435 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1437 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1438 mips64r6 descriptors.
1439 (parse_mips_ase_option): Handle -Mginv option.
1440 (print_mips_disassembler_options): Document -Mginv.
1441 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1443 (mips_opcodes): Define ginvi and ginvt.
1445 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1446 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1448 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1449 * mips-opc.c (CRC, CRC64): New macros.
1450 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1451 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1454 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1457 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1458 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1460 2018-06-06 Alan Modra <amodra@gmail.com>
1462 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1463 setjmp. Move init for some other vars later too.
1465 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1467 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1468 (dis_private): Add new fields for property section tracking.
1469 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1470 (xtensa_instruction_fits): New functions.
1471 (fetch_data): Bump minimal fetch size to 4.
1472 (print_insn_xtensa): Make struct dis_private static.
1473 Load and prepare property table on section change.
1474 Don't disassemble literals. Don't disassemble instructions that
1475 cross property table boundaries.
1477 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1479 * configure: Regenerated.
1481 2018-06-01 Jan Beulich <jbeulich@suse.com>
1483 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1484 * i386-tbl.h: Re-generate.
1486 2018-06-01 Jan Beulich <jbeulich@suse.com>
1488 * i386-opc.tbl (sldt, str): Add NoRex64.
1489 * i386-tbl.h: Re-generate.
1491 2018-06-01 Jan Beulich <jbeulich@suse.com>
1493 * i386-opc.tbl (invpcid): Add Oword.
1494 * i386-tbl.h: Re-generate.
1496 2018-06-01 Alan Modra <amodra@gmail.com>
1498 * sysdep.h (_bfd_error_handler): Don't declare.
1499 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1500 * rl78-decode.opc: Likewise.
1501 * msp430-decode.c: Regenerate.
1502 * rl78-decode.c: Regenerate.
1504 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1506 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1507 * i386-init.h : Regenerated.
1509 2018-05-25 Alan Modra <amodra@gmail.com>
1511 * Makefile.in: Regenerate.
1512 * po/POTFILES.in: Regenerate.
1514 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1516 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1517 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1518 (insert_bab, extract_bab, insert_btab, extract_btab,
1519 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1520 (BAT, BBA VBA RBS XB6S): Delete macros.
1521 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1522 (BB, BD, RBX, XC6): Update for new macros.
1523 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1524 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1525 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1526 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1528 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1530 * Makefile.am: Add support for s12z architecture.
1531 * configure.ac: Likewise.
1532 * disassemble.c: Likewise.
1533 * disassemble.h: Likewise.
1534 * Makefile.in: Regenerate.
1535 * configure: Regenerate.
1536 * s12z-dis.c: New file.
1539 2018-05-18 Alan Modra <amodra@gmail.com>
1541 * nfp-dis.c: Don't #include libbfd.h.
1542 (init_nfp3200_priv): Use bfd_get_section_contents.
1543 (nit_nfp6000_mecsr_sec): Likewise.
1545 2018-05-17 Nick Clifton <nickc@redhat.com>
1547 * po/zh_CN.po: Updated simplified Chinese translation.
1549 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1552 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1553 * aarch64-dis-2.c: Regenerate.
1555 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1558 * aarch64-asm.c (opintl.h): Include.
1559 (aarch64_ins_sysreg): Enforce read/write constraints.
1560 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1561 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1562 (F_REG_READ, F_REG_WRITE): New.
1563 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1564 AARCH64_OPND_SYSREG.
1565 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1566 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1567 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1568 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1569 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1570 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1571 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1572 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1573 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1574 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1575 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1576 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1577 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1578 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1579 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1580 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1581 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1583 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1586 * aarch64-dis.c (no_notes: New.
1587 (parse_aarch64_dis_option): Support notes.
1588 (aarch64_decode_insn, print_operands): Likewise.
1589 (print_aarch64_disassembler_options): Document notes.
1590 * aarch64-opc.c (aarch64_print_operand): Support notes.
1592 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1595 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1596 and take error struct.
1597 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1598 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1599 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1600 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1601 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1602 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1603 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1604 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1605 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1606 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1607 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1608 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1609 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1610 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1611 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1612 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1613 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1614 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1615 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1616 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1617 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1618 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1619 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1620 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1621 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1622 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1623 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1624 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1625 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1626 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1627 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1628 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1629 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1630 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1631 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1632 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1633 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1634 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1635 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1636 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1637 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1638 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1639 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1640 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1641 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1642 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1643 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1644 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1645 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1646 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1647 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1648 (determine_disassembling_preference, aarch64_decode_insn,
1649 print_insn_aarch64_word, print_insn_data): Take errors struct.
1650 (print_insn_aarch64): Use errors.
1651 * aarch64-asm-2.c: Regenerate.
1652 * aarch64-dis-2.c: Regenerate.
1653 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1654 boolean in aarch64_insert_operan.
1655 (print_operand_extractor): Likewise.
1656 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1658 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1660 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1662 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1664 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1666 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1668 * cr16-opc.c (cr16_instruction): Comment typo fix.
1669 * hppa-dis.c (print_insn_hppa): Likewise.
1671 2018-05-08 Jim Wilson <jimw@sifive.com>
1673 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1674 (match_c_slli64, match_srxi_as_c_srxi): New.
1675 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1676 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1677 <c.slli, c.srli, c.srai>: Use match_s_slli.
1678 <c.slli64, c.srli64, c.srai64>: New.
1680 2018-05-08 Alan Modra <amodra@gmail.com>
1682 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1683 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1684 partition opcode space for index lookup.
1686 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1688 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1689 <insn_length>: ...with this. Update usage.
1690 Remove duplicate call to *info->memory_error_func.
1692 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1693 H.J. Lu <hongjiu.lu@intel.com>
1695 * i386-dis.c (Gva): New.
1696 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1697 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1698 (prefix_table): New instructions (see prefix above).
1699 (mod_table): New instructions (see prefix above).
1700 (OP_G): Handle va_mode.
1701 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1702 CPU_MOVDIR64B_FLAGS.
1703 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1704 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1705 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1706 * i386-opc.tbl: Add movidir{i,64b}.
1707 * i386-init.h: Regenerated.
1708 * i386-tbl.h: Likewise.
1710 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1712 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1714 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1715 (AddrPrefixOpReg): This.
1716 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1717 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1719 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1721 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1722 (vle_num_opcodes): Likewise.
1723 (spe2_num_opcodes): Likewise.
1724 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1725 initialization loop.
1726 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1727 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1730 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1732 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1734 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1736 Makefile.am: Added nfp-dis.c.
1737 configure.ac: Added bfd_nfp_arch.
1738 disassemble.h: Added print_insn_nfp prototype.
1739 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1740 nfp-dis.c: New, for NFP support.
1741 po/POTFILES.in: Added nfp-dis.c to the list.
1742 Makefile.in: Regenerate.
1743 configure: Regenerate.
1745 2018-04-26 Jan Beulich <jbeulich@suse.com>
1747 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1748 templates into their base ones.
1749 * i386-tlb.h: Re-generate.
1751 2018-04-26 Jan Beulich <jbeulich@suse.com>
1753 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1754 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1755 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1756 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1757 * i386-init.h: Re-generate.
1759 2018-04-26 Jan Beulich <jbeulich@suse.com>
1761 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1762 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1763 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1764 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1766 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1768 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1770 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1771 cpuregzmm, and cpuregmask.
1772 * i386-init.h: Re-generate.
1773 * i386-tbl.h: Re-generate.
1775 2018-04-26 Jan Beulich <jbeulich@suse.com>
1777 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1778 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1779 * i386-init.h: Re-generate.
1781 2018-04-26 Jan Beulich <jbeulich@suse.com>
1783 * i386-gen.c (VexImmExt): Delete.
1784 * i386-opc.h (VexImmExt, veximmext): Delete.
1785 * i386-opc.tbl: Drop all VexImmExt uses.
1786 * i386-tlb.h: Re-generate.
1788 2018-04-25 Jan Beulich <jbeulich@suse.com>
1790 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1791 register-only forms.
1792 * i386-tlb.h: Re-generate.
1794 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1796 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1798 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1800 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1802 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1803 (cpu_flags): Add CpuCLDEMOTE.
1804 * i386-init.h: Regenerate.
1805 * i386-opc.h (enum): Add CpuCLDEMOTE,
1806 (i386_cpu_flags): Add cpucldemote.
1807 * i386-opc.tbl: Add cldemote.
1808 * i386-tbl.h: Regenerate.
1810 2018-04-16 Alan Modra <amodra@gmail.com>
1812 * Makefile.am: Remove sh5 and sh64 support.
1813 * configure.ac: Likewise.
1814 * disassemble.c: Likewise.
1815 * disassemble.h: Likewise.
1816 * sh-dis.c: Likewise.
1817 * sh64-dis.c: Delete.
1818 * sh64-opc.c: Delete.
1819 * sh64-opc.h: Delete.
1820 * Makefile.in: Regenerate.
1821 * configure: Regenerate.
1822 * po/POTFILES.in: Regenerate.
1824 2018-04-16 Alan Modra <amodra@gmail.com>
1826 * Makefile.am: Remove w65 support.
1827 * configure.ac: Likewise.
1828 * disassemble.c: Likewise.
1829 * disassemble.h: Likewise.
1830 * w65-dis.c: Delete.
1831 * w65-opc.h: Delete.
1832 * Makefile.in: Regenerate.
1833 * configure: Regenerate.
1834 * po/POTFILES.in: Regenerate.
1836 2018-04-16 Alan Modra <amodra@gmail.com>
1838 * configure.ac: Remove we32k support.
1839 * configure: Regenerate.
1841 2018-04-16 Alan Modra <amodra@gmail.com>
1843 * Makefile.am: Remove m88k support.
1844 * configure.ac: Likewise.
1845 * disassemble.c: Likewise.
1846 * disassemble.h: Likewise.
1847 * m88k-dis.c: Delete.
1848 * Makefile.in: Regenerate.
1849 * configure: Regenerate.
1850 * po/POTFILES.in: Regenerate.
1852 2018-04-16 Alan Modra <amodra@gmail.com>
1854 * Makefile.am: Remove i370 support.
1855 * configure.ac: Likewise.
1856 * disassemble.c: Likewise.
1857 * disassemble.h: Likewise.
1858 * i370-dis.c: Delete.
1859 * i370-opc.c: Delete.
1860 * Makefile.in: Regenerate.
1861 * configure: Regenerate.
1862 * po/POTFILES.in: Regenerate.
1864 2018-04-16 Alan Modra <amodra@gmail.com>
1866 * Makefile.am: Remove h8500 support.
1867 * configure.ac: Likewise.
1868 * disassemble.c: Likewise.
1869 * disassemble.h: Likewise.
1870 * h8500-dis.c: Delete.
1871 * h8500-opc.h: Delete.
1872 * Makefile.in: Regenerate.
1873 * configure: Regenerate.
1874 * po/POTFILES.in: Regenerate.
1876 2018-04-16 Alan Modra <amodra@gmail.com>
1878 * configure.ac: Remove tahoe support.
1879 * configure: Regenerate.
1881 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1883 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1885 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1887 * i386-tbl.h: Regenerated.
1889 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1891 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1892 PREFIX_MOD_1_0FAE_REG_6.
1894 (OP_E_register): Use va_mode.
1895 * i386-dis-evex.h (prefix_table):
1896 New instructions (see prefixes above).
1897 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1898 (cpu_flags): Likewise.
1899 * i386-opc.h (enum): Likewise.
1900 (i386_cpu_flags): Likewise.
1901 * i386-opc.tbl: Add umonitor, umwait, tpause.
1902 * i386-init.h: Regenerate.
1903 * i386-tbl.h: Likewise.
1905 2018-04-11 Alan Modra <amodra@gmail.com>
1907 * opcodes/i860-dis.c: Delete.
1908 * opcodes/i960-dis.c: Delete.
1909 * Makefile.am: Remove i860 and i960 support.
1910 * configure.ac: Likewise.
1911 * disassemble.c: Likewise.
1912 * disassemble.h: Likewise.
1913 * Makefile.in: Regenerate.
1914 * configure: Regenerate.
1915 * po/POTFILES.in: Regenerate.
1917 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1920 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1922 (print_insn): Clear vex instead of vex.evex.
1924 2018-04-04 Nick Clifton <nickc@redhat.com>
1926 * po/es.po: Updated Spanish translation.
1928 2018-03-28 Jan Beulich <jbeulich@suse.com>
1930 * i386-gen.c (opcode_modifiers): Delete VecESize.
1931 * i386-opc.h (VecESize): Delete.
1932 (struct i386_opcode_modifier): Delete vecesize.
1933 * i386-opc.tbl: Drop VecESize.
1934 * i386-tlb.h: Re-generate.
1936 2018-03-28 Jan Beulich <jbeulich@suse.com>
1938 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1939 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1940 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1941 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1942 * i386-tlb.h: Re-generate.
1944 2018-03-28 Jan Beulich <jbeulich@suse.com>
1946 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1948 * i386-tlb.h: Re-generate.
1950 2018-03-28 Jan Beulich <jbeulich@suse.com>
1952 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1953 (vex_len_table): Drop Y for vcvt*2si.
1954 (putop): Replace plain 'Y' handling by abort().
1956 2018-03-28 Nick Clifton <nickc@redhat.com>
1959 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1960 instructions with only a base address register.
1961 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1962 handle AARHC64_OPND_SVE_ADDR_R.
1963 (aarch64_print_operand): Likewise.
1964 * aarch64-asm-2.c: Regenerate.
1965 * aarch64_dis-2.c: Regenerate.
1966 * aarch64-opc-2.c: Regenerate.
1968 2018-03-22 Jan Beulich <jbeulich@suse.com>
1970 * i386-opc.tbl: Drop VecESize from register only insn forms and
1971 memory forms not allowing broadcast.
1972 * i386-tlb.h: Re-generate.
1974 2018-03-22 Jan Beulich <jbeulich@suse.com>
1976 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1977 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1978 sha256*): Drop Disp<N>.
1980 2018-03-22 Jan Beulich <jbeulich@suse.com>
1982 * i386-dis.c (EbndS, bnd_swap_mode): New.
1983 (prefix_table): Use EbndS.
1984 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1985 * i386-opc.tbl (bndmov): Move misplaced Load.
1986 * i386-tlb.h: Re-generate.
1988 2018-03-22 Jan Beulich <jbeulich@suse.com>
1990 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1991 templates allowing memory operands and folded ones for register
1993 * i386-tlb.h: Re-generate.
1995 2018-03-22 Jan Beulich <jbeulich@suse.com>
1997 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1998 256-bit templates. Drop redundant leftover Disp<N>.
1999 * i386-tlb.h: Re-generate.
2001 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
2003 * riscv-opc.c (riscv_insn_types): New.
2005 2018-03-13 Nick Clifton <nickc@redhat.com>
2007 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2009 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2011 * i386-opc.tbl: Add Optimize to clr.
2012 * i386-tbl.h: Regenerated.
2014 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2016 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2017 * i386-opc.h (OldGcc): Removed.
2018 (i386_opcode_modifier): Remove oldgcc.
2019 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2020 instructions for old (<= 2.8.1) versions of gcc.
2021 * i386-tbl.h: Regenerated.
2023 2018-03-08 Jan Beulich <jbeulich@suse.com>
2025 * i386-opc.h (EVEXDYN): New.
2026 * i386-opc.tbl: Fold various AVX512VL templates.
2027 * i386-tlb.h: Re-generate.
2029 2018-03-08 Jan Beulich <jbeulich@suse.com>
2031 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2032 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2033 vpexpandd, vpexpandq): Fold AFX512VF templates.
2034 * i386-tlb.h: Re-generate.
2036 2018-03-08 Jan Beulich <jbeulich@suse.com>
2038 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2039 Fold 128- and 256-bit VEX-encoded templates.
2040 * i386-tlb.h: Re-generate.
2042 2018-03-08 Jan Beulich <jbeulich@suse.com>
2044 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2045 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2046 vpexpandd, vpexpandq): Fold AVX512F templates.
2047 * i386-tlb.h: Re-generate.
2049 2018-03-08 Jan Beulich <jbeulich@suse.com>
2051 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2052 64-bit templates. Drop Disp<N>.
2053 * i386-tlb.h: Re-generate.
2055 2018-03-08 Jan Beulich <jbeulich@suse.com>
2057 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2058 and 256-bit templates.
2059 * i386-tlb.h: Re-generate.
2061 2018-03-08 Jan Beulich <jbeulich@suse.com>
2063 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2064 * i386-tlb.h: Re-generate.
2066 2018-03-08 Jan Beulich <jbeulich@suse.com>
2068 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2070 * i386-tlb.h: Re-generate.
2072 2018-03-08 Jan Beulich <jbeulich@suse.com>
2074 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2075 * i386-tlb.h: Re-generate.
2077 2018-03-08 Jan Beulich <jbeulich@suse.com>
2079 * i386-gen.c (opcode_modifiers): Delete FloatD.
2080 * i386-opc.h (FloatD): Delete.
2081 (struct i386_opcode_modifier): Delete floatd.
2082 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2084 * i386-tlb.h: Re-generate.
2086 2018-03-08 Jan Beulich <jbeulich@suse.com>
2088 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2090 2018-03-08 Jan Beulich <jbeulich@suse.com>
2092 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2093 * i386-tlb.h: Re-generate.
2095 2018-03-08 Jan Beulich <jbeulich@suse.com>
2097 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2099 * i386-tlb.h: Re-generate.
2101 2018-03-07 Alan Modra <amodra@gmail.com>
2103 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2105 * disassemble.h (print_insn_rs6000): Delete.
2106 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2107 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2108 (print_insn_rs6000): Delete.
2110 2018-03-03 Alan Modra <amodra@gmail.com>
2112 * sysdep.h (opcodes_error_handler): Define.
2113 (_bfd_error_handler): Declare.
2114 * Makefile.am: Remove stray #.
2115 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2117 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2118 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2119 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2120 opcodes_error_handler to print errors. Standardize error messages.
2121 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2122 and include opintl.h.
2123 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2124 * i386-gen.c: Standardize error messages.
2125 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2126 * Makefile.in: Regenerate.
2127 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2128 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2129 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2130 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2131 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2132 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2133 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2134 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2135 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2136 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2137 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2138 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2139 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2141 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2143 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2144 vpsub[bwdq] instructions.
2145 * i386-tbl.h: Regenerated.
2147 2018-03-01 Alan Modra <amodra@gmail.com>
2149 * configure.ac (ALL_LINGUAS): Sort.
2150 * configure: Regenerate.
2152 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2154 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2155 macro by assignements.
2157 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2160 * i386-gen.c (opcode_modifiers): Add Optimize.
2161 * i386-opc.h (Optimize): New enum.
2162 (i386_opcode_modifier): Add optimize.
2163 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2164 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2165 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2166 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2167 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2169 * i386-tbl.h: Regenerated.
2171 2018-02-26 Alan Modra <amodra@gmail.com>
2173 * crx-dis.c (getregliststring): Allocate a large enough buffer
2174 to silence false positive gcc8 warning.
2176 2018-02-22 Shea Levy <shea@shealevy.com>
2178 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2180 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2182 * i386-opc.tbl: Add {rex},
2183 * i386-tbl.h: Regenerated.
2185 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2187 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2188 (mips16_opcodes): Replace `M' with `m' for "restore".
2190 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2192 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2194 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2196 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2197 variable to `function_index'.
2199 2018-02-13 Nick Clifton <nickc@redhat.com>
2202 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2203 about truncation of printing.
2205 2018-02-12 Henry Wong <henry@stuffedcow.net>
2207 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2209 2018-02-05 Nick Clifton <nickc@redhat.com>
2211 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2213 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2215 * i386-dis.c (enum): Add pconfig.
2216 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2217 (cpu_flags): Add CpuPCONFIG.
2218 * i386-opc.h (enum): Add CpuPCONFIG.
2219 (i386_cpu_flags): Add cpupconfig.
2220 * i386-opc.tbl: Add PCONFIG instruction.
2221 * i386-init.h: Regenerate.
2222 * i386-tbl.h: Likewise.
2224 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2226 * i386-dis.c (enum): Add PREFIX_0F09.
2227 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2228 (cpu_flags): Add CpuWBNOINVD.
2229 * i386-opc.h (enum): Add CpuWBNOINVD.
2230 (i386_cpu_flags): Add cpuwbnoinvd.
2231 * i386-opc.tbl: Add WBNOINVD instruction.
2232 * i386-init.h: Regenerate.
2233 * i386-tbl.h: Likewise.
2235 2018-01-17 Jim Wilson <jimw@sifive.com>
2237 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2239 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2241 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2242 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2243 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2244 (cpu_flags): Add CpuIBT, CpuSHSTK.
2245 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2246 (i386_cpu_flags): Add cpuibt, cpushstk.
2247 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2248 * i386-init.h: Regenerate.
2249 * i386-tbl.h: Likewise.
2251 2018-01-16 Nick Clifton <nickc@redhat.com>
2253 * po/pt_BR.po: Updated Brazilian Portugese translation.
2254 * po/de.po: Updated German translation.
2256 2018-01-15 Jim Wilson <jimw@sifive.com>
2258 * riscv-opc.c (match_c_nop): New.
2259 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2261 2018-01-15 Nick Clifton <nickc@redhat.com>
2263 * po/uk.po: Updated Ukranian translation.
2265 2018-01-13 Nick Clifton <nickc@redhat.com>
2267 * po/opcodes.pot: Regenerated.
2269 2018-01-13 Nick Clifton <nickc@redhat.com>
2271 * configure: Regenerate.
2273 2018-01-13 Nick Clifton <nickc@redhat.com>
2275 2.30 branch created.
2277 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2279 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2280 * i386-tbl.h: Regenerate.
2282 2018-01-10 Jan Beulich <jbeulich@suse.com>
2284 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2285 * i386-tbl.h: Re-generate.
2287 2018-01-10 Jan Beulich <jbeulich@suse.com>
2289 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2290 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2291 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2292 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2293 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2294 Disp8MemShift of AVX512VL forms.
2295 * i386-tbl.h: Re-generate.
2297 2018-01-09 Jim Wilson <jimw@sifive.com>
2299 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2300 then the hi_addr value is zero.
2302 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2304 * arm-dis.c (arm_opcodes): Add csdb.
2305 (thumb32_opcodes): Add csdb.
2307 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2309 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2310 * aarch64-asm-2.c: Regenerate.
2311 * aarch64-dis-2.c: Regenerate.
2312 * aarch64-opc-2.c: Regenerate.
2314 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2317 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2318 Remove AVX512 vmovd with 64-bit operands.
2319 * i386-tbl.h: Regenerated.
2321 2018-01-05 Jim Wilson <jimw@sifive.com>
2323 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2326 2018-01-03 Alan Modra <amodra@gmail.com>
2328 Update year range in copyright notice of all files.
2330 2018-01-02 Jan Beulich <jbeulich@suse.com>
2332 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2333 and OPERAND_TYPE_REGZMM entries.
2335 For older changes see ChangeLog-2017
2337 Copyright (C) 2018 Free Software Foundation, Inc.
2339 Copying and distribution of this file, with or without modification,
2340 are permitted in any medium without royalty provided the copyright
2341 notice and this notice are preserved.
2347 version-control: never