opcodes/ChangeLog

   1 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
   2
   3         * s390-mkopc.c (main): Support alternate arch strings.
   4
   5 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
   6
   7         * s390-opc.txt: Fix kmctr instruction type.
   8
   9 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
  10
  11         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
  12         * i386-init.h: Regenerated.
  13
  14 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
  15
  16         * opcodes/arc-dis.c (print_insn_arc): Changed.
  17
  18 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
  19
  20         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
  21         camellia_fl.
  22
  23 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  24
  25         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
  26         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
  27         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
  28
  29 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
  30
  31         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
  32         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
  33         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
  34         PREFIX_MOD_3_0FAE_REG_4.
  35         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
  36         PREFIX_MOD_3_0FAE_REG_4.
  37         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
  38         (cpu_flags): Add CpuPTWRITE.
  39         * i386-opc.h (CpuPTWRITE): New.
  40         (i386_cpu_flags): Add cpuptwrite.
  41         * i386-opc.tbl: Add ptwrite instruction.
  42         * i386-init.h: Regenerated.
  43         * i386-tbl.h: Likewise.
  44
  45 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  46
  47         * arc-dis.h: Wrap around in extern "C".
  48
  49 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  50
  51         * aarch64-tbl.h (V8_2_INSN): New macro.
  52         (aarch64_opcode_table): Use it.
  53
  54 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  55
  56         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
  57         CORE_INSN, __FP_INSN and SIMD_INSN.
  58
  59 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  60
  61         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
  62         (aarch64_opcode_table): Update uses accordingly.
  63
  64 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
  65         Kwok Cheung Yeung  <kcy@codesourcery.com>
  66
  67         opcodes/
  68         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
  69         'e_cmplwi' to 'e_cmpli' instead.
  70         (OPVUPRT, OPVUPRT_MASK): Define.
  71         (powerpc_opcodes): Add E200Z4 insns.
  72         (vle_opcodes): Add context save/restore insns.
  73
  74 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
  75
  76         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
  77         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
  78         "j".
  79
  80 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
  81
  82         * arc-nps400-tbl.h: Change block comments to GNU format.
  83         * arc-dis.c: Add new globals addrtypenames,
  84         addrtypenames_max, and addtypeunknown.
  85         (get_addrtype): New function.
  86         (print_insn_arc): Print colons and address types when
  87         required.
  88         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
  89         define insert and extract functions for all address types.
  90         (arc_operands): Add operands for colon and all address
  91         types.
  92         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
  93         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
  94         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
  95         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
  96         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
  97         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
  98
  99 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 100
 101         * configure: Regenerated.
 102
 103 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 104
 105         * arc-dis.c (skipclass): New structure.
 106         (decodelist): New variable.
 107         (is_compatible_p): New function.
 108         (new_element): Likewise.
 109         (skip_class_p): Likewise.
 110         (find_format_from_table): Use skip_class_p function.
 111         (find_format): Decode first the extension instructions.
 112         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 113         e_flags.
 114         (parse_option): New function.
 115         (parse_disassembler_options): Likewise.
 116         (print_arc_disassembler_options): Likewise.
 117         (print_insn_arc): Use parse_disassembler_options function.  Proper
 118         select ARCv2 cpu variant.
 119         * disassemble.c (disassembler_usage): Add ARC disassembler
 120         options.
 121
 122 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 123
 124         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 125         annotation from the "nal" entry and reorder it beyond "bltzal".
 126
 127 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 128
 129         * sparc-opc.c (ldtxa): New macro.
 130         (sparc_opcodes): Use the macro defined above to add entries for
 131         the LDTXA instructions.
 132         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 133         instruction.
 134
 135 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 136
 137         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 138         and "jmpc".
 139
 140 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 143         (movzb): Adjust to cover all permitted suffixes.
 144         (movzw): New.
 145         * i386-tbl.h: Re-generate.
 146
 147 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 148
 149         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 150         (lgdt): Remove Tbyte from non-64-bit variant.
 151         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 152         xsaves64, xsavec64): Remove Disp16.
 153         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 154         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 155         64-bit variants.
 156         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 157         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 158         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 159         64-bit variants.
 160         * i386-tbl.h: Re-generate.
 161
 162 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 165         * i386-tbl.h: Re-generate.
 166
 167 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 168
 169         * arm-dis.c (print_insn): Fix typo in comment.
 170
 171 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 172
 173         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 174         range of ldst_elemlist operands.
 175         (print_register_list): Use PRIi64 to print the index.
 176         (aarch64_print_operand): Likewise.
 177
 178 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 179
 180         * mcore-opc.h: Remove sentinal.
 181         * mcore-dis.c (print_insn_mcore): Adjust.
 182
 183 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 184
 185         * arc-opc.c: Correct description of availability of NPS400
 186         features.
 187
 188 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 189
 190         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 191         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 192         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 193         xor3>: New mnemonics.
 194         <setb>: Change to a VX form instruction.
 195         (insert_sh6): Add support for rldixor.
 196         (extract_sh6): Likewise.
 197
 198 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 199
 200         * arc-ext.h: Wrap in extern C.
 201
 202 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 203
 204         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 205         Use same method for determining instruction length on ARC700 and
 206         NPS-400.
 207         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 208         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 209         with the NPS400 subclass.
 210         * arc-opc.c: Likewise.
 211
 212 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 213
 214         * sparc-opc.c (rdasr): New macro.
 215         (wrasr): Likewise.
 216         (rdpr): Likewise.
 217         (wrpr): Likewise.
 218         (rdhpr): Likewise.
 219         (wrhpr): Likewise.
 220         (sparc_opcodes): Use the macros above to fix and expand the
 221         definition of read/write instructions from/to
 222         asr/privileged/hyperprivileged instructions.
 223         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 224         %hva_mask_nz.  Prefer softint_set and softint_clear over
 225         set_softint and clear_softint.
 226         (print_insn_sparc): Support %ver in Rd.
 227
 228 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 229
 230         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 231         architecture according to the hardware capabilities they require.
 232
 233 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 234
 235         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 236         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 237         bfd_mach_sparc_v9{c,d,e,v,m}.
 238         * sparc-opc.c (MASK_V9C): Define.
 239         (MASK_V9D): Likewise.
 240         (MASK_V9E): Likewise.
 241         (MASK_V9V): Likewise.
 242         (MASK_V9M): Likewise.
 243         (v6): Add MASK_V9{C,D,E,V,M}.
 244         (v6notlet): Likewise.
 245         (v7): Likewise.
 246         (v8): Likewise.
 247         (v9): Likewise.
 248         (v9andleon): Likewise.
 249         (v9a): Likewise.
 250         (v9b): Likewise.
 251         (v9c): Define.
 252         (v9d): Likewise.
 253         (v9e): Likewise.
 254         (v9v): Likewise.
 255         (v9m): Likewise.
 256         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 257
 258 2016-06-15  Nick Clifton  <nickc@redhat.com>
 259
 260         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 261         constants to match expected behaviour.
 262         (nds32_parse_opcode): Likewise.  Also for whitespace.
 263
 264 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 265
 266         * arc-opc.c (extract_rhv1): Extract value from insn.
 267
 268 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 269
 270         * arc-nps400-tbl.h: Add ldbit instruction.
 271         * arc-opc.c: Add flag classes required for ldbit.
 272
 273 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 274
 275         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 276         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 277         support the above instructions.
 278
 279 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 280
 281         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 282         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 283         csma, cbba, zncv, and hofs.
 284         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 285         support the above instructions.
 286
 287 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 288
 289         * arc-nps400-tbl.h: Add andab and orab instructions.
 290
 291 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 292
 293         * arc-nps400-tbl.h: Add addl-like instructions.
 294
 295 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 296
 297         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 298
 299 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 300
 301         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 302         instructions.
 303
 304 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 305
 306         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 307         variable.
 308         (init_disasm): Handle new command line option "insnlength".
 309         (print_s390_disassembler_options): Mention new option in help
 310         output.
 311         (print_insn_s390): Use the encoded insn length when dumping
 312         unknown instructions.
 313
 314 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 315
 316         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 317          to the address and set as symbol address for LDS/ STS immediate operands.
 318
 319 2016-06-07  Alan Modra  <amodra@gmail.com>
 320
 321         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 322         cpu for "vle" to e500.
 323         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 324         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 325         (PPCNONE): Delete, substitute throughout.
 326         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 327         except for major opcode 4 and 31.
 328         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 329
 330 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 331
 332         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 333         ARM_EXT_RAS in relevant entries.
 334
 335 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 336
 337         PR binutils/20196
 338         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 339         opcodes for E6500.
 340
 341 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 342
 343         PR binutis/18386
 344         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 345         (indir_v_mode): New.
 346         Add comments for '&'.
 347         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 348         (putop): Handle '&'.
 349         (intel_operand_size): Handle indir_v_mode.
 350         (OP_E_register): Likewise.
 351         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 352         64-bit indirect call/jmp for AMD64.
 353         * i386-tbl.h: Regenerated
 354
 355 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 356
 357         * arc-dis.c (struct arc_operand_iterator): New structure.
 358         (find_format_from_table): All the old content from find_format,
 359         with some minor adjustments, and parameter renaming.
 360         (find_format_long_instructions): New function.
 361         (find_format): Rewritten.
 362         (arc_insn_length): Add LSB parameter.
 363         (extract_operand_value): New function.
 364         (operand_iterator_next): New function.
 365         (print_insn_arc): Use new functions to find opcode, and iterator
 366         over operands.
 367         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 368         (extract_nps_3bit_dst_short): New function.
 369         (insert_nps_3bit_src2_short): New function.
 370         (extract_nps_3bit_src2_short): New function.
 371         (insert_nps_bitop1_size): New function.
 372         (extract_nps_bitop1_size): New function.
 373         (insert_nps_bitop2_size): New function.
 374         (extract_nps_bitop2_size): New function.
 375         (insert_nps_bitop_mod4_msb): New function.
 376         (extract_nps_bitop_mod4_msb): New function.
 377         (insert_nps_bitop_mod4_lsb): New function.
 378         (extract_nps_bitop_mod4_lsb): New function.
 379         (insert_nps_bitop_dst_pos3_pos4): New function.
 380         (extract_nps_bitop_dst_pos3_pos4): New function.
 381         (insert_nps_bitop_ins_ext): New function.
 382         (extract_nps_bitop_ins_ext): New function.
 383         (arc_operands): Add new operands.
 384         (arc_long_opcodes): New global array.
 385         (arc_num_long_opcodes): New global.
 386         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 387
 388 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 389
 390         * nds32-asm.h: Add extern "C".
 391         * sh-opc.h: Likewise.
 392
 393 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 394
 395         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 396         0,b,limm to the rflt instruction.
 397
 398 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 399
 400         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 401         constant.
 402
 403 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 404
 405         PR gas/20145
 406         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 407         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 408         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 409         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 410         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 411         * i386-init.h: Regenerated.
 412
 413 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         PR gas/20145
 416         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 417         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 418         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 419         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 420         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 421         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 422         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 423         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 424         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 425         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 426         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 427         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 428         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 429         CpuRegMask for AVX512.
 430         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 431         and CpuRegMask.
 432         (set_bitfield_from_cpu_flag_init): New function.
 433         (set_bitfield): Remove const on f.  Call
 434         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 435         * i386-opc.h (CpuRegMMX): New.
 436         (CpuRegXMM): Likewise.
 437         (CpuRegYMM): Likewise.
 438         (CpuRegZMM): Likewise.
 439         (CpuRegMask): Likewise.
 440         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 441         and cpuregmask.
 442         * i386-init.h: Regenerated.
 443         * i386-tbl.h: Likewise.
 444
 445 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 446
 447         PR gas/20154
 448         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 449         (opcode_modifiers): Add AMD64 and Intel64.
 450         (main): Properly verify CpuMax.
 451         * i386-opc.h (CpuAMD64): Removed.
 452         (CpuIntel64): Likewise.
 453         (CpuMax): Set to CpuNo64.
 454         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 455         (AMD64): New.
 456         (Intel64): Likewise.
 457         (i386_opcode_modifier): Add amd64 and intel64.
 458         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 459         on call and jmp.
 460         * i386-init.h: Regenerated.
 461         * i386-tbl.h: Likewise.
 462
 463 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 464
 465         PR gas/20154
 466         * i386-gen.c (main): Fail if CpuMax is incorrect.
 467         * i386-opc.h (CpuMax): Set to CpuIntel64.
 468         * i386-tbl.h: Regenerated.
 469
 470 2016-05-27  Nick Clifton  <nickc@redhat.com>
 471
 472         PR target/20150
 473         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 474         (msp430dis_opcode_unsigned): New function.
 475         (msp430dis_opcode_signed): New function.
 476         (msp430_singleoperand): Use the new opcode reading functions.
 477         Only disassenmble bytes if they were successfully read.
 478         (msp430_doubleoperand): Likewise.
 479         (msp430_branchinstr): Likewise.
 480         (msp430x_callx_instr): Likewise.
 481         (print_insn_msp430): Check that it is safe to read bytes before
 482         attempting disassembly.  Use the new opcode reading functions.
 483
 484 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 485
 486         * ppc-opc.c (CY): New define.  Document it.
 487         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 488
 489 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 490
 491         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 492         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 493         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 494         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 495         CPU_ANY_AVX_FLAGS.
 496         * i386-init.h: Regenerated.
 497
 498 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 499
 500         PR gas/20141
 501         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 502         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 503         * i386-init.h: Regenerated.
 504
 505 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 506
 507         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 508         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 509         * i386-init.h: Regenerated.
 510
 511 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 512
 513         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 514         information.
 515         (print_insn_arc): Set insn_type information.
 516         * arc-opc.c (C_CC): Add F_CLASS_COND.
 517         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 518         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 519         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 520         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 521         (brne, brne_s, jeq_s, jne_s): Likewise.
 522
 523 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 524
 525         * arc-tbl.h (neg): New instruction variant.
 526
 527 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 528
 529         * arc-dis.c (find_format, find_format, get_auxreg)
 530         (print_insn_arc): Changed.
 531         * arc-ext.h (INSERT_XOP): Likewise.
 532
 533 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 534
 535         * tic54x-dis.c (sprint_mmr): Adjust.
 536         * tic54x-opc.c: Likewise.
 537
 538 2016-05-19  Alan Modra  <amodra@gmail.com>
 539
 540         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 541
 542 2016-05-19  Alan Modra  <amodra@gmail.com>
 543
 544         * ppc-opc.c: Formatting.
 545         (NSISIGNOPT): Define.
 546         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 547
 548 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 549
 550         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 551         replacing references to `micromips_ase' throughout.
 552         (_print_insn_mips): Don't use file-level microMIPS annotation to
 553         determine the disassembly mode with the symbol table.
 554
 555 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 556
 557         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 558
 559 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 560
 561         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 562         mips64r6.
 563         * mips-opc.c (D34): New macro.
 564         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 565
 566 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 567
 568         * i386-dis.c (prefix_table): Add RDPID instruction.
 569         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 570         (cpu_flags): Add RDPID bitfield.
 571         * i386-opc.h (enum): Add RDPID element.
 572         (i386_cpu_flags): Add RDPID field.
 573         * i386-opc.tbl: Add RDPID instruction.
 574         * i386-init.h: Regenerate.
 575         * i386-tbl.h: Regenerate.
 576
 577 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 578
 579         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 580         branch type of a symbol.
 581         (print_insn): Likewise.
 582
 583 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 584
 585         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 586         Mainline Security Extensions instructions.
 587         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 588         Extensions instructions.
 589         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 590         instructions.
 591         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 592         special registers.
 593
 594 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 595
 596         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 597
 598 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 599
 600         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 601         (arcExtMap_genOpcode): Likewise.
 602         * arc-opc.c (arg_32bit_rc): Define new variable.
 603         (arg_32bit_u6): Likewise.
 604         (arg_32bit_limm): Likewise.
 605
 606 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 607
 608         * aarch64-gen.c (VERIFIER): Define.
 609         * aarch64-opc.c (VERIFIER): Define.
 610         (verify_ldpsw): Use static linkage.
 611         * aarch64-opc.h (verify_ldpsw): Remove.
 612         * aarch64-tbl.h: Use VERIFIER for verifiers.
 613
 614 2016-04-28  Nick Clifton  <nickc@redhat.com>
 615
 616         PR target/19722
 617         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 618         * aarch64-opc.c (verify_ldpsw): New function.
 619         * aarch64-opc.h (verify_ldpsw): New prototype.
 620         * aarch64-tbl.h: Add initialiser for verifier field.
 621         (LDPSW): Set verifier to verify_ldpsw.
 622
 623 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         PR binutils/19983
 626         PR binutils/19984
 627         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 628         smaller than address size.
 629
 630 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 631
 632         * alpha-dis.c: Regenerate.
 633         * crx-dis.c: Likewise.
 634         * disassemble.c: Likewise.
 635         * epiphany-opc.c: Likewise.
 636         * fr30-opc.c: Likewise.
 637         * frv-opc.c: Likewise.
 638         * ip2k-opc.c: Likewise.
 639         * iq2000-opc.c: Likewise.
 640         * lm32-opc.c: Likewise.
 641         * lm32-opinst.c: Likewise.
 642         * m32c-opc.c: Likewise.
 643         * m32r-opc.c: Likewise.
 644         * m32r-opinst.c: Likewise.
 645         * mep-opc.c: Likewise.
 646         * mt-opc.c: Likewise.
 647         * or1k-opc.c: Likewise.
 648         * or1k-opinst.c: Likewise.
 649         * tic80-opc.c: Likewise.
 650         * xc16x-opc.c: Likewise.
 651         * xstormy16-opc.c: Likewise.
 652
 653 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 654
 655         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 656         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 657         calcsd, and calcxd instructions.
 658         * arc-opc.c (insert_nps_bitop_size): Delete.
 659         (extract_nps_bitop_size): Delete.
 660         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 661         (extract_nps_qcmp_m3): Define.
 662         (extract_nps_qcmp_m2): Define.
 663         (extract_nps_qcmp_m1): Define.
 664         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 665         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 666         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 667         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 668         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 669         NPS_QCMP_M3.
 670
 671 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 672
 673         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 674
 675 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 676
 677         * Makefile.in: Regenerated with automake 1.11.6.
 678         * aclocal.m4: Likewise.
 679
 680 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 681
 682         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 683         instructions.
 684         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 685         (extract_nps_cmem_uimm16): New function.
 686         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 687
 688 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 689
 690         * arc-dis.c (arc_insn_length): New function.
 691         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 692         (find_format): Change insnLen parameter to unsigned.
 693
 694 2016-04-13  Nick Clifton  <nickc@redhat.com>
 695
 696         PR target/19937
 697         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 698         the LD.B and LD.BU instructions.
 699
 700 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 701
 702         * arc-dis.c (find_format): Check for extension flags.
 703         (print_flags): New function.
 704         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 705         .extAuxRegister.
 706         * arc-ext.c (arcExtMap_coreRegName): Use
 707         LAST_EXTENSION_CORE_REGISTER.
 708         (arcExtMap_coreReadWrite): Likewise.
 709         (dump_ARC_extmap): Update printing.
 710         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 711         (arc_aux_regs): Add cpu field.
 712         * arc-regs.h: Add cpu field, lower case name aux registers.
 713
 714 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 715
 716         * arc-tbl.h: Add rtsc, sleep with no arguments.
 717
 718 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 719
 720         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 721         Initialize.
 722         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 723         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 724         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 725         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 726         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 727         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 728         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 729         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 730         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 731         (arc_opcode arc_opcodes): Null terminate the array.
 732         (arc_num_opcodes): Remove.
 733         * arc-ext.h (INSERT_XOP): Define.
 734         (extInstruction_t): Likewise.
 735         (arcExtMap_instName): Delete.
 736         (arcExtMap_insn): New function.
 737         (arcExtMap_genOpcode): Likewise.
 738         * arc-ext.c (ExtInstruction): Remove.
 739         (create_map): Zero initialize instruction fields.
 740         (arcExtMap_instName): Remove.
 741         (arcExtMap_insn): New function.
 742         (dump_ARC_extmap): More info while debuging.
 743         (arcExtMap_genOpcode): New function.
 744         * arc-dis.c (find_format): New function.
 745         (print_insn_arc): Use find_format.
 746         (arc_get_disassembler): Enable dump_ARC_extmap only when
 747         debugging.
 748
 749 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 750
 751         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 752         instruction bits out.
 753
 754 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 755
 756         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 757         * arc-opc.c (arc_flag_operands): Add new flags.
 758         (arc_flag_classes): Add new classes.
 759
 760 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 761
 762         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 763
 764 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 765
 766         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 767         encode1, rflt, crc16, and crc32 instructions.
 768         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 769         (arc_flag_classes): Add C_NPS_R.
 770         (insert_nps_bitop_size_2b): New function.
 771         (extract_nps_bitop_size_2b): Likewise.
 772         (insert_nps_bitop_uimm8): Likewise.
 773         (extract_nps_bitop_uimm8): Likewise.
 774         (arc_operands): Add new operand entries.
 775
 776 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 777
 778         * arc-regs.h: Add a new subclass field.  Add double assist
 779         accumulator register values.
 780         * arc-tbl.h: Use DPA subclass to mark the double assist
 781         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 782         * arc-opc.c (RSP): Define instead of SP.
 783         (arc_aux_regs): Add the subclass field.
 784
 785 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 786
 787         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 788
 789 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 790
 791         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 792         NPS_R_SRC1.
 793
 794 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 795
 796         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 797         issues.  No functional changes.
 798
 799 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 800
 801         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 802         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 803         (RTT): Remove duplicate.
 804         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 805         (PCT_CONFIG*): Remove.
 806         (D1L, D1H, D2H, D2L): Define.
 807
 808 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 809
 810         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 811
 812 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 813
 814         * arc-tbl.h (invld07): Remove.
 815         * arc-ext-tbl.h: New file.
 816         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 817         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 818
 819 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 820
 821         Fix -Wstack-usage warnings.
 822         * aarch64-dis.c (print_operands): Substitute size.
 823         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 824
 825 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 826
 827         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 828         to get a proper diagnostic when an invalid ASR register is used.
 829
 830 2016-03-22  Nick Clifton  <nickc@redhat.com>
 831
 832         * configure: Regenerate.
 833
 834 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 835
 836         * arc-nps400-tbl.h: New file.
 837         * arc-opc.c: Add top level comment.
 838         (insert_nps_3bit_dst): New function.
 839         (extract_nps_3bit_dst): New function.
 840         (insert_nps_3bit_src2): New function.
 841         (extract_nps_3bit_src2): New function.
 842         (insert_nps_bitop_size): New function.
 843         (extract_nps_bitop_size): New function.
 844         (arc_flag_operands): Add nps400 entries.
 845         (arc_flag_classes): Add nps400 entries.
 846         (arc_operands): Add nps400 entries.
 847         (arc_opcodes): Add nps400 include.
 848
 849 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 850
 851         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 852         the new class enum values.
 853
 854 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 855
 856         * arc-dis.c (print_insn_arc): Handle nps400.
 857
 858 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 859
 860         * arc-opc.c (BASE): Delete.
 861
 862 2016-03-18  Nick Clifton  <nickc@redhat.com>
 863
 864         PR target/19721
 865         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 866         of MOV insn that aliases an ORR insn.
 867
 868 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 869
 870         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 871
 872 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 873
 874         * mcore-opc.h: Add const qualifiers.
 875         * microblaze-opc.h (struct op_code_struct): Likewise.
 876         * sh-opc.h: Likewise.
 877         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 878         (tic4x_print_op): Likewise.
 879
 880 2016-03-02  Alan Modra  <amodra@gmail.com>
 881
 882         * or1k-desc.h: Regenerate.
 883         * fr30-ibld.c: Regenerate.
 884         * rl78-decode.c: Regenerate.
 885
 886 2016-03-01  Nick Clifton  <nickc@redhat.com>
 887
 888         PR target/19747
 889         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 890
 891 2016-02-24  Renlin Li  <renlin.li@arm.com>
 892
 893         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 894         (print_insn_coprocessor): Support fp16 instructions.
 895
 896 2016-02-24  Renlin Li  <renlin.li@arm.com>
 897
 898         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 899         vminnm, vrint(mpna).
 900
 901 2016-02-24  Renlin Li  <renlin.li@arm.com>
 902
 903         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 904         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 905
 906 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 907
 908         * i386-dis.c (print_insn): Parenthesize expression to prevent
 909         truncated addresses.
 910         (OP_J): Likewise.
 911
 912 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 913             Janek van Oirschot  <jvanoirs@synopsys.com>
 914
 915         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 916         variable.
 917
 918 2016-02-04  Nick Clifton  <nickc@redhat.com>
 919
 920         PR target/19561
 921         * msp430-dis.c (print_insn_msp430): Add a special case for
 922         decoding an RRC instruction with the ZC bit set in the extension
 923         word.
 924
 925 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 926
 927         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 928         * epiphany-ibld.c: Regenerate.
 929         * fr30-ibld.c: Regenerate.
 930         * frv-ibld.c: Regenerate.
 931         * ip2k-ibld.c: Regenerate.
 932         * iq2000-ibld.c: Regenerate.
 933         * lm32-ibld.c: Regenerate.
 934         * m32c-ibld.c: Regenerate.
 935         * m32r-ibld.c: Regenerate.
 936         * mep-ibld.c: Regenerate.
 937         * mt-ibld.c: Regenerate.
 938         * or1k-ibld.c: Regenerate.
 939         * xc16x-ibld.c: Regenerate.
 940         * xstormy16-ibld.c: Regenerate.
 941
 942 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 943
 944         * epiphany-dis.c: Regenerated from latest cpu files.
 945
 946 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 947
 948         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 949         test bit.
 950
 951 2016-01-25  Renlin Li  <renlin.li@arm.com>
 952
 953         * arm-dis.c (mapping_symbol_for_insn): New function.
 954         (find_ifthen_state): Call mapping_symbol_for_insn().
 955
 956 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 957
 958         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 959         of MSR UAO immediate operand.
 960
 961 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 962
 963         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 964         instruction support.
 965
 966 2016-01-17  Alan Modra  <amodra@gmail.com>
 967
 968         * configure: Regenerate.
 969
 970 2016-01-14  Nick Clifton  <nickc@redhat.com>
 971
 972         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 973         instructions that can support stack pointer operations.
 974         * rl78-decode.c: Regenerate.
 975         * rl78-dis.c: Fix display of stack pointer in MOVW based
 976         instructions.
 977
 978 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 979
 980         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 981         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 982         erxtatus_el1 and erxaddr_el1.
 983
 984 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 985
 986         * arm-dis.c (arm_opcodes): Add "esb".
 987         (thumb_opcodes): Likewise.
 988
 989 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 990
 991         * ppc-opc.c <xscmpnedp>: Delete.
 992         <xvcmpnedp>: Likewise.
 993         <xvcmpnedp.>: Likewise.
 994         <xvcmpnesp>: Likewise.
 995         <xvcmpnesp.>: Likewise.
 996
 997 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 998
 999         PR gas/13050
1000         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1001         addition to ISA_A.
1002
1003 2016-01-01  Alan Modra  <amodra@gmail.com>
1004
1005         Update year range in copyright notice of all files.
1006
1007 For older changes see ChangeLog-2015
1008 \f
1009 Copyright (C) 2016 Free Software Foundation, Inc.
1010
1011 Copying and distribution of this file, with or without modification,
1012 are permitted in any medium without royalty provided the copyright
1013 notice and this notice are preserved.
1014
1015 Local Variables:
1016 mode: change-log
1017 left-margin: 8
1018 fill-column: 74
1019 version-control: never
1020 End: