opcodes/ChangeLog

   1 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
   2             Michael Collison <michael.collison@arm.com>
   3
   4         * arm-dis.c (enum mve_instructions): Add new instructions.
   5         (enum mve_unpredictable): Add new reasons.
   6         (enum mve_undefined): Likewise.
   7         (is_mve_encoding_conflict): Handle new instructions.
   8         (is_mve_undefined): Likewise.
   9         (is_mve_unpredictable): Likewise.
  10         (coprocessor_opcodes): Move NEON VDUP from here...
  11         (neon_opcodes): ... to here.
  12         (mve_opcodes): Add new instructions.
  13         (print_mve_undefined):  Handle new reasons.
  14         (print_mve_unpredictable): Likewise.
  15         (print_mve_size): Handle new instructions.
  16         (print_insn_neon): Handle vdup.
  17         (print_insn_mve): Handle new operands.
  18
  19 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  20             Michael Collison <michael.collison@arm.com>
  21
  22         * arm-dis.c (enum mve_instructions): Add new instructions.
  23         (enum mve_unpredictable): Add new values.
  24         (mve_opcodes): Add new instructions.
  25         (vec_condnames): New array with vector conditions.
  26         (mve_predicatenames): New array with predicate suffixes.
  27         (mve_vec_sizename): New array with vector sizes.
  28         (enum vpt_pred_state): New enum with vector predication states.
  29         (struct vpt_block): New struct type for vpt blocks.
  30         (vpt_block_state): Global struct to keep track of state.
  31         (mve_extract_pred_mask): New helper function.
  32         (num_instructions_vpt_block): Likewise.
  33         (mark_outside_vpt_block): Likewise.
  34         (mark_inside_vpt_block): Likewise.
  35         (invert_next_predicate_state): Likewise.
  36         (update_next_predicate_state): Likewise.
  37         (update_vpt_block_state): Likewise.
  38         (is_vpt_instruction): Likewise.
  39         (is_mve_encoding_conflict): Add entries for new instructions.
  40         (is_mve_unpredictable): Likewise.
  41         (print_mve_unpredictable): Handle new cases.
  42         (print_instruction_predicate): Likewise.
  43         (print_mve_size): New function.
  44         (print_vec_condition): New function.
  45         (print_insn_mve): Handle vpt blocks and new print operands.
  46
  47 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  48
  49         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
  50         8, 14 and 15 for Armv8.1-M Mainline.
  51
  52 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  53             Michael Collison <michael.collison@arm.com>
  54
  55         * arm-dis.c (enum mve_instructions): New enum.
  56         (enum mve_unpredictable): Likewise.
  57         (enum mve_undefined): Likewise.
  58         (struct mopcode32): New struct.
  59         (is_mve_okay_in_it): New function.
  60         (is_mve_architecture): Likewise.
  61         (arm_decode_field): Likewise.
  62         (arm_decode_field_multiple): Likewise.
  63         (is_mve_encoding_conflict): Likewise.
  64         (is_mve_undefined): Likewise.
  65         (is_mve_unpredictable): Likewise.
  66         (print_mve_undefined): Likewise.
  67         (print_mve_unpredictable): Likewise.
  68         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
  69         (print_insn_mve): New function.
  70         (print_insn_thumb32): Handle MVE architecture.
  71         (select_arm_features): Force thumb for Armv8.1-m Mainline.
  72
  73 2019-05-10  Nick Clifton  <nickc@redhat.com>
  74
  75         PR 24538
  76         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
  77         end of the table prematurely.
  78
  79 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
  80
  81         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
  82         macros for R6.
  83
  84 2019-05-11  Alan Modra  <amodra@gmail.com>
  85
  86         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
  87         when -Mraw is in effect.
  88
  89 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  90
  91         * aarch64-dis-2.c: Regenerate.
  92         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
  93         (OP_SVE_BBB): New variant set.
  94         (OP_SVE_DDDD): New variant set.
  95         (OP_SVE_HHH): New variant set.
  96         (OP_SVE_HHHU): New variant set.
  97         (OP_SVE_SSS): New variant set.
  98         (OP_SVE_SSSU): New variant set.
  99         (OP_SVE_SHH): New variant set.
 100         (OP_SVE_SBBU): New variant set.
 101         (OP_SVE_DSS): New variant set.
 102         (OP_SVE_DHHU): New variant set.
 103         (OP_SVE_VMV_HSD_BHS): New variant set.
 104         (OP_SVE_VVU_HSD_BHS): New variant set.
 105         (OP_SVE_VVVU_SD_BH): New variant set.
 106         (OP_SVE_VVVU_BHSD): New variant set.
 107         (OP_SVE_VVV_QHD_DBS): New variant set.
 108         (OP_SVE_VVV_HSD_BHS): New variant set.
 109         (OP_SVE_VVV_HSD_BHS2): New variant set.
 110         (OP_SVE_VVV_BHS_HSD): New variant set.
 111         (OP_SVE_VV_BHS_HSD): New variant set.
 112         (OP_SVE_VVV_SD): New variant set.
 113         (OP_SVE_VVU_BHS_HSD): New variant set.
 114         (OP_SVE_VZVV_SD): New variant set.
 115         (OP_SVE_VZVV_BH): New variant set.
 116         (OP_SVE_VZV_SD): New variant set.
 117         (aarch64_opcode_table): Add sve2 instructions.
 118
 119 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 120
 121         * aarch64-asm-2.c: Regenerated.
 122         * aarch64-dis-2.c: Regenerated.
 123         * aarch64-opc-2.c: Regenerated.
 124         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 125         for SVE_SHLIMM_UNPRED_22.
 126         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 127         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 128         operand.
 129
 130 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 131
 132         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 133         sve_size_tsz_bhs iclass encode.
 134         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 135         sve_size_tsz_bhs iclass decode.
 136
 137 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 138
 139         * aarch64-asm-2.c: Regenerated.
 140         * aarch64-dis-2.c: Regenerated.
 141         * aarch64-opc-2.c: Regenerated.
 142         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 143         for SVE_Zm4_11_INDEX.
 144         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 145         (fields): Handle SVE_i2h field.
 146         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 147         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 148
 149 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 150
 151         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 152         sve_shift_tsz_bhsd iclass encode.
 153         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 154         sve_shift_tsz_bhsd iclass decode.
 155
 156 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 157
 158         * aarch64-asm-2.c: Regenerated.
 159         * aarch64-dis-2.c: Regenerated.
 160         * aarch64-opc-2.c: Regenerated.
 161         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 162         (aarch64_encode_variant_using_iclass): Handle
 163         sve_shift_tsz_hsd iclass encode.
 164         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 165         sve_shift_tsz_hsd iclass decode.
 166         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 167         for SVE_SHRIMM_UNPRED_22.
 168         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 169         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 170         operand.
 171
 172 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 173
 174         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 175         sve_size_013 iclass encode.
 176         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 177         sve_size_013 iclass decode.
 178
 179 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 180
 181         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 182         sve_size_bh iclass encode.
 183         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 184         sve_size_bh iclass decode.
 185
 186 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 187
 188         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 189         sve_size_sd2 iclass encode.
 190         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 191         sve_size_sd2 iclass decode.
 192         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 193         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 194
 195 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 196
 197         * aarch64-asm-2.c: Regenerated.
 198         * aarch64-dis-2.c: Regenerated.
 199         * aarch64-opc-2.c: Regenerated.
 200         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 201         for SVE_ADDR_ZX.
 202         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 203         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 204
 205 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 206
 207         * aarch64-asm-2.c: Regenerated.
 208         * aarch64-dis-2.c: Regenerated.
 209         * aarch64-opc-2.c: Regenerated.
 210         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 211         for SVE_Zm3_11_INDEX.
 212         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 213         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 214         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 215         fields.
 216         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 217
 218 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 219
 220         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 221         sve_size_hsd2 iclass encode.
 222         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 223         sve_size_hsd2 iclass decode.
 224         * aarch64-opc.c (fields): Handle SVE_size field.
 225         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 226
 227 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 228
 229         * aarch64-asm-2.c: Regenerated.
 230         * aarch64-dis-2.c: Regenerated.
 231         * aarch64-opc-2.c: Regenerated.
 232         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 233         for SVE_IMM_ROT3.
 234         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 235         (fields): Handle SVE_rot3 field.
 236         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 237         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 238
 239 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 240
 241         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 242         instructions.
 243
 244 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 245
 246         * aarch64-tbl.h
 247         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 248         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 249         aarch64_feature_sve2bitperm): New feature sets.
 250         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 251         for feature set addresses.
 252         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 253         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 254
 255 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 256             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 257
 258         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 259         argument and set ASE_EVA_R6 appropriately.
 260         (set_default_mips_dis_options): Pass ISA to above.
 261         (parse_mips_dis_option): Likewise.
 262         * mips-opc.c (EVAR6): New macro.
 263         (mips_builtin_opcodes): Add llwpe, scwpe.
 264
 265 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 266
 267         * aarch64-asm-2.c: Regenerated.
 268         * aarch64-dis-2.c: Regenerated.
 269         * aarch64-opc-2.c: Regenerated.
 270         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 271         AARCH64_OPND_TME_UIMM16.
 272         (aarch64_print_operand): Likewise.
 273         * aarch64-tbl.h (QL_IMM_NIL): New.
 274         (TME): New.
 275         (_TME_INSN): New.
 276         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 277
 278 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 279
 280         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 281
 282 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 283             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 284
 285         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 286
 287 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 288
 289         * s12z-opc.h: Add extern "C" bracketing to help
 290         users who wish to use this interface in c++ code.
 291
 292 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 293
 294         * s12z-opc.c (bm_decode): Handle bit map operations with the
 295         "reserved0" mode.
 296
 297 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 298
 299         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 300         specifier.  Add entries for VLDR and VSTR of system registers.
 301         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 302         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 303         of %J and %K format specifier.
 304
 305 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 306
 307         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 308         Add new entries for VSCCLRM instruction.
 309         (print_insn_coprocessor): Handle new %C format control code.
 310
 311 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 312
 313         * arm-dis.c (enum isa): New enum.
 314         (struct sopcode32): New structure.
 315         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 316         set isa field of all current entries to ANY.
 317         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 318         Only match an entry if its isa field allows the current mode.
 319
 320 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 321
 322         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 323         CLRM.
 324         (print_insn_thumb32): Add logic to print %n CLRM register list.
 325
 326 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 327
 328         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 329         and %Q patterns.
 330
 331 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 332
 333         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 334         (print_insn_thumb32): Edit the switch case for %Z.
 335
 336 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 337
 338         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 339
 340 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 341
 342         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 343
 344 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 345
 346         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 347
 348 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 349
 350         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 351         Arm register with r13 and r15 unpredictable.
 352         (thumb32_opcodes): New instructions for bfx and bflx.
 353
 354 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 355
 356         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 357
 358 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 359
 360         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 361
 362 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 363
 364         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 365
 366 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 367
 368         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 369
 370 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 371
 372         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 373         "optr". ("operator" is a reserved word in c++).
 374
 375 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 376
 377         * aarch64-opc.c (aarch64_print_operand): Add case for
 378         AARCH64_OPND_Rt_SP.
 379         (verify_constraints): Likewise.
 380         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 381         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 382         to accept Rt|SP as first operand.
 383         (AARCH64_OPERANDS): Add new Rt_SP.
 384         * aarch64-asm-2.c: Regenerated.
 385         * aarch64-dis-2.c: Regenerated.
 386         * aarch64-opc-2.c: Regenerated.
 387
 388 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 389
 390         * aarch64-asm-2.c: Regenerated.
 391         * aarch64-dis-2.c: Likewise.
 392         * aarch64-opc-2.c: Likewise.
 393         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 394
 395 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 396
 397         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 398
 399 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 400
 401         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 402         * i386-init.h: Regenerated.
 403
 404 2019-04-07  Alan Modra  <amodra@gmail.com>
 405
 406         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 407         op_separator to control printing of spaces, comma and parens
 408         rather than need_comma, need_paren and spaces vars.
 409
 410 2019-04-07  Alan Modra  <amodra@gmail.com>
 411
 412         PR 24421
 413         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 414         (print_insn_neon, print_insn_arm): Likewise.
 415
 416 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 417
 418         * i386-dis-evex.h (evex_table): Updated to support BF16
 419         instructions.
 420         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 421         and EVEX_W_0F3872_P_3.
 422         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 423         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 424         * i386-opc.h (enum): Add CpuAVX512_BF16.
 425         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 426         * i386-opc.tbl: Add AVX512 BF16 instructions.
 427         * i386-init.h: Regenerated.
 428         * i386-tbl.h: Likewise.
 429
 430 2019-04-05  Alan Modra  <amodra@gmail.com>
 431
 432         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 433         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 434         to favour printing of "-" branch hint when using the "y" bit.
 435         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 436
 437 2019-04-05  Alan Modra  <amodra@gmail.com>
 438
 439         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 440         opcode until first operand is output.
 441
 442 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 443
 444         PR gas/24349
 445         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 446         (valid_bo_post_v2): Add support for 'at' branch hints.
 447         (insert_bo): Only error on branch on ctr.
 448         (get_bo_hint_mask): New function.
 449         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 450         for inserting 'at' branch hints.
 451         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 452         for extracting 'at' branch hints.
 453         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 454         (BOE): Delete operand.
 455         (BOM, BOP): New operands.
 456         (RM): Update value.
 457         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 458         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 459         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 460         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 461         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 462         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 463         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 464         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 465         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 466         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 467         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 468         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 469         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 470         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 471         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 472         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 473         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 474         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 475         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 476         bttarl+>: New extended mnemonics.
 477
 478 2019-03-28  Alan Modra  <amodra@gmail.com>
 479
 480         PR 24390
 481         * ppc-opc.c (BTF): Define.
 482         (powerpc_opcodes): Use for mtfsb*.
 483         * ppc-dis.c (print_insn_powerpc): Print fields with both
 484         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 485
 486 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 487
 488         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 489         (mapping_symbol_for_insn): Implement new algorithm.
 490         (print_insn): Remove duplicate code.
 491
 492 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 493
 494         * aarch64-dis.c (print_insn_aarch64):
 495         Implement override.
 496
 497 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 498
 499         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 500         order.
 501
 502 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 503
 504         * aarch64-dis.c (last_stop_offset): New.
 505         (print_insn_aarch64): Use stop_offset.
 506
 507 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 508
 509         PR gas/24359
 510         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 511         CPU_ANY_AVX2_FLAGS.
 512         * i386-init.h: Regenerated.
 513
 514 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 515
 516         PR gas/24348
 517         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 518         vmovdqu16, vmovdqu32 and vmovdqu64.
 519         * i386-tbl.h: Regenerated.
 520
 521 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 522
 523         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 524         from vstrszb, vstrszh, and vstrszf.
 525
 526 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 527
 528         * s390-opc.txt: Add instruction descriptions.
 529
 530 2019-02-08  Jim Wilson  <jimw@sifive.com>
 531
 532         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 533         <bne>: Likewise.
 534
 535 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 536
 537         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 538
 539 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 540
 541         PR binutils/23212
 542         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 543         * aarch64-opc.c (verify_elem_sd): New.
 544         (fields): Add FLD_sz entr.
 545         * aarch64-tbl.h (_SIMD_INSN): New.
 546         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 547         fmulx scalar and vector by element isns.
 548
 549 2019-02-07  Nick Clifton  <nickc@redhat.com>
 550
 551         * po/sv.po: Updated Swedish translation.
 552
 553 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 554
 555         * s390-mkopc.c (main): Accept arch13 as cpu string.
 556         * s390-opc.c: Add new instruction formats and instruction opcode
 557         masks.
 558         * s390-opc.txt: Add new arch13 instructions.
 559
 560 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 561
 562         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 563         (aarch64_opcode): Change encoding for stg, stzg
 564         st2g and st2zg.
 565         * aarch64-asm-2.c: Regenerated.
 566         * aarch64-dis-2.c: Regenerated.
 567         * aarch64-opc-2.c: Regenerated.
 568
 569 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 570
 571         * aarch64-asm-2.c: Regenerated.
 572         * aarch64-dis-2.c: Likewise.
 573         * aarch64-opc-2.c: Likewise.
 574         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 575
 576 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 577             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 578
 579         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 580         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 581         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 582         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 583         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 584         case for ldstgv_indexed.
 585         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 586         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 587         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 588         * aarch64-asm-2.c: Regenerated.
 589         * aarch64-dis-2.c: Regenerated.
 590         * aarch64-opc-2.c: Regenerated.
 591
 592 2019-01-23  Nick Clifton  <nickc@redhat.com>
 593
 594         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 595
 596 2019-01-21  Nick Clifton  <nickc@redhat.com>
 597
 598         * po/de.po: Updated German translation.
 599         * po/uk.po: Updated Ukranian translation.
 600
 601 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 602         * mips-dis.c (mips_arch_choices): Fix typo in
 603         gs464, gs464e and gs264e descriptors.
 604
 605 2019-01-19  Nick Clifton  <nickc@redhat.com>
 606
 607         * configure: Regenerate.
 608         * po/opcodes.pot: Regenerate.
 609
 610 2018-06-24  Nick Clifton  <nickc@redhat.com>
 611
 612         2.32 branch created.
 613
 614 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 615
 616         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 617         if it is null.
 618         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 619         zero.
 620
 621 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 622
 623         * configure: Regenerate.
 624
 625 2019-01-07  Alan Modra  <amodra@gmail.com>
 626
 627         * configure: Regenerate.
 628         * po/POTFILES.in: Regenerate.
 629
 630 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 631
 632         * s12z-opc.c: New file.
 633         * s12z-opc.h: New file.
 634         * s12z-dis.c: Removed all code not directly related to display
 635         of instructions.  Used the interface provided by the new files
 636         instead.
 637         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 638         * Makefile.in: Regenerate.
 639         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 640         * configure: Regenerate.
 641
 642 2019-01-01  Alan Modra  <amodra@gmail.com>
 643
 644         Update year range in copyright notice of all files.
 645
 646 For older changes see ChangeLog-2018
 647 \f
 648 Copyright (C) 2019 Free Software Foundation, Inc.
 649
 650 Copying and distribution of this file, with or without modification,
 651 are permitted in any medium without royalty provided the copyright
 652 notice and this notice are preserved.
 653
 654 Local Variables:
 655 mode: change-log
 656 left-margin: 8
 657 fill-column: 74
 658 version-control: never
 659 End: