opcodes/ChangeLog

   1 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
   4         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
   5         "sync_rmb" and "sync_wmb" as aliases.
   6         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
   7         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
   8
   9 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
  10
  11         * arc-dis.c (parse_option): Update quarkse_em option..
  12         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
  13         QUARKSE1.
  14         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
  15
  16 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
  17
  18         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
  19
  20 2017-05-01  Michael Clark  <michaeljclark@mac.com>
  21
  22         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
  23         register.
  24
  25 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
  26
  27         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
  28         and branches and not synthetic data instructions.
  29
  30 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
  31
  32         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
  33
  34 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
  35
  36         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
  37         * arc-opc.c (insert_r13el): New function.
  38         (R13_EL): Define.
  39         * arc-tbl.h: Add new enter/leave variants.
  40
  41 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
  42
  43         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
  44
  45 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
  46
  47         * mips-dis.c (print_mips_disassembler_options): Add
  48         `no-aliases'.
  49
  50 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
  51
  52         * mips16-opc.c (AL): New macro.
  53         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
  54         of "ld" and "lw" as aliases.
  55
  56 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
  57
  58         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
  59         arguments.
  60
  61 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
  62             Alan Modra  <amodra@gmail.com>
  63
  64         * ppc-opc.c (ELEV): Define.
  65         (vle_opcodes): Add se_rfgi and e_sc.
  66         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
  67         for E200Z4.
  68
  69 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  70
  71         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
  72
  73 2017-04-21  Nick Clifton  <nickc@redhat.com>
  74
  75         PR binutils/21380
  76         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
  77         LD3R and LD4R.
  78
  79 2017-04-13  Alan Modra  <amodra@gmail.com>
  80
  81         * epiphany-desc.c: Regenerate.
  82         * fr30-desc.c: Regenerate.
  83         * frv-desc.c: Regenerate.
  84         * ip2k-desc.c: Regenerate.
  85         * iq2000-desc.c: Regenerate.
  86         * lm32-desc.c: Regenerate.
  87         * m32c-desc.c: Regenerate.
  88         * m32r-desc.c: Regenerate.
  89         * mep-desc.c: Regenerate.
  90         * mt-desc.c: Regenerate.
  91         * or1k-desc.c: Regenerate.
  92         * xc16x-desc.c: Regenerate.
  93         * xstormy16-desc.c: Regenerate.
  94
  95 2017-04-11  Alan Modra  <amodra@gmail.com>
  96
  97         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
  98         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
  99         PPC_OPCODE_TMR for e6500.
 100         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 101         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 102         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 103         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 104         (PPCHTM): Define as PPC_OPCODE_POWER8.
 105         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 106
 107 2017-04-10  Alan Modra  <amodra@gmail.com>
 108
 109         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 110         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 111         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 112         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 113
 114 2017-04-09  Pip Cet  <pipcet@gmail.com>
 115
 116         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 117         appropriate floating-point precision directly.
 118
 119 2017-04-07  Alan Modra  <amodra@gmail.com>
 120
 121         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 122         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 123         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 124         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 125         vector instructions with E6500 not PPCVEC2.
 126
 127 2017-04-06  Pip Cet  <pipcet@gmail.com>
 128
 129         * Makefile.am: Add wasm32-dis.c.
 130         * configure.ac: Add wasm32-dis.c to wasm32 target.
 131         * disassemble.c: Add wasm32 disassembler code.
 132         * wasm32-dis.c: New file.
 133         * Makefile.in: Regenerate.
 134         * configure: Regenerate.
 135         * po/POTFILES.in: Regenerate.
 136         * po/opcodes.pot: Regenerate.
 137
 138 2017-04-05  Pedro Alves  <palves@redhat.com>
 139
 140         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 141         * arm-dis.c (parse_arm_disassembler_options): Constify.
 142         * ppc-dis.c (powerpc_init_dialect): Constify local.
 143         * vax-dis.c (parse_disassembler_options): Constify.
 144
 145 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 146
 147         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 148         RISCV_GP_SYMBOL.
 149
 150 2017-03-30  Pip Cet  <pipcet@gmail.com>
 151
 152         * configure.ac: Add (empty) bfd_wasm32_arch target.
 153         * configure: Regenerate
 154         * po/opcodes.pot: Regenerate.
 155
 156 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 157
 158         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 159         OSA2015.
 160         * opcodes/sparc-opc.c (asi_table): New ASIs.
 161
 162 2017-03-29  Alan Modra  <amodra@gmail.com>
 163
 164         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 165         "raw" option.
 166         (lookup_powerpc): Don't special case -1 dialect.  Handle
 167         PPC_OPCODE_RAW.
 168         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 169         lookup_powerpc call, pass it on second.
 170
 171 2017-03-27  Alan Modra  <amodra@gmail.com>
 172
 173         PR 21303
 174         * ppc-dis.c (struct ppc_mopt): Comment.
 175         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 176
 177 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 178
 179         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 180         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 181         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 182         (insert_nps_misc_imm_offset): New function.
 183         (extract_nps_misc imm_offset): New function.
 184         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 185         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 186
 187 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 188
 189         * s390-mkopc.c (main): Remove vx2 check.
 190         * s390-opc.txt: Remove vx2 instruction flags.
 191
 192 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 193
 194         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 195         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 196         (insert_nps_imm_offset): New function.
 197         (extract_nps_imm_offset): New function.
 198         (insert_nps_imm_entry): New function.
 199         (extract_nps_imm_entry): New function.
 200
 201 2017-03-17  Alan Modra  <amodra@gmail.com>
 202
 203         PR 21248
 204         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 205         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 206         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 207
 208 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 209
 210         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 211         <c.andi>: Likewise.
 212         <c.addiw> Likewise.
 213
 214 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 215
 216         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 217
 218 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 219
 220         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 221         <srl> Likewise.
 222         <srai> Likewise.
 223         <sra> Likewise.
 224
 225 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 226
 227         * i386-gen.c (opcode_modifiers): Replace S with Load.
 228         * i386-opc.h (S): Removed.
 229         (Load): New.
 230         (i386_opcode_modifier): Replace s with load.
 231         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 232         and {evex}.  Replace S with Load.
 233         * i386-tbl.h: Regenerated.
 234
 235 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 236
 237         * i386-opc.tbl: Use CpuCET on rdsspq.
 238         * i386-tbl.h: Regenerated.
 239
 240 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 241
 242         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 243         <vsx>: Do not use PPC_OPCODE_VSX3;
 244
 245 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 246
 247         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 248
 249 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 250
 251         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 252         (MOD_0F1E_PREFIX_1): Likewise.
 253         (MOD_0F38F5_PREFIX_2): Likewise.
 254         (MOD_0F38F6_PREFIX_0): Likewise.
 255         (RM_0F1E_MOD_3_REG_7): Likewise.
 256         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 257         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 258         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 259         (PREFIX_0F1E): Likewise.
 260         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 261         (PREFIX_0F38F5): Likewise.
 262         (dis386_twobyte): Use PREFIX_0F1E.
 263         (reg_table): Add REG_0F1E_MOD_3.
 264         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 265         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 266         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 267         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 268         (three_byte_table): Use PREFIX_0F38F5.
 269         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 270         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 271         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 272         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 273         PREFIX_MOD_3_0F01_REG_5_RM_2.
 274         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 275         (cpu_flags): Add CpuCET.
 276         * i386-opc.h (CpuCET): New enum.
 277         (CpuUnused): Commented out.
 278         (i386_cpu_flags): Add cpucet.
 279         * i386-opc.tbl: Add Intel CET instructions.
 280         * i386-init.h: Regenerated.
 281         * i386-tbl.h: Likewise.
 282
 283 2017-03-06  Alan Modra  <amodra@gmail.com>
 284
 285         PR 21124
 286         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 287         (extract_raq, extract_ras, extract_rbx): New functions.
 288         (powerpc_operands): Use opposite corresponding insert function.
 289         (Q_MASK): Define.
 290         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 291         register restriction.
 292
 293 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 294
 295         * disassemble.c Include "safe-ctype.h".
 296         (disassemble_init_for_target): Handle s390 init.
 297         (remove_whitespace_and_extra_commas): New function.
 298         (disassembler_options_cmp): Likewise.
 299         * arm-dis.c: Include "libiberty.h".
 300         (NUM_ELEM): Delete.
 301         (regnames): Use long disassembler style names.
 302         Add force-thumb and no-force-thumb options.
 303         (NUM_ARM_REGNAMES): Rename from this...
 304         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 305         (get_arm_regname_num_options): Delete.
 306         (set_arm_regname_option): Likewise.
 307         (get_arm_regnames): Likewise.
 308         (parse_disassembler_options): Likewise.
 309         (parse_arm_disassembler_option): Rename from this...
 310         (parse_arm_disassembler_options): ...to this.  Make static.
 311         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 312         (print_insn): Use parse_arm_disassembler_options.
 313         (disassembler_options_arm): New function.
 314         (print_arm_disassembler_options): Handle updated regnames.
 315         * ppc-dis.c: Include "libiberty.h".
 316         (ppc_opts): Add "32" and "64" entries.
 317         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 318         (powerpc_init_dialect): Add break to switch statement.
 319         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 320         (disassembler_options_powerpc): New function.
 321         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 322         Remove printing of "32" and "64".
 323         * s390-dis.c: Include "libiberty.h".
 324         (init_flag): Remove unneeded variable.
 325         (struct s390_options_t): New structure type.
 326         (options): New structure.
 327         (init_disasm): Rename from this...
 328         (disassemble_init_s390): ...to this.  Add initializations for
 329         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 330         (print_insn_s390): Delete call to init_disasm.
 331         (disassembler_options_s390): New function.
 332         (print_s390_disassembler_options): Print using information from
 333         struct 'options'.
 334         * po/opcodes.pot: Regenerate.
 335
 336 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-dis.c (PCMPESTR_Fixup): New.
 339         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 340         (prefix_table): Use PCMPESTR_Fixup.
 341         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 342         PCMPESTR_Fixup.
 343         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 344         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 345         Split 64-bit and non-64-bit variants.
 346         * opcodes/i386-tbl.h: Re-generate.
 347
 348 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 349
 350         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 351         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 352         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 353         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 354         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 355         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 356         (OP_SVE_V_HSD): New macros.
 357         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 358         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 359         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 360         (aarch64_opcode_table): Add new SVE instructions.
 361         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 362         for rotation operands.  Add new SVE operands.
 363         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 364         (ins_sve_quad_index): Likewise.
 365         (ins_imm_rotate): Split into...
 366         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 367         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 368         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 369         functions.
 370         (aarch64_ins_sve_addr_ri_s4): New function.
 371         (aarch64_ins_sve_quad_index): Likewise.
 372         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 373         * aarch64-asm-2.c: Regenerate.
 374         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 375         (ext_sve_quad_index): Likewise.
 376         (ext_imm_rotate): Split into...
 377         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 378         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 379         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 380         functions.
 381         (aarch64_ext_sve_addr_ri_s4): New function.
 382         (aarch64_ext_sve_quad_index): Likewise.
 383         (aarch64_ext_sve_index): Allow quad indices.
 384         (do_misc_decoding): Likewise.
 385         * aarch64-dis-2.c: Regenerate.
 386         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 387         aarch64_field_kinds.
 388         (OPD_F_OD_MASK): Widen by one bit.
 389         (OPD_F_NO_ZR): Bump accordingly.
 390         (get_operand_field_width): New function.
 391         * aarch64-opc.c (fields): Add new SVE fields.
 392         (operand_general_constraint_met_p): Handle new SVE operands.
 393         (aarch64_print_operand): Likewise.
 394         * aarch64-opc-2.c: Regenerate.
 395
 396 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 397
 398         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 399         (aarch64_feature_compnum): ...this.
 400         (SIMD_V8_3): Replace with...
 401         (COMPNUM): ...this.
 402         (CNUM_INSN): New macro.
 403         (aarch64_opcode_table): Use it for the complex number instructions.
 404
 405 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 406
 407         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 408
 409 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 410
 411         Add support for associating SPARC ASIs with an architecture level.
 412         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 413         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 414         decoding of SPARC ASIs.
 415
 416 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 417
 418         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 419         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 420
 421 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 422
 423         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 424         1 (instead of to itself). Correct typo.
 425
 426 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 427
 428         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 429         pseudoinstructions.
 430
 431 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 432
 433         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 434         (aarch64_sys_reg_supported_p): Handle them.
 435
 436 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 437
 438         * arc-opc.c (UIMM6_20R): Define.
 439         (SIMM12_20): Use above.
 440         (SIMM12_20R): Define.
 441         (SIMM3_5_S): Use above.
 442         (UIMM7_A32_11R_S): Define.
 443         (UIMM7_9_S): Use above.
 444         (UIMM3_13R_S): Define.
 445         (SIMM11_A32_7_S): Use above.
 446         (SIMM9_8R): Define.
 447         (UIMM10_A32_8_S): Use above.
 448         (UIMM8_8R_S): Define.
 449         (W6): Use above.
 450         (arc_relax_opcodes): Use all above defines.
 451
 452 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 453
 454         * arc-regs.h: Distinguish some of the registers different on
 455         ARC700 and HS38 cpus.
 456
 457 2017-02-14  Alan Modra  <amodra@gmail.com>
 458
 459         PR 21118
 460         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 461         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 462
 463 2017-02-11  Stafford Horne  <shorne@gmail.com>
 464             Alan Modra  <amodra@gmail.com>
 465
 466         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 467         Use insn_bytes_value and insn_int_value directly instead.  Don't
 468         free allocated memory until function exit.
 469
 470 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 471
 472         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 473
 474 2017-02-03  Nick Clifton  <nickc@redhat.com>
 475
 476         PR 21096
 477         * aarch64-opc.c (print_register_list): Ensure that the register
 478         list index will fir into the tb buffer.
 479         (print_register_offset_address): Likewise.
 480         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 481
 482 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 483
 484         PR 21056
 485         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 486         instructions when the previous fetch packet ends with a 32-bit
 487         instruction.
 488
 489 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 490
 491         * pru-opc.c: Remove vague reference to a future GDB port.
 492
 493 2017-01-20  Nick Clifton  <nickc@redhat.com>
 494
 495         * po/ga.po: Updated Irish translation.
 496
 497 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 498
 499         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 500
 501 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 502
 503         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 504         if FETCH_DATA returns 0.
 505         (m68k_scan_mask): Likewise.
 506         (print_insn_m68k): Update code to handle -1 return value.
 507
 508 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 509
 510         * m68k-dis.c (enum print_insn_arg_error): New.
 511         (NEXTBYTE): Replace -3 with
 512         PRINT_INSN_ARG_MEMORY_ERROR.
 513         (NEXTULONG): Likewise.
 514         (NEXTSINGLE): Likewise.
 515         (NEXTDOUBLE): Likewise.
 516         (NEXTDOUBLE): Likewise.
 517         (NEXTPACKED): Likewise.
 518         (FETCH_ARG): Likewise.
 519         (FETCH_DATA): Update comments.
 520         (print_insn_arg): Update comments. Replace magic numbers with
 521         enum.
 522         (match_insn_m68k): Likewise.
 523
 524 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 525
 526         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 527         * i386-dis-evex.h (evex_table): Updated.
 528         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 529         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 530         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 531         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 532         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 533         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 534         * i386-init.h: Regenerate.
 535         * i386-tbl.h: Ditto.
 536
 537 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 538
 539         * msp430-dis.c (msp430_singleoperand): Return -1 if
 540         msp430dis_opcode_signed returns false.
 541         (msp430_doubleoperand): Likewise.
 542         (msp430_branchinstr): Return -1 if
 543         msp430dis_opcode_unsigned returns false.
 544         (msp430x_calla_instr): Likewise.
 545         (print_insn_msp430): Likewise.
 546
 547 2017-01-05  Nick Clifton  <nickc@redhat.com>
 548
 549         PR 20946
 550         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 551         could not be matched.
 552         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 553         NULL.
 554
 555 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 556
 557         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 558         (aarch64_opcode_table): Use RCPC_INSN.
 559
 560 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 561
 562         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 563         extension.
 564         * riscv-opcodes/all-opcodes: Likewise.
 565
 566 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 567
 568         * riscv-dis.c (print_insn_args): Add fall through comment.
 569
 570 2017-01-03  Nick Clifton  <nickc@redhat.com>
 571
 572         * po/sr.po: New Serbian translation.
 573         * configure.ac (ALL_LINGUAS): Add sr.
 574         * configure: Regenerate.
 575
 576 2017-01-02  Alan Modra  <amodra@gmail.com>
 577
 578         * epiphany-desc.h: Regenerate.
 579         * epiphany-opc.h: Regenerate.
 580         * fr30-desc.h: Regenerate.
 581         * fr30-opc.h: Regenerate.
 582         * frv-desc.h: Regenerate.
 583         * frv-opc.h: Regenerate.
 584         * ip2k-desc.h: Regenerate.
 585         * ip2k-opc.h: Regenerate.
 586         * iq2000-desc.h: Regenerate.
 587         * iq2000-opc.h: Regenerate.
 588         * lm32-desc.h: Regenerate.
 589         * lm32-opc.h: Regenerate.
 590         * m32c-desc.h: Regenerate.
 591         * m32c-opc.h: Regenerate.
 592         * m32r-desc.h: Regenerate.
 593         * m32r-opc.h: Regenerate.
 594         * mep-desc.h: Regenerate.
 595         * mep-opc.h: Regenerate.
 596         * mt-desc.h: Regenerate.
 597         * mt-opc.h: Regenerate.
 598         * or1k-desc.h: Regenerate.
 599         * or1k-opc.h: Regenerate.
 600         * xc16x-desc.h: Regenerate.
 601         * xc16x-opc.h: Regenerate.
 602         * xstormy16-desc.h: Regenerate.
 603         * xstormy16-opc.h: Regenerate.
 604
 605 2017-01-02  Alan Modra  <amodra@gmail.com>
 606
 607         Update year range in copyright notice of all files.
 608
 609 For older changes see ChangeLog-2016
 610 \f
 611 Copyright (C) 2017 Free Software Foundation, Inc.
 612
 613 Copying and distribution of this file, with or without modification,
 614 are permitted in any medium without royalty provided the copyright
 615 notice and this notice are preserved.
 616
 617 Local Variables:
 618 mode: change-log
 619 left-margin: 8
 620 fill-column: 74
 621 version-control: never
 622 End: