opcodes/ChangeLog

   1 2017-04-11  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2.
   4         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
   5         (PPCVEC3): Define as PPC_OPCODE_POWER9.
   6
   7 2017-04-10  Alan Modra  <amodra@gmail.com>
   8
   9         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
  10         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
  11         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
  12         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
  13
  14 2017-04-09  Pip Cet  <pipcet@gmail.com>
  15
  16         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
  17         appropriate floating-point precision directly.
  18
  19 2017-04-07  Alan Modra  <amodra@gmail.com>
  20
  21         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
  22         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
  23         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
  24         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
  25         vector instructions with E6500 not PPCVEC2.
  26
  27 2017-04-06  Pip Cet  <pipcet@gmail.com>
  28
  29         * Makefile.am: Add wasm32-dis.c.
  30         * configure.ac: Add wasm32-dis.c to wasm32 target.
  31         * disassemble.c: Add wasm32 disassembler code.
  32         * wasm32-dis.c: New file.
  33         * Makefile.in: Regenerate.
  34         * configure: Regenerate.
  35         * po/POTFILES.in: Regenerate.
  36         * po/opcodes.pot: Regenerate.
  37
  38 2017-04-05  Pedro Alves  <palves@redhat.com>
  39
  40         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
  41         * arm-dis.c (parse_arm_disassembler_options): Constify.
  42         * ppc-dis.c (powerpc_init_dialect): Constify local.
  43         * vax-dis.c (parse_disassembler_options): Constify.
  44
  45 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
  46
  47         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
  48         RISCV_GP_SYMBOL.
  49
  50 2017-03-30  Pip Cet  <pipcet@gmail.com>
  51
  52         * configure.ac: Add (empty) bfd_wasm32_arch target.
  53         * configure: Regenerate
  54         * po/opcodes.pot: Regenerate.
  55
  56 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
  57
  58         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
  59         OSA2015.
  60         * opcodes/sparc-opc.c (asi_table): New ASIs.
  61
  62 2017-03-29  Alan Modra  <amodra@gmail.com>
  63
  64         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
  65         "raw" option.
  66         (lookup_powerpc): Don't special case -1 dialect.  Handle
  67         PPC_OPCODE_RAW.
  68         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
  69         lookup_powerpc call, pass it on second.
  70
  71 2017-03-27  Alan Modra  <amodra@gmail.com>
  72
  73         PR 21303
  74         * ppc-dis.c (struct ppc_mopt): Comment.
  75         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
  76
  77 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
  78
  79         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
  80         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
  81         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
  82         (insert_nps_misc_imm_offset): New function.
  83         (extract_nps_misc imm_offset): New function.
  84         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
  85         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
  86
  87 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  88
  89         * s390-mkopc.c (main): Remove vx2 check.
  90         * s390-opc.txt: Remove vx2 instruction flags.
  91
  92 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
  93
  94         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
  95         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
  96         (insert_nps_imm_offset): New function.
  97         (extract_nps_imm_offset): New function.
  98         (insert_nps_imm_entry): New function.
  99         (extract_nps_imm_entry): New function.
 100
 101 2017-03-17  Alan Modra  <amodra@gmail.com>
 102
 103         PR 21248
 104         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 105         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 106         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 107
 108 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 109
 110         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 111         <c.andi>: Likewise.
 112         <c.addiw> Likewise.
 113
 114 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 115
 116         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 117
 118 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 119
 120         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 121         <srl> Likewise.
 122         <srai> Likewise.
 123         <sra> Likewise.
 124
 125 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 126
 127         * i386-gen.c (opcode_modifiers): Replace S with Load.
 128         * i386-opc.h (S): Removed.
 129         (Load): New.
 130         (i386_opcode_modifier): Replace s with load.
 131         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 132         and {evex}.  Replace S with Load.
 133         * i386-tbl.h: Regenerated.
 134
 135 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 136
 137         * i386-opc.tbl: Use CpuCET on rdsspq.
 138         * i386-tbl.h: Regenerated.
 139
 140 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 141
 142         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 143         <vsx>: Do not use PPC_OPCODE_VSX3;
 144
 145 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 146
 147         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 148
 149 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 150
 151         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 152         (MOD_0F1E_PREFIX_1): Likewise.
 153         (MOD_0F38F5_PREFIX_2): Likewise.
 154         (MOD_0F38F6_PREFIX_0): Likewise.
 155         (RM_0F1E_MOD_3_REG_7): Likewise.
 156         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 157         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 158         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 159         (PREFIX_0F1E): Likewise.
 160         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 161         (PREFIX_0F38F5): Likewise.
 162         (dis386_twobyte): Use PREFIX_0F1E.
 163         (reg_table): Add REG_0F1E_MOD_3.
 164         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 165         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 166         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 167         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 168         (three_byte_table): Use PREFIX_0F38F5.
 169         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 170         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 171         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 172         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 173         PREFIX_MOD_3_0F01_REG_5_RM_2.
 174         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 175         (cpu_flags): Add CpuCET.
 176         * i386-opc.h (CpuCET): New enum.
 177         (CpuUnused): Commented out.
 178         (i386_cpu_flags): Add cpucet.
 179         * i386-opc.tbl: Add Intel CET instructions.
 180         * i386-init.h: Regenerated.
 181         * i386-tbl.h: Likewise.
 182
 183 2017-03-06  Alan Modra  <amodra@gmail.com>
 184
 185         PR 21124
 186         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 187         (extract_raq, extract_ras, extract_rbx): New functions.
 188         (powerpc_operands): Use opposite corresponding insert function.
 189         (Q_MASK): Define.
 190         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 191         register restriction.
 192
 193 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 194
 195         * disassemble.c Include "safe-ctype.h".
 196         (disassemble_init_for_target): Handle s390 init.
 197         (remove_whitespace_and_extra_commas): New function.
 198         (disassembler_options_cmp): Likewise.
 199         * arm-dis.c: Include "libiberty.h".
 200         (NUM_ELEM): Delete.
 201         (regnames): Use long disassembler style names.
 202         Add force-thumb and no-force-thumb options.
 203         (NUM_ARM_REGNAMES): Rename from this...
 204         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 205         (get_arm_regname_num_options): Delete.
 206         (set_arm_regname_option): Likewise.
 207         (get_arm_regnames): Likewise.
 208         (parse_disassembler_options): Likewise.
 209         (parse_arm_disassembler_option): Rename from this...
 210         (parse_arm_disassembler_options): ...to this.  Make static.
 211         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 212         (print_insn): Use parse_arm_disassembler_options.
 213         (disassembler_options_arm): New function.
 214         (print_arm_disassembler_options): Handle updated regnames.
 215         * ppc-dis.c: Include "libiberty.h".
 216         (ppc_opts): Add "32" and "64" entries.
 217         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 218         (powerpc_init_dialect): Add break to switch statement.
 219         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 220         (disassembler_options_powerpc): New function.
 221         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 222         Remove printing of "32" and "64".
 223         * s390-dis.c: Include "libiberty.h".
 224         (init_flag): Remove unneeded variable.
 225         (struct s390_options_t): New structure type.
 226         (options): New structure.
 227         (init_disasm): Rename from this...
 228         (disassemble_init_s390): ...to this.  Add initializations for
 229         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 230         (print_insn_s390): Delete call to init_disasm.
 231         (disassembler_options_s390): New function.
 232         (print_s390_disassembler_options): Print using information from
 233         struct 'options'.
 234         * po/opcodes.pot: Regenerate.
 235
 236 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 237
 238         * i386-dis.c (PCMPESTR_Fixup): New.
 239         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 240         (prefix_table): Use PCMPESTR_Fixup.
 241         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 242         PCMPESTR_Fixup.
 243         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 244         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 245         Split 64-bit and non-64-bit variants.
 246         * opcodes/i386-tbl.h: Re-generate.
 247
 248 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 249
 250         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 251         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 252         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 253         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 254         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 255         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 256         (OP_SVE_V_HSD): New macros.
 257         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 258         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 259         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 260         (aarch64_opcode_table): Add new SVE instructions.
 261         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 262         for rotation operands.  Add new SVE operands.
 263         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 264         (ins_sve_quad_index): Likewise.
 265         (ins_imm_rotate): Split into...
 266         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 267         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 268         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 269         functions.
 270         (aarch64_ins_sve_addr_ri_s4): New function.
 271         (aarch64_ins_sve_quad_index): Likewise.
 272         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 273         * aarch64-asm-2.c: Regenerate.
 274         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 275         (ext_sve_quad_index): Likewise.
 276         (ext_imm_rotate): Split into...
 277         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 278         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 279         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 280         functions.
 281         (aarch64_ext_sve_addr_ri_s4): New function.
 282         (aarch64_ext_sve_quad_index): Likewise.
 283         (aarch64_ext_sve_index): Allow quad indices.
 284         (do_misc_decoding): Likewise.
 285         * aarch64-dis-2.c: Regenerate.
 286         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 287         aarch64_field_kinds.
 288         (OPD_F_OD_MASK): Widen by one bit.
 289         (OPD_F_NO_ZR): Bump accordingly.
 290         (get_operand_field_width): New function.
 291         * aarch64-opc.c (fields): Add new SVE fields.
 292         (operand_general_constraint_met_p): Handle new SVE operands.
 293         (aarch64_print_operand): Likewise.
 294         * aarch64-opc-2.c: Regenerate.
 295
 296 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 297
 298         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 299         (aarch64_feature_compnum): ...this.
 300         (SIMD_V8_3): Replace with...
 301         (COMPNUM): ...this.
 302         (CNUM_INSN): New macro.
 303         (aarch64_opcode_table): Use it for the complex number instructions.
 304
 305 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 308
 309 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 310
 311         Add support for associating SPARC ASIs with an architecture level.
 312         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 313         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 314         decoding of SPARC ASIs.
 315
 316 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 317
 318         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 319         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 320
 321 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 322
 323         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 324         1 (instead of to itself). Correct typo.
 325
 326 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 327
 328         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 329         pseudoinstructions.
 330
 331 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 332
 333         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 334         (aarch64_sys_reg_supported_p): Handle them.
 335
 336 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 337
 338         * arc-opc.c (UIMM6_20R): Define.
 339         (SIMM12_20): Use above.
 340         (SIMM12_20R): Define.
 341         (SIMM3_5_S): Use above.
 342         (UIMM7_A32_11R_S): Define.
 343         (UIMM7_9_S): Use above.
 344         (UIMM3_13R_S): Define.
 345         (SIMM11_A32_7_S): Use above.
 346         (SIMM9_8R): Define.
 347         (UIMM10_A32_8_S): Use above.
 348         (UIMM8_8R_S): Define.
 349         (W6): Use above.
 350         (arc_relax_opcodes): Use all above defines.
 351
 352 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 353
 354         * arc-regs.h: Distinguish some of the registers different on
 355         ARC700 and HS38 cpus.
 356
 357 2017-02-14  Alan Modra  <amodra@gmail.com>
 358
 359         PR 21118
 360         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 361         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 362
 363 2017-02-11  Stafford Horne  <shorne@gmail.com>
 364             Alan Modra  <amodra@gmail.com>
 365
 366         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 367         Use insn_bytes_value and insn_int_value directly instead.  Don't
 368         free allocated memory until function exit.
 369
 370 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 371
 372         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 373
 374 2017-02-03  Nick Clifton  <nickc@redhat.com>
 375
 376         PR 21096
 377         * aarch64-opc.c (print_register_list): Ensure that the register
 378         list index will fir into the tb buffer.
 379         (print_register_offset_address): Likewise.
 380         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 381
 382 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 383
 384         PR 21056
 385         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 386         instructions when the previous fetch packet ends with a 32-bit
 387         instruction.
 388
 389 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 390
 391         * pru-opc.c: Remove vague reference to a future GDB port.
 392
 393 2017-01-20  Nick Clifton  <nickc@redhat.com>
 394
 395         * po/ga.po: Updated Irish translation.
 396
 397 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 398
 399         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 400
 401 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 402
 403         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 404         if FETCH_DATA returns 0.
 405         (m68k_scan_mask): Likewise.
 406         (print_insn_m68k): Update code to handle -1 return value.
 407
 408 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 409
 410         * m68k-dis.c (enum print_insn_arg_error): New.
 411         (NEXTBYTE): Replace -3 with
 412         PRINT_INSN_ARG_MEMORY_ERROR.
 413         (NEXTULONG): Likewise.
 414         (NEXTSINGLE): Likewise.
 415         (NEXTDOUBLE): Likewise.
 416         (NEXTDOUBLE): Likewise.
 417         (NEXTPACKED): Likewise.
 418         (FETCH_ARG): Likewise.
 419         (FETCH_DATA): Update comments.
 420         (print_insn_arg): Update comments. Replace magic numbers with
 421         enum.
 422         (match_insn_m68k): Likewise.
 423
 424 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 425
 426         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 427         * i386-dis-evex.h (evex_table): Updated.
 428         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 429         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 430         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 431         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 432         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 433         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 434         * i386-init.h: Regenerate.
 435         * i386-tbl.h: Ditto.
 436
 437 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 438
 439         * msp430-dis.c (msp430_singleoperand): Return -1 if
 440         msp430dis_opcode_signed returns false.
 441         (msp430_doubleoperand): Likewise.
 442         (msp430_branchinstr): Return -1 if
 443         msp430dis_opcode_unsigned returns false.
 444         (msp430x_calla_instr): Likewise.
 445         (print_insn_msp430): Likewise.
 446
 447 2017-01-05  Nick Clifton  <nickc@redhat.com>
 448
 449         PR 20946
 450         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 451         could not be matched.
 452         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 453         NULL.
 454
 455 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 456
 457         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 458         (aarch64_opcode_table): Use RCPC_INSN.
 459
 460 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 461
 462         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 463         extension.
 464         * riscv-opcodes/all-opcodes: Likewise.
 465
 466 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 467
 468         * riscv-dis.c (print_insn_args): Add fall through comment.
 469
 470 2017-01-03  Nick Clifton  <nickc@redhat.com>
 471
 472         * po/sr.po: New Serbian translation.
 473         * configure.ac (ALL_LINGUAS): Add sr.
 474         * configure: Regenerate.
 475
 476 2017-01-02  Alan Modra  <amodra@gmail.com>
 477
 478         * epiphany-desc.h: Regenerate.
 479         * epiphany-opc.h: Regenerate.
 480         * fr30-desc.h: Regenerate.
 481         * fr30-opc.h: Regenerate.
 482         * frv-desc.h: Regenerate.
 483         * frv-opc.h: Regenerate.
 484         * ip2k-desc.h: Regenerate.
 485         * ip2k-opc.h: Regenerate.
 486         * iq2000-desc.h: Regenerate.
 487         * iq2000-opc.h: Regenerate.
 488         * lm32-desc.h: Regenerate.
 489         * lm32-opc.h: Regenerate.
 490         * m32c-desc.h: Regenerate.
 491         * m32c-opc.h: Regenerate.
 492         * m32r-desc.h: Regenerate.
 493         * m32r-opc.h: Regenerate.
 494         * mep-desc.h: Regenerate.
 495         * mep-opc.h: Regenerate.
 496         * mt-desc.h: Regenerate.
 497         * mt-opc.h: Regenerate.
 498         * or1k-desc.h: Regenerate.
 499         * or1k-opc.h: Regenerate.
 500         * xc16x-desc.h: Regenerate.
 501         * xc16x-opc.h: Regenerate.
 502         * xstormy16-desc.h: Regenerate.
 503         * xstormy16-opc.h: Regenerate.
 504
 505 2017-01-02  Alan Modra  <amodra@gmail.com>
 506
 507         Update year range in copyright notice of all files.
 508
 509 For older changes see ChangeLog-2016
 510 \f
 511 Copyright (C) 2017 Free Software Foundation, Inc.
 512
 513 Copying and distribution of this file, with or without modification,
 514 are permitted in any medium without royalty provided the copyright
 515 notice and this notice are preserved.
 516
 517 Local Variables:
 518 mode: change-log
 519 left-margin: 8
 520 fill-column: 74
 521 version-control: never
 522 End: