opcodes/ChangeLog

   1 2010-10-02  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/12076
   4         * i386-dis.c (RMAL): Remove duplicate.
   5
   6 2010-09-30  Pierre Muller  <muller@ics.u-strasbg.fr>
   7
   8         * s390-mkopc.c (main): Exit with error 1 if sscanf fails
   9         to parse all 6 parameters.
  10
  11 2010-09-28  Pierre Muller  <muller@ics.u-strasbg.fr>
  12
  13         * s390-mkopc.c (main): Change description array size to 80.
  14         Add maximum length of 79 to description parsing.
  15
  16 2010-09-27  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
  17
  18         * configure: Regenerate.
  19
  20 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  21
  22         * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
  23         (main): Recognize the new CPU string.
  24         * s390-opc.c: Add new instruction formats and masks.
  25         * s390-opc.txt: Add new z196 instructions.
  26
  27 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  28
  29         * s390-dis.c (print_insn_s390): Pick instruction with most
  30         specific mask.
  31         * s390-opc.c: Add unused bits to the insn mask.
  32         * s390-opc.txt: Reorder some instructions to prefer more recent
  33         versions.
  34
  35 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
  36
  37         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
  38         correction to unaligned PCs while printing comment.
  39
  40 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  41
  42         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
  43         (thumb32_opcodes): Likewise.
  44         (banked_regname): New function.
  45         (print_insn_arm): Add Virtualization Extensions support.
  46         (print_insn_thumb32): Likewise.
  47
  48 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  49
  50         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
  51         ARM state.
  52
  53 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  54
  55         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
  56         (thumb32_opcodes): Likewise.
  57
  58 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  59
  60         * arm-dis.c (arm_opcodes): Add support for pldw.
  61         (thumb32_opcodes): Likewise.
  62
  63 2010-09-22  Robin Getz  <robin.getz@analog.com>
  64
  65         * bfin-dis.c (fmtconst): Cast address to 32bits.
  66
  67 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  68
  69         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
  70
  71 2010-09-22  Robin Getz  <robin.getz@analog.com>
  72
  73         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
  74         Reject P6/P7 to TESTSET.
  75         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
  76         SP onto the stack.
  77         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
  78         P/D fields match all the time.
  79         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
  80         are 0 for accumulator compares.
  81         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
  82         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
  83         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
  84         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
  85         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
  86         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
  87         insns.
  88         (decode_dagMODim_0): Verify br field for IREG ops.
  89         (decode_LDST_0): Reject preg load into same preg.
  90         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
  91         (print_insn_bfin): Likewise.
  92
  93 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  94
  95         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
  96
  97 2010-09-22  Robin Getz  <robin.getz@analog.com>
  98
  99         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
 100
 101 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 102
 103         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
 104
 105 2010-09-22  Robin Getz  <robin.getz@analog.com>
 106
 107         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
 108         register values greater than 8.
 109         (IS_RESERVEDREG, allreg, mostreg): New helpers.
 110         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
 111         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
 112         (decode_CC2dreg_0): Check valid CC register number.
 113
 114 2010-09-22  Robin Getz  <robin.getz@analog.com>
 115
 116         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
 117
 118 2010-09-22  Robin Getz  <robin.getz@analog.com>
 119
 120         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
 121         (reg_names): Likewise.
 122         (decode_statbits): Likewise; while reformatting to make manageable.
 123
 124 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 125
 126         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
 127         (decode_pseudoOChar_0): New function.
 128         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
 129
 130 2010-09-22  Robin Getz  <robin.getz@analog.com>
 131
 132         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
 133         LSHIFT instead of SHIFT.
 134
 135 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 136
 137         * bfin-dis.c (constant_formats): Constify the whole structure.
 138         (fmtconst): Add const to return value.
 139         (reg_names): Mark const.
 140         (decode_multfunc): Mark s0/s1 as const.
 141         (decode_macfunc): Mark a/sop as const.
 142
 143 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 144
 145         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 146
 147 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 148
 149         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 150         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 151
 152 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 153
 154         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 155         dlx_insn_type array.
 156
 157 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 158
 159         PR binutils/11960
 160         * i386-dis.c (sIv): New.
 161         (dis386): Replace Iq with sIv on "pushT".
 162         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 163         (x86_64_table): Replace {T|}/{P|} with P.
 164         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 165         (OP_sI): Update v_mode.  Remove w_mode.
 166
 167 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 168
 169         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 170         on E500 and E500MC.
 171
 172 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 173
 174         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 175         prefetchw.
 176
 177 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 178
 179         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 180         to processor flags for PENTIUMPRO processors and later.
 181         * i386-opc.h (enum): Add CpuNop.
 182         (i386_cpu_flags): Add cpunop bit.
 183         * i386-opc.tbl: Change nop cpu_flags.
 184         * i386-init.h: Regenerated.
 185         * i386-tbl.h: Likewise.
 186
 187 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 188
 189         * i386-opc.h (enum): Fix typos in comments.
 190
 191 2010-08-06  Alan Modra  <amodra@gmail.com>
 192
 193         * disassemble.c: Formatting.
 194         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 195
 196 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 197
 198         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 199         * i386-tbl.h: Regenerated.
 200
 201 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 202
 203         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 204
 205         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 206         * i386-tbl.h: Regenerated.
 207
 208 2010-07-29  DJ Delorie  <dj@redhat.com>
 209
 210         * rx-decode.opc (SRR): New.
 211         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 212         r0,r0) and NOP3 (max r0,r0) special cases.
 213         * rx-decode.c: Regenerate.
 214
 215 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 216
 217         * i386-dis.c: Add 0F to VEX opcode enums.
 218
 219 2010-07-27  DJ Delorie  <dj@redhat.com>
 220
 221         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 222         (rx_decode_opcode): Likewise.
 223         * rx-decode.c: Regenerate.
 224
 225 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 226             Ina Pandit  <ina.pandit@kpitcummins.com>
 227
 228         * v850-dis.c (v850_sreg_names): Updated structure for system
 229         registers.
 230         (float_cc_names): new structure for condition codes.
 231         (print_value): Update the function that prints value.
 232         (get_operand_value): New function to get the operand value.
 233         (disassemble): Updated to handle the disassembly of instructions.
 234         (print_insn_v850): Updated function to print instruction for different
 235         families.
 236         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 237         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 238         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 239         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 240         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 241         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 242         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 243         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 244         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 245         (v850_operands): Update with the relocation name. Also update
 246         the instructions with specific set of processors.
 247
 248 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 249
 250         * arm-dis.c (print_insn_arm): Add cases for printing more
 251         symbolic operands.
 252         (print_insn_thumb32): Likewise.
 253
 254 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 255
 256         * mips-dis.c (print_insn_mips): Correct branch instruction type
 257         determination.
 258
 259 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 260
 261         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 262         type and delay slot determination.
 263         (print_insn_mips16): Extend branch instruction type and delay
 264         slot determination to cover all instructions.
 265         * mips16-opc.c (BR): Remove macro.
 266         (UBR, CBR): New macros.
 267         (mips16_opcodes): Update branch annotation for "b", "beqz",
 268         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 269         and "jrc".
 270
 271 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 272
 273         AVX Programming Reference (June, 2010)
 274         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 275         * i386-opc.tbl: Likewise.
 276         * i386-tbl.h: Regenerated.
 277
 278 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 279
 280         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 281
 282 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 283
 284         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 285         ppc_cpu_t before inverting.
 286         (ppc_parse_cpu): Likewise.
 287         (print_insn_powerpc): Likewise.
 288
 289 2010-07-03  Alan Modra  <amodra@gmail.com>
 290
 291         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 292         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 293         (PPC64, MFDEC2): Update.
 294         (NON32, NO371): Define.
 295         (powerpc_opcode): Update to not use old opcode flags, and avoid
 296         -m601 duplicates.
 297
 298 2010-07-03  DJ Delorie  <dj@delorie.com>
 299
 300         * m32c-ibld.c: Regenerate.
 301
 302 2010-07-03  Alan Modra  <amodra@gmail.com>
 303
 304         * ppc-opc.c (PWR2COM): Define.
 305         (PPCPWR2): Add PPC_OPCODE_COMMON.
 306         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 307         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 308         "rac" from -mcom.
 309
 310 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 311
 312         AVX Programming Reference (June, 2010)
 313         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 314         (PREFIX_0FAE_REG_1): Likewise.
 315         (PREFIX_0FAE_REG_2): Likewise.
 316         (PREFIX_0FAE_REG_3): Likewise.
 317         (PREFIX_VEX_3813): Likewise.
 318         (PREFIX_VEX_3A1D): Likewise.
 319         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 320         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 321         PREFIX_VEX_3A1D.
 322         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 323         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 324         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 325
 326         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 327         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 328         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 329
 330         * i386-opc.h (CpuXsaveopt): New.
 331         (CpuFSGSBase): Likewise.
 332         (CpuRdRnd): Likewise.
 333         (CpuF16C): Likewise.
 334         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 335         cpuf16c.
 336
 337         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 338         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 339         * i386-init.h: Regenerated.
 340         * i386-tbl.h: Likewise.
 341
 342 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 343
 344         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 345         and mtocrf on EFS.
 346
 347 2010-06-29  Alan Modra  <amodra@gmail.com>
 348
 349         * maxq-dis.c: Delete file.
 350         * Makefile.am: Remove references to maxq.
 351         * configure.in: Likewise.
 352         * disassemble.c: Likewise.
 353         * Makefile.in: Regenerate.
 354         * configure: Regenerate.
 355         * po/POTFILES.in: Regenerate.
 356
 357 2010-06-29  Alan Modra  <amodra@gmail.com>
 358
 359         * mep-dis.c: Regenerate.
 360
 361 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 362
 363         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 364
 365 2010-06-27  Alan Modra  <amodra@gmail.com>
 366
 367         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 368         (decodeInstr): Likewise.
 369         * dlx-dis.c (print_insn_dlx): Likewise.
 370         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 371         * maxq-dis.c (check_move, print_insn): Likewise.
 372         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 373         * msp430-dis.c (msp430_branchinstr): Likewise.
 374         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 375         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 376         * sparc-dis.c (print_insn_sparc): Likewise.
 377         * fr30-asm.c: Regenerate.
 378         * frv-asm.c: Regenerate.
 379         * ip2k-asm.c: Regenerate.
 380         * iq2000-asm.c: Regenerate.
 381         * lm32-asm.c: Regenerate.
 382         * m32c-asm.c: Regenerate.
 383         * m32r-asm.c: Regenerate.
 384         * mep-asm.c: Regenerate.
 385         * mt-asm.c: Regenerate.
 386         * openrisc-asm.c: Regenerate.
 387         * xc16x-asm.c: Regenerate.
 388         * xstormy16-asm.c: Regenerate.
 389
 390 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 391
 392         PR gas/11673
 393         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 394
 395 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 396
 397         PR binutils/11676
 398         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 399
 400 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 401
 402         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 403         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 404         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 405         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 406         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 407         Treat lwsync as msync on e500.
 408
 409 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 410
 411         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 412
 413 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 414
 415         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 416         constants is the same on 32-bit and 64-bit hosts.
 417
 418 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 419
 420         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 421         .short directives so that they can be reassembled.
 422
 423 2010-05-26  Catherine Moore <clm@codesourcery.com>
 424             David Ung  <davidu@mips.com>
 425
 426         * mips-opc.c: Change membership to I1 for instructions ssnop and
 427         ehb.
 428
 429 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 430
 431         * i386-dis.c (sib): New.
 432         (get_sib): Likewise.
 433         (print_insn): Call get_sib.
 434         OP_E_memory): Use sib.
 435
 436 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 437
 438         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 439         * mips-opc.c (I16): Remove.
 440         (mips_builtin_op): Reclassify jalx.
 441
 442 2010-05-19  Alan Modra  <amodra@gmail.com>
 443
 444         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 445         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 446
 447 2010-05-13  Alan Modra  <amodra@gmail.com>
 448
 449         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 450
 451 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 452
 453         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 454         format.
 455         (print_insn_thumb16): Add support for new %W format.
 456
 457 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 458
 459         * Makefile.in: Regenerate with automake 1.11.1.
 460         * aclocal.m4: Ditto.
 461
 462 2010-05-05  Nick Clifton  <nickc@redhat.com>
 463
 464         * po/es.po: Updated Spanish translation.
 465
 466 2010-04-22  Nick Clifton  <nickc@redhat.com>
 467
 468         * po/opcodes.pot: Updated by the Translation project.
 469         * po/vi.po: Updated Vietnamese translation.
 470
 471 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 472
 473         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 474         bits in opcode.
 475
 476 2010-04-09  Nick Clifton  <nickc@redhat.com>
 477
 478         * i386-dis.c (print_insn): Remove unused variable op.
 479         (OP_sI): Remove unused variable mask.
 480
 481 2010-04-07  Alan Modra  <amodra@gmail.com>
 482
 483         * configure: Regenerate.
 484
 485 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 486
 487         * ppc-opc.c (RBOPT): New define.
 488         ("dccci"): Enable for PPCA2.  Make operands optional.
 489         ("iccci"): Likewise.  Do not deprecate for PPC476.
 490
 491 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 492
 493         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 494
 495 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 496
 497         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 498         * Makefile.in: Regenerate.
 499         * configure.in (bfd_tic6x_arch): New.
 500         * configure: Regenerate.
 501         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 502         (disassembler): Handle TI C6X.
 503         * tic6x-dis.c: New.
 504
 505 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 506
 507         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 508
 509 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 510
 511         * dis-buf.c (buffer_read_memory): Give error for reading just
 512         before the start of memory.
 513
 514 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 515             Quentin Neill <quentin.neill@amd.com>
 516
 517         * i386-dis.c (OP_LWP_I): Removed.
 518         (reg_table): Do not use OP_LWP_I, use Iq.
 519         (OP_LWPCB_E): Remove use of names16.
 520         (OP_LWP_E): Same.
 521         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 522         should not set the Vex.length bit.
 523         * i386-tbl.h: Regenerated.
 524
 525 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 526
 527         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 528
 529 2010-02-24  Nick Clifton  <nickc@redhat.com>
 530
 531         PR binutils/6773
 532         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 533         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 534         (thumb32_opcodes): Likewise.
 535
 536 2010-02-15  Nick Clifton  <nickc@redhat.com>
 537
 538         * po/vi.po: Updated Vietnamese translation.
 539
 540 2010-02-12  Doug Evans  <dje@sebabeach.org>
 541
 542         * lm32-opinst.c: Regenerate.
 543
 544 2010-02-11  Doug Evans  <dje@sebabeach.org>
 545
 546         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 547         (print_address): Delete CGEN_PRINT_ADDRESS.
 548         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 549         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 550         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 551         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 552
 553         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 554         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 555         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 556         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 557         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 558         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 559         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 560         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 561         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 562         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 563         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 564         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 565
 566 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 567
 568         * i386-dis.c: Update copyright.
 569         * i386-gen.c: Likewise.
 570         * i386-opc.h: Likewise.
 571         * i386-opc.tbl: Likewise.
 572
 573 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 574             Sebastian Pop  <sebastian.pop@amd.com>
 575
 576         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 577         function to handle 5th imm8 operand.
 578         (PREFIX_VEX_3A48): Added.
 579         (PREFIX_VEX_3A49): Added.
 580         (VEX_W_3A48_P_2): Added.
 581         (VEX_W_3A49_P_2): Added.
 582         (prefix table): Added entries for PREFIX_VEX_3A48
 583         and PREFIX_VEX_3A49.
 584         (vex table): Added entries for VEX_W_3A48_P_2 and
 585         and VEX_W_3A49_P_2.
 586         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 587         for Vec_Imm4 operands.
 588         * i386-opc.h (enum): Added Vec_Imm4.
 589         (i386_operand_type): Added vec_imm4.
 590         * i386-opc.tbl: Add entries for vpermilp[ds].
 591         * i386-init.h: Regenerated.
 592         * i386-tbl.h: Regenerated.
 593
 594 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 595
 596         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 597         and "pwr7".  Move "a2" into alphabetical order.
 598
 599 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 600
 601         * ppc-dis.c (ppc_opts): Add titan entry.
 602         * ppc-opc.c (TITAN, MULHW): Define.
 603         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 604
 605 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 606
 607         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 608         to CPU_BDVER1_FLAGS
 609         * i386-init.h: Regenerated.
 610
 611 2010-02-03  Anthony Green  <green@moxielogic.com>
 612
 613         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 614         0x0f, and make 0x00 an illegal instruction.
 615
 616 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 617
 618         * opcodes/arm-dis.c (struct arm_private_data): New.
 619         (print_insn_coprocessor, print_insn_arm): Update to use struct
 620         arm_private_data.
 621         (is_mapping_symbol, get_map_sym_type): New functions.
 622         (get_sym_code_type): Check the symbol's section.  Do not check
 623         mapping symbols.
 624         (print_insn): Default to disassembling ARM mode code.  Check
 625         for mapping symbols separately from other symbols.  Use
 626         struct arm_private_data.
 627
 628 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 629
 630         * i386-dis.c (EXVexWdqScalar): New.
 631         (vex_scalar_w_dq_mode): Likewise.
 632         (prefix_table): Update entries for PREFIX_VEX_3899,
 633         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 634         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 635         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 636         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 637         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 638         (OP_EX): Likewise.
 639
 640 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 641
 642         * i386-dis.c (XMScalar): New.
 643         (EXdScalar): Likewise.
 644         (EXqScalar): Likewise.
 645         (EXqScalarS): Likewise.
 646         (VexScalar): Likewise.
 647         (EXdVexScalarS): Likewise.
 648         (EXqVexScalarS): Likewise.
 649         (XMVexScalar): Likewise.
 650         (scalar_mode): Likewise.
 651         (d_scalar_mode): Likewise.
 652         (d_scalar_swap_mode): Likewise.
 653         (q_scalar_mode): Likewise.
 654         (q_scalar_swap_mode): Likewise.
 655         (vex_scalar_mode): Likewise.
 656         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 657         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 658         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 659         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 660         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 661         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 662         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 663         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 664         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 665         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 666         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 667         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 668         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 669         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 670         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 671         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 672         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 673         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 674         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 675         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 676         q_scalar_mode, q_scalar_swap_mode.
 677         (OP_XMM): Handle scalar_mode.
 678         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 679         and q_scalar_swap_mode.
 680         (OP_VEX): Handle vex_scalar_mode.
 681
 682 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 683
 684         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 685
 686 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 687
 688         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 689
 690 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 691
 692         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 693
 694 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 695
 696         * i386-dis.c (Bad_Opcode): New.
 697         (bad_opcode): Likewise.
 698         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 699         (dis386_twobyte): Likewise.
 700         (reg_table): Likewise.
 701         (prefix_table): Likewise.
 702         (x86_64_table): Likewise.
 703         (vex_len_table): Likewise.
 704         (vex_w_table): Likewise.
 705         (mod_table): Likewise.
 706         (rm_table): Likewise.
 707         (float_reg): Likewise.
 708         (reg_table): Remove trailing "(bad)" entries.
 709         (prefix_table): Likewise.
 710         (x86_64_table): Likewise.
 711         (vex_len_table): Likewise.
 712         (vex_w_table): Likewise.
 713         (mod_table): Likewise.
 714         (rm_table): Likewise.
 715         (get_valid_dis386): Handle bytemode 0.
 716
 717 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 718
 719         * i386-opc.h (VEXScalar): New.
 720
 721         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 722         instructions.
 723         * i386-tbl.h: Regenerated.
 724
 725 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 726
 727         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 728
 729         * i386-opc.tbl: Add xsave64 and xrstor64.
 730         * i386-tbl.h: Regenerated.
 731
 732 2010-01-20  Nick Clifton  <nickc@redhat.com>
 733
 734         PR 11170
 735         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 736         based post-indexed addressing.
 737
 738 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 739
 740         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 741         * i386-tbl.h: Regenerated.
 742
 743 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 744
 745         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 746         comments.
 747
 748 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 749
 750         * i386-dis.c (names_mm): New.
 751         (intel_names_mm): Likewise.
 752         (att_names_mm): Likewise.
 753         (names_xmm): Likewise.
 754         (intel_names_xmm): Likewise.
 755         (att_names_xmm): Likewise.
 756         (names_ymm): Likewise.
 757         (intel_names_ymm): Likewise.
 758         (att_names_ymm): Likewise.
 759         (print_insn): Set names_mm, names_xmm and names_ymm.
 760         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 761         (OP_XMM): Likewise.
 762         (OP_EM): Likewise.
 763         (OP_EMC): Likewise.
 764         (OP_MXC): Likewise.
 765         (OP_EX): Likewise.
 766         (XMM_Fixup): Likewise.
 767         (OP_VEX): Likewise.
 768         (OP_EX_VexReg): Likewise.
 769         (OP_Vex_2src): Likewise.
 770         (OP_Vex_2src_1): Likewise.
 771         (OP_Vex_2src_2): Likewise.
 772         (OP_REG_VexI4): Likewise.
 773
 774 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 775
 776         * i386-dis.c (print_insn): Update comments.
 777
 778 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 779
 780         * i386-dis.c (rex_original): Removed.
 781         (ckprefix): Remove rex_original.
 782         (print_insn): Update comments.
 783
 784 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 785
 786         * Makefile.in: Regenerate.
 787         * configure: Regenerate.
 788
 789 2010-01-07  Doug Evans  <dje@sebabeach.org>
 790
 791         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 792         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 793         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 794         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 795         * xstormy16-ibld.c: Regenerate.
 796
 797 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 798
 799         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 800         * i386-init.h: Regenerated.
 801
 802 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 803
 804         * arm-dis.c (print_insn): Fixed search for next symbol and data
 805         dumping condition, and the initial mapping symbol state.
 806
 807 2010-01-05  Doug Evans  <dje@sebabeach.org>
 808
 809         * cgen-ibld.in: #include "cgen/basic-modes.h".
 810         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 811         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 812         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 813         * xstormy16-ibld.c: Regenerate.
 814
 815 2010-01-04  Nick Clifton  <nickc@redhat.com>
 816
 817         PR 11123
 818         * arm-dis.c (print_insn_coprocessor): Initialise value.
 819
 820 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 821
 822         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 823
 824 2010-01-02  Doug Evans  <dje@sebabeach.org>
 825
 826         * cgen-asm.in: Update copyright year.
 827         * cgen-dis.in: Update copyright year.
 828         * cgen-ibld.in: Update copyright year.
 829         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 830         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 831         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 832         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 833         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 834         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 835         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 836         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 837         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 838         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 839         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 840         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 841         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 842         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 843         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 844         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 845         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 846         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 847         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 848         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 849         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 850
 851 For older changes see ChangeLog-2009
 852 \f
 853 Local Variables:
 854 mode: change-log
 855 left-margin: 8
 856 fill-column: 74
 857 version-control: never
 858 End: