1 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
3 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
5 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
8 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
9 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
10 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
11 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
12 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
13 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
14 EVEX_LEN_0F3A1B_P_2_W_1.
15 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
16 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
17 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
18 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
19 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
20 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
21 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
22 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
24 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
27 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
28 EVEX.vvvv when disassembling VEX and EVEX instructions.
29 (OP_VEX): Set vex.register_specifier to 0 after readding
30 vex.register_specifier.
31 (OP_Vex_2src_1): Likewise.
32 (OP_Vex_2src_2): Likewise.
34 (OP_EX_Vex): Don't check vex.register_specifier.
35 (OP_XMM_Vex): Likewise.
37 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
38 Lili Cui <lili.cui@intel.com>
40 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
41 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
43 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
44 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
45 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
46 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
47 (i386_cpu_flags): Add cpuavx512_vp2intersect.
48 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
49 * i386-init.h: Regenerated.
50 * i386-tbl.h: Likewise.
52 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
53 Lili Cui <lili.cui@intel.com>
55 * doc/c-i386.texi: Document enqcmd.
56 * testsuite/gas/i386/enqcmd-intel.d: New file.
57 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
58 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
59 * testsuite/gas/i386/enqcmd.d: Likewise.
60 * testsuite/gas/i386/enqcmd.s: Likewise.
61 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
62 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
63 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
64 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
65 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
66 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
67 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
70 2019-06-04 Alan Hayward <alan.hayward@arm.com>
72 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
74 2019-06-03 Alan Modra <amodra@gmail.com>
76 * ppc-dis.c (prefix_opcd_indices): Correct size.
78 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
81 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
83 * i386-tbl.h: Regenerated.
85 2019-05-24 Alan Modra <amodra@gmail.com>
87 * po/POTFILES.in: Regenerate.
89 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
90 Alan Modra <amodra@gmail.com>
92 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
93 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
94 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
95 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
96 XTOP>): Define and add entries.
97 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
98 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
99 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
100 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
102 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
103 Alan Modra <amodra@gmail.com>
105 * ppc-dis.c (ppc_opts): Add "future" entry.
106 (PREFIX_OPCD_SEGS): Define.
107 (prefix_opcd_indices): New array.
108 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
109 (lookup_prefix): New function.
110 (print_insn_powerpc): Handle 64-bit prefix instructions.
111 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
112 (PMRR, POWERXX): Define.
113 (prefix_opcodes): New instruction table.
114 (prefix_num_opcodes): New constant.
116 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
118 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
119 * configure: Regenerated.
120 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
122 (HFILES): Add bpf-desc.h and bpf-opc.h.
123 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
124 bpf-ibld.c and bpf-opc.c.
126 * Makefile.in: Regenerated.
127 * disassemble.c (ARCH_bpf): Define.
128 (disassembler): Add case for bfd_arch_bpf.
129 (disassemble_init_for_target): Likewise.
130 (enum epbf_isa_attr): Define.
131 * disassemble.h: extern print_insn_bpf.
132 * bpf-asm.c: Generated.
133 * bpf-opc.h: Likewise.
134 * bpf-opc.c: Likewise.
135 * bpf-ibld.c: Likewise.
136 * bpf-dis.c: Likewise.
137 * bpf-desc.h: Likewise.
138 * bpf-desc.c: Likewise.
140 2019-05-21 Sudakshina Das <sudi.das@arm.com>
142 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
143 and VMSR with the new operands.
145 2019-05-21 Sudakshina Das <sudi.das@arm.com>
147 * arm-dis.c (enum mve_instructions): New enum
148 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
150 (mve_opcodes): New instructions as above.
151 (is_mve_encoding_conflict): Add cases for csinc, csinv,
153 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
155 2019-05-21 Sudakshina Das <sudi.das@arm.com>
157 * arm-dis.c (emun mve_instructions): Updated for new instructions.
158 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
159 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
160 uqshl, urshrl and urshr.
161 (is_mve_okay_in_it): Add new instructions to TRUE list.
162 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
163 (print_insn_mve): Updated to accept new %j,
164 %<bitfield>m and %<bitfield>n patterns.
166 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
168 * mips-opc.c (mips_builtin_opcodes): Change source register
171 2019-05-20 Nick Clifton <nickc@redhat.com>
173 * po/fr.po: Updated French translation.
175 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
176 Michael Collison <michael.collison@arm.com>
178 * arm-dis.c (thumb32_opcodes): Add new instructions.
179 (enum mve_instructions): Likewise.
180 (enum mve_undefined): Add new reasons.
181 (is_mve_encoding_conflict): Handle new instructions.
182 (is_mve_undefined): Likewise.
183 (is_mve_unpredictable): Likewise.
184 (print_mve_undefined): Likewise.
185 (print_mve_size): Likewise.
187 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
188 Michael Collison <michael.collison@arm.com>
190 * arm-dis.c (thumb32_opcodes): Add new instructions.
191 (enum mve_instructions): Likewise.
192 (is_mve_encoding_conflict): Handle new instructions.
193 (is_mve_undefined): Likewise.
194 (is_mve_unpredictable): Likewise.
195 (print_mve_size): Likewise.
197 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
198 Michael Collison <michael.collison@arm.com>
200 * arm-dis.c (thumb32_opcodes): Add new instructions.
201 (enum mve_instructions): Likewise.
202 (is_mve_encoding_conflict): Likewise.
203 (is_mve_unpredictable): Likewise.
204 (print_mve_size): Likewise.
206 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
207 Michael Collison <michael.collison@arm.com>
209 * arm-dis.c (thumb32_opcodes): Add new instructions.
210 (enum mve_instructions): Likewise.
211 (is_mve_encoding_conflict): Handle new instructions.
212 (is_mve_undefined): Likewise.
213 (is_mve_unpredictable): Likewise.
214 (print_mve_size): Likewise.
216 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
217 Michael Collison <michael.collison@arm.com>
219 * arm-dis.c (thumb32_opcodes): Add new instructions.
220 (enum mve_instructions): Likewise.
221 (is_mve_encoding_conflict): Handle new instructions.
222 (is_mve_undefined): Likewise.
223 (is_mve_unpredictable): Likewise.
224 (print_mve_size): Likewise.
225 (print_insn_mve): Likewise.
227 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
228 Michael Collison <michael.collison@arm.com>
230 * arm-dis.c (thumb32_opcodes): Add new instructions.
231 (print_insn_thumb32): Handle new instructions.
233 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
234 Michael Collison <michael.collison@arm.com>
236 * arm-dis.c (enum mve_instructions): Add new instructions.
237 (enum mve_undefined): Add new reasons.
238 (is_mve_encoding_conflict): Handle new instructions.
239 (is_mve_undefined): Likewise.
240 (is_mve_unpredictable): Likewise.
241 (print_mve_undefined): Likewise.
242 (print_mve_size): Likewise.
243 (print_mve_shift_n): Likewise.
244 (print_insn_mve): Likewise.
246 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
247 Michael Collison <michael.collison@arm.com>
249 * arm-dis.c (enum mve_instructions): Add new instructions.
250 (is_mve_encoding_conflict): Handle new instructions.
251 (is_mve_unpredictable): Likewise.
252 (print_mve_rotate): Likewise.
253 (print_mve_size): Likewise.
254 (print_insn_mve): Likewise.
256 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
257 Michael Collison <michael.collison@arm.com>
259 * arm-dis.c (enum mve_instructions): Add new instructions.
260 (is_mve_encoding_conflict): Handle new instructions.
261 (is_mve_unpredictable): Likewise.
262 (print_mve_size): Likewise.
263 (print_insn_mve): Likewise.
265 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
266 Michael Collison <michael.collison@arm.com>
268 * arm-dis.c (enum mve_instructions): Add new instructions.
269 (enum mve_undefined): Add new reasons.
270 (is_mve_encoding_conflict): Handle new instructions.
271 (is_mve_undefined): Likewise.
272 (is_mve_unpredictable): Likewise.
273 (print_mve_undefined): Likewise.
274 (print_mve_size): Likewise.
275 (print_insn_mve): Likewise.
277 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
278 Michael Collison <michael.collison@arm.com>
280 * arm-dis.c (enum mve_instructions): Add new instructions.
281 (is_mve_encoding_conflict): Handle new instructions.
282 (is_mve_undefined): Likewise.
283 (is_mve_unpredictable): Likewise.
284 (print_mve_size): Likewise.
285 (print_insn_mve): Likewise.
287 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
288 Michael Collison <michael.collison@arm.com>
290 * arm-dis.c (enum mve_instructions): Add new instructions.
291 (enum mve_unpredictable): Add new reasons.
292 (enum mve_undefined): Likewise.
293 (is_mve_okay_in_it): Handle new isntructions.
294 (is_mve_encoding_conflict): Likewise.
295 (is_mve_undefined): Likewise.
296 (is_mve_unpredictable): Likewise.
297 (print_mve_vmov_index): Likewise.
298 (print_simd_imm8): Likewise.
299 (print_mve_undefined): Likewise.
300 (print_mve_unpredictable): Likewise.
301 (print_mve_size): Likewise.
302 (print_insn_mve): Likewise.
304 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
305 Michael Collison <michael.collison@arm.com>
307 * arm-dis.c (enum mve_instructions): Add new instructions.
308 (enum mve_unpredictable): Add new reasons.
309 (enum mve_undefined): Likewise.
310 (is_mve_encoding_conflict): Handle new instructions.
311 (is_mve_undefined): Likewise.
312 (is_mve_unpredictable): Likewise.
313 (print_mve_undefined): Likewise.
314 (print_mve_unpredictable): Likewise.
315 (print_mve_rounding_mode): Likewise.
316 (print_mve_vcvt_size): Likewise.
317 (print_mve_size): Likewise.
318 (print_insn_mve): Likewise.
320 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
321 Michael Collison <michael.collison@arm.com>
323 * arm-dis.c (enum mve_instructions): Add new instructions.
324 (enum mve_unpredictable): Add new reasons.
325 (enum mve_undefined): Likewise.
326 (is_mve_undefined): Handle new instructions.
327 (is_mve_unpredictable): Likewise.
328 (print_mve_undefined): Likewise.
329 (print_mve_unpredictable): Likewise.
330 (print_mve_size): Likewise.
331 (print_insn_mve): Likewise.
333 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
334 Michael Collison <michael.collison@arm.com>
336 * arm-dis.c (enum mve_instructions): Add new instructions.
337 (enum mve_undefined): Add new reasons.
338 (insns): Add new instructions.
339 (is_mve_encoding_conflict):
340 (print_mve_vld_str_addr): New print function.
341 (is_mve_undefined): Handle new instructions.
342 (is_mve_unpredictable): Likewise.
343 (print_mve_undefined): Likewise.
344 (print_mve_size): Likewise.
345 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
346 (print_insn_mve): Handle new operands.
348 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
349 Michael Collison <michael.collison@arm.com>
351 * arm-dis.c (enum mve_instructions): Add new instructions.
352 (enum mve_unpredictable): Add new reasons.
353 (is_mve_encoding_conflict): Handle new instructions.
354 (is_mve_unpredictable): Likewise.
355 (mve_opcodes): Add new instructions.
356 (print_mve_unpredictable): Handle new reasons.
357 (print_mve_register_blocks): New print function.
358 (print_mve_size): Handle new instructions.
359 (print_insn_mve): Likewise.
361 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
362 Michael Collison <michael.collison@arm.com>
364 * arm-dis.c (enum mve_instructions): Add new instructions.
365 (enum mve_unpredictable): Add new reasons.
366 (enum mve_undefined): Likewise.
367 (is_mve_encoding_conflict): Handle new instructions.
368 (is_mve_undefined): Likewise.
369 (is_mve_unpredictable): Likewise.
370 (coprocessor_opcodes): Move NEON VDUP from here...
371 (neon_opcodes): ... to here.
372 (mve_opcodes): Add new instructions.
373 (print_mve_undefined): Handle new reasons.
374 (print_mve_unpredictable): Likewise.
375 (print_mve_size): Handle new instructions.
376 (print_insn_neon): Handle vdup.
377 (print_insn_mve): Handle new operands.
379 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
380 Michael Collison <michael.collison@arm.com>
382 * arm-dis.c (enum mve_instructions): Add new instructions.
383 (enum mve_unpredictable): Add new values.
384 (mve_opcodes): Add new instructions.
385 (vec_condnames): New array with vector conditions.
386 (mve_predicatenames): New array with predicate suffixes.
387 (mve_vec_sizename): New array with vector sizes.
388 (enum vpt_pred_state): New enum with vector predication states.
389 (struct vpt_block): New struct type for vpt blocks.
390 (vpt_block_state): Global struct to keep track of state.
391 (mve_extract_pred_mask): New helper function.
392 (num_instructions_vpt_block): Likewise.
393 (mark_outside_vpt_block): Likewise.
394 (mark_inside_vpt_block): Likewise.
395 (invert_next_predicate_state): Likewise.
396 (update_next_predicate_state): Likewise.
397 (update_vpt_block_state): Likewise.
398 (is_vpt_instruction): Likewise.
399 (is_mve_encoding_conflict): Add entries for new instructions.
400 (is_mve_unpredictable): Likewise.
401 (print_mve_unpredictable): Handle new cases.
402 (print_instruction_predicate): Likewise.
403 (print_mve_size): New function.
404 (print_vec_condition): New function.
405 (print_insn_mve): Handle vpt blocks and new print operands.
407 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
409 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
410 8, 14 and 15 for Armv8.1-M Mainline.
412 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
413 Michael Collison <michael.collison@arm.com>
415 * arm-dis.c (enum mve_instructions): New enum.
416 (enum mve_unpredictable): Likewise.
417 (enum mve_undefined): Likewise.
418 (struct mopcode32): New struct.
419 (is_mve_okay_in_it): New function.
420 (is_mve_architecture): Likewise.
421 (arm_decode_field): Likewise.
422 (arm_decode_field_multiple): Likewise.
423 (is_mve_encoding_conflict): Likewise.
424 (is_mve_undefined): Likewise.
425 (is_mve_unpredictable): Likewise.
426 (print_mve_undefined): Likewise.
427 (print_mve_unpredictable): Likewise.
428 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
429 (print_insn_mve): New function.
430 (print_insn_thumb32): Handle MVE architecture.
431 (select_arm_features): Force thumb for Armv8.1-m Mainline.
433 2019-05-10 Nick Clifton <nickc@redhat.com>
436 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
437 end of the table prematurely.
439 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
441 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
444 2019-05-11 Alan Modra <amodra@gmail.com>
446 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
447 when -Mraw is in effect.
449 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
451 * aarch64-dis-2.c: Regenerate.
452 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
453 (OP_SVE_BBB): New variant set.
454 (OP_SVE_DDDD): New variant set.
455 (OP_SVE_HHH): New variant set.
456 (OP_SVE_HHHU): New variant set.
457 (OP_SVE_SSS): New variant set.
458 (OP_SVE_SSSU): New variant set.
459 (OP_SVE_SHH): New variant set.
460 (OP_SVE_SBBU): New variant set.
461 (OP_SVE_DSS): New variant set.
462 (OP_SVE_DHHU): New variant set.
463 (OP_SVE_VMV_HSD_BHS): New variant set.
464 (OP_SVE_VVU_HSD_BHS): New variant set.
465 (OP_SVE_VVVU_SD_BH): New variant set.
466 (OP_SVE_VVVU_BHSD): New variant set.
467 (OP_SVE_VVV_QHD_DBS): New variant set.
468 (OP_SVE_VVV_HSD_BHS): New variant set.
469 (OP_SVE_VVV_HSD_BHS2): New variant set.
470 (OP_SVE_VVV_BHS_HSD): New variant set.
471 (OP_SVE_VV_BHS_HSD): New variant set.
472 (OP_SVE_VVV_SD): New variant set.
473 (OP_SVE_VVU_BHS_HSD): New variant set.
474 (OP_SVE_VZVV_SD): New variant set.
475 (OP_SVE_VZVV_BH): New variant set.
476 (OP_SVE_VZV_SD): New variant set.
477 (aarch64_opcode_table): Add sve2 instructions.
479 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
481 * aarch64-asm-2.c: Regenerated.
482 * aarch64-dis-2.c: Regenerated.
483 * aarch64-opc-2.c: Regenerated.
484 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
485 for SVE_SHLIMM_UNPRED_22.
486 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
487 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
490 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
492 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
493 sve_size_tsz_bhs iclass encode.
494 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
495 sve_size_tsz_bhs iclass decode.
497 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
499 * aarch64-asm-2.c: Regenerated.
500 * aarch64-dis-2.c: Regenerated.
501 * aarch64-opc-2.c: Regenerated.
502 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
503 for SVE_Zm4_11_INDEX.
504 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
505 (fields): Handle SVE_i2h field.
506 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
507 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
509 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
511 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
512 sve_shift_tsz_bhsd iclass encode.
513 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
514 sve_shift_tsz_bhsd iclass decode.
516 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
518 * aarch64-asm-2.c: Regenerated.
519 * aarch64-dis-2.c: Regenerated.
520 * aarch64-opc-2.c: Regenerated.
521 * aarch64-asm.c (aarch64_ins_sve_shrimm):
522 (aarch64_encode_variant_using_iclass): Handle
523 sve_shift_tsz_hsd iclass encode.
524 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
525 sve_shift_tsz_hsd iclass decode.
526 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
527 for SVE_SHRIMM_UNPRED_22.
528 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
529 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
532 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
534 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
535 sve_size_013 iclass encode.
536 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
537 sve_size_013 iclass decode.
539 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
541 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
542 sve_size_bh iclass encode.
543 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
544 sve_size_bh iclass decode.
546 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
548 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
549 sve_size_sd2 iclass encode.
550 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
551 sve_size_sd2 iclass decode.
552 * aarch64-opc.c (fields): Handle SVE_sz2 field.
553 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
555 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
557 * aarch64-asm-2.c: Regenerated.
558 * aarch64-dis-2.c: Regenerated.
559 * aarch64-opc-2.c: Regenerated.
560 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
562 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
563 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
565 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
567 * aarch64-asm-2.c: Regenerated.
568 * aarch64-dis-2.c: Regenerated.
569 * aarch64-opc-2.c: Regenerated.
570 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
571 for SVE_Zm3_11_INDEX.
572 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
573 (fields): Handle SVE_i3l and SVE_i3h2 fields.
574 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
576 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
578 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
580 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
581 sve_size_hsd2 iclass encode.
582 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
583 sve_size_hsd2 iclass decode.
584 * aarch64-opc.c (fields): Handle SVE_size field.
585 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
587 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
589 * aarch64-asm-2.c: Regenerated.
590 * aarch64-dis-2.c: Regenerated.
591 * aarch64-opc-2.c: Regenerated.
592 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
594 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
595 (fields): Handle SVE_rot3 field.
596 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
597 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
599 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
601 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
604 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
607 (aarch64_feature_sve2, aarch64_feature_sve2aes,
608 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
609 aarch64_feature_sve2bitperm): New feature sets.
610 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
611 for feature set addresses.
612 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
613 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
615 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
616 Faraz Shahbazker <fshahbazker@wavecomp.com>
618 * mips-dis.c (mips_calculate_combination_ases): Add ISA
619 argument and set ASE_EVA_R6 appropriately.
620 (set_default_mips_dis_options): Pass ISA to above.
621 (parse_mips_dis_option): Likewise.
622 * mips-opc.c (EVAR6): New macro.
623 (mips_builtin_opcodes): Add llwpe, scwpe.
625 2019-05-01 Sudakshina Das <sudi.das@arm.com>
627 * aarch64-asm-2.c: Regenerated.
628 * aarch64-dis-2.c: Regenerated.
629 * aarch64-opc-2.c: Regenerated.
630 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
631 AARCH64_OPND_TME_UIMM16.
632 (aarch64_print_operand): Likewise.
633 * aarch64-tbl.h (QL_IMM_NIL): New.
636 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
638 2019-04-29 John Darrington <john@darrington.wattle.id.au>
640 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
642 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
643 Faraz Shahbazker <fshahbazker@wavecomp.com>
645 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
647 2019-04-24 John Darrington <john@darrington.wattle.id.au>
649 * s12z-opc.h: Add extern "C" bracketing to help
650 users who wish to use this interface in c++ code.
652 2019-04-24 John Darrington <john@darrington.wattle.id.au>
654 * s12z-opc.c (bm_decode): Handle bit map operations with the
657 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
659 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
660 specifier. Add entries for VLDR and VSTR of system registers.
661 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
662 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
663 of %J and %K format specifier.
665 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
667 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
668 Add new entries for VSCCLRM instruction.
669 (print_insn_coprocessor): Handle new %C format control code.
671 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
673 * arm-dis.c (enum isa): New enum.
674 (struct sopcode32): New structure.
675 (coprocessor_opcodes): change type of entries to struct sopcode32 and
676 set isa field of all current entries to ANY.
677 (print_insn_coprocessor): Change type of insn to struct sopcode32.
678 Only match an entry if its isa field allows the current mode.
680 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
682 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
684 (print_insn_thumb32): Add logic to print %n CLRM register list.
686 2019-04-15 Sudakshina Das <sudi.das@arm.com>
688 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
691 2019-04-15 Sudakshina Das <sudi.das@arm.com>
693 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
694 (print_insn_thumb32): Edit the switch case for %Z.
696 2019-04-15 Sudakshina Das <sudi.das@arm.com>
698 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
700 2019-04-15 Sudakshina Das <sudi.das@arm.com>
702 * arm-dis.c (thumb32_opcodes): New instruction bfl.
704 2019-04-15 Sudakshina Das <sudi.das@arm.com>
706 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
708 2019-04-15 Sudakshina Das <sudi.das@arm.com>
710 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
711 Arm register with r13 and r15 unpredictable.
712 (thumb32_opcodes): New instructions for bfx and bflx.
714 2019-04-15 Sudakshina Das <sudi.das@arm.com>
716 * arm-dis.c (thumb32_opcodes): New instructions for bf.
718 2019-04-15 Sudakshina Das <sudi.das@arm.com>
720 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
722 2019-04-15 Sudakshina Das <sudi.das@arm.com>
724 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
726 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
728 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
730 2019-04-12 John Darrington <john@darrington.wattle.id.au>
732 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
733 "optr". ("operator" is a reserved word in c++).
735 2019-04-11 Sudakshina Das <sudi.das@arm.com>
737 * aarch64-opc.c (aarch64_print_operand): Add case for
739 (verify_constraints): Likewise.
740 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
741 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
742 to accept Rt|SP as first operand.
743 (AARCH64_OPERANDS): Add new Rt_SP.
744 * aarch64-asm-2.c: Regenerated.
745 * aarch64-dis-2.c: Regenerated.
746 * aarch64-opc-2.c: Regenerated.
748 2019-04-11 Sudakshina Das <sudi.das@arm.com>
750 * aarch64-asm-2.c: Regenerated.
751 * aarch64-dis-2.c: Likewise.
752 * aarch64-opc-2.c: Likewise.
753 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
755 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
757 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
759 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
761 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
762 * i386-init.h: Regenerated.
764 2019-04-07 Alan Modra <amodra@gmail.com>
766 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
767 op_separator to control printing of spaces, comma and parens
768 rather than need_comma, need_paren and spaces vars.
770 2019-04-07 Alan Modra <amodra@gmail.com>
773 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
774 (print_insn_neon, print_insn_arm): Likewise.
776 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
778 * i386-dis-evex.h (evex_table): Updated to support BF16
780 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
781 and EVEX_W_0F3872_P_3.
782 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
783 (cpu_flags): Add bitfield for CpuAVX512_BF16.
784 * i386-opc.h (enum): Add CpuAVX512_BF16.
785 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
786 * i386-opc.tbl: Add AVX512 BF16 instructions.
787 * i386-init.h: Regenerated.
788 * i386-tbl.h: Likewise.
790 2019-04-05 Alan Modra <amodra@gmail.com>
792 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
793 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
794 to favour printing of "-" branch hint when using the "y" bit.
795 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
797 2019-04-05 Alan Modra <amodra@gmail.com>
799 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
800 opcode until first operand is output.
802 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
805 * ppc-opc.c (valid_bo_pre_v2): Add comments.
806 (valid_bo_post_v2): Add support for 'at' branch hints.
807 (insert_bo): Only error on branch on ctr.
808 (get_bo_hint_mask): New function.
809 (insert_boe): Add new 'branch_taken' formal argument. Add support
810 for inserting 'at' branch hints.
811 (extract_boe): Add new 'branch_taken' formal argument. Add support
812 for extracting 'at' branch hints.
813 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
814 (BOE): Delete operand.
815 (BOM, BOP): New operands.
817 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
818 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
819 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
820 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
821 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
822 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
823 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
824 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
825 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
826 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
827 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
828 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
829 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
830 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
831 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
832 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
833 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
834 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
835 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
836 bttarl+>: New extended mnemonics.
838 2019-03-28 Alan Modra <amodra@gmail.com>
841 * ppc-opc.c (BTF): Define.
842 (powerpc_opcodes): Use for mtfsb*.
843 * ppc-dis.c (print_insn_powerpc): Print fields with both
844 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
846 2019-03-25 Tamar Christina <tamar.christina@arm.com>
848 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
849 (mapping_symbol_for_insn): Implement new algorithm.
850 (print_insn): Remove duplicate code.
852 2019-03-25 Tamar Christina <tamar.christina@arm.com>
854 * aarch64-dis.c (print_insn_aarch64):
857 2019-03-25 Tamar Christina <tamar.christina@arm.com>
859 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
862 2019-03-25 Tamar Christina <tamar.christina@arm.com>
864 * aarch64-dis.c (last_stop_offset): New.
865 (print_insn_aarch64): Use stop_offset.
867 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
870 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
872 * i386-init.h: Regenerated.
874 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
877 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
878 vmovdqu16, vmovdqu32 and vmovdqu64.
879 * i386-tbl.h: Regenerated.
881 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
883 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
884 from vstrszb, vstrszh, and vstrszf.
886 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
888 * s390-opc.txt: Add instruction descriptions.
890 2019-02-08 Jim Wilson <jimw@sifive.com>
892 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
895 2019-02-07 Tamar Christina <tamar.christina@arm.com>
897 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
899 2019-02-07 Tamar Christina <tamar.christina@arm.com>
902 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
903 * aarch64-opc.c (verify_elem_sd): New.
904 (fields): Add FLD_sz entr.
905 * aarch64-tbl.h (_SIMD_INSN): New.
906 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
907 fmulx scalar and vector by element isns.
909 2019-02-07 Nick Clifton <nickc@redhat.com>
911 * po/sv.po: Updated Swedish translation.
913 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
915 * s390-mkopc.c (main): Accept arch13 as cpu string.
916 * s390-opc.c: Add new instruction formats and instruction opcode
918 * s390-opc.txt: Add new arch13 instructions.
920 2019-01-25 Sudakshina Das <sudi.das@arm.com>
922 * aarch64-tbl.h (QL_LDST_AT): Update macro.
923 (aarch64_opcode): Change encoding for stg, stzg
925 * aarch64-asm-2.c: Regenerated.
926 * aarch64-dis-2.c: Regenerated.
927 * aarch64-opc-2.c: Regenerated.
929 2019-01-25 Sudakshina Das <sudi.das@arm.com>
931 * aarch64-asm-2.c: Regenerated.
932 * aarch64-dis-2.c: Likewise.
933 * aarch64-opc-2.c: Likewise.
934 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
936 2019-01-25 Sudakshina Das <sudi.das@arm.com>
937 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
939 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
940 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
941 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
942 * aarch64-dis.h (ext_addr_simple_2): Likewise.
943 * aarch64-opc.c (operand_general_constraint_met_p): Remove
944 case for ldstgv_indexed.
945 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
946 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
947 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
948 * aarch64-asm-2.c: Regenerated.
949 * aarch64-dis-2.c: Regenerated.
950 * aarch64-opc-2.c: Regenerated.
952 2019-01-23 Nick Clifton <nickc@redhat.com>
954 * po/pt_BR.po: Updated Brazilian Portuguese translation.
956 2019-01-21 Nick Clifton <nickc@redhat.com>
958 * po/de.po: Updated German translation.
959 * po/uk.po: Updated Ukranian translation.
961 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
962 * mips-dis.c (mips_arch_choices): Fix typo in
963 gs464, gs464e and gs264e descriptors.
965 2019-01-19 Nick Clifton <nickc@redhat.com>
967 * configure: Regenerate.
968 * po/opcodes.pot: Regenerate.
970 2018-06-24 Nick Clifton <nickc@redhat.com>
974 2019-01-09 John Darrington <john@darrington.wattle.id.au>
976 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
978 -dis.c (opr_emit_disassembly): Do not omit an index if it is
981 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
983 * configure: Regenerate.
985 2019-01-07 Alan Modra <amodra@gmail.com>
987 * configure: Regenerate.
988 * po/POTFILES.in: Regenerate.
990 2019-01-03 John Darrington <john@darrington.wattle.id.au>
992 * s12z-opc.c: New file.
993 * s12z-opc.h: New file.
994 * s12z-dis.c: Removed all code not directly related to display
995 of instructions. Used the interface provided by the new files
997 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
998 * Makefile.in: Regenerate.
999 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1000 * configure: Regenerate.
1002 2019-01-01 Alan Modra <amodra@gmail.com>
1004 Update year range in copyright notice of all files.
1006 For older changes see ChangeLog-2018
1008 Copyright (C) 2019 Free Software Foundation, Inc.
1010 Copying and distribution of this file, with or without modification,
1011 are permitted in any medium without royalty provided the copyright
1012 notice and this notice are preserved.
1018 version-control: never