opcodes/ChangeLog

   1 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
   2
   3         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
   4         constant.
   5
   6 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         PR gas/20145
   9         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
  10         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
  11         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
  12         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
  13         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
  14         * i386-init.h: Regenerated.
  15
  16 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  17
  18         PR gas/20145
  19         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
  20         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
  21         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
  22         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
  23         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
  24         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
  25         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
  26         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
  27         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
  28         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
  29         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
  30         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
  31         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
  32         CpuRegMask for AVX512.
  33         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
  34         and CpuRegMask.
  35         (set_bitfield_from_cpu_flag_init): New function.
  36         (set_bitfield): Remove const on f.  Call
  37         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
  38         * i386-opc.h (CpuRegMMX): New.
  39         (CpuRegXMM): Likewise.
  40         (CpuRegYMM): Likewise.
  41         (CpuRegZMM): Likewise.
  42         (CpuRegMask): Likewise.
  43         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
  44         and cpuregmask.
  45         * i386-init.h: Regenerated.
  46         * i386-tbl.h: Likewise.
  47
  48 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  49
  50         PR gas/20154
  51         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
  52         (opcode_modifiers): Add AMD64 and Intel64.
  53         (main): Properly verify CpuMax.
  54         * i386-opc.h (CpuAMD64): Removed.
  55         (CpuIntel64): Likewise.
  56         (CpuMax): Set to CpuNo64.
  57         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
  58         (AMD64): New.
  59         (Intel64): Likewise.
  60         (i386_opcode_modifier): Add amd64 and intel64.
  61         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
  62         on call and jmp.
  63         * i386-init.h: Regenerated.
  64         * i386-tbl.h: Likewise.
  65
  66 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  67
  68         PR gas/20154
  69         * i386-gen.c (main): Fail if CpuMax is incorrect.
  70         * i386-opc.h (CpuMax): Set to CpuIntel64.
  71         * i386-tbl.h: Regenerated.
  72
  73 2016-05-27  Nick Clifton  <nickc@redhat.com>
  74
  75         PR target/20150
  76         * msp430-dis.c (msp430dis_read_two_bytes): New function.
  77         (msp430dis_opcode_unsigned): New function.
  78         (msp430dis_opcode_signed): New function.
  79         (msp430_singleoperand): Use the new opcode reading functions.
  80         Only disassenmble bytes if they were successfully read.
  81         (msp430_doubleoperand): Likewise.
  82         (msp430_branchinstr): Likewise.
  83         (msp430x_callx_instr): Likewise.
  84         (print_insn_msp430): Check that it is safe to read bytes before
  85         attempting disassembly.  Use the new opcode reading functions.
  86
  87 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
  88
  89         * ppc-opc.c (CY): New define.  Document it.
  90         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
  91
  92 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
  93
  94         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
  95         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
  96         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
  97         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
  98         CPU_ANY_AVX_FLAGS.
  99         * i386-init.h: Regenerated.
 100
 101 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 102
 103         PR gas/20141
 104         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 105         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 106         * i386-init.h: Regenerated.
 107
 108 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 109
 110         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 111         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 112         * i386-init.h: Regenerated.
 113
 114 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 115
 116         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 117         information.
 118         (print_insn_arc): Set insn_type information.
 119         * arc-opc.c (C_CC): Add F_CLASS_COND.
 120         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 121         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 122         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 123         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 124         (brne, brne_s, jeq_s, jne_s): Likewise.
 125
 126 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 127
 128         * arc-tbl.h (neg): New instruction variant.
 129
 130 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 131
 132         * arc-dis.c (find_format, find_format, get_auxreg)
 133         (print_insn_arc): Changed.
 134         * arc-ext.h (INSERT_XOP): Likewise.
 135
 136 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 137
 138         * tic54x-dis.c (sprint_mmr): Adjust.
 139         * tic54x-opc.c: Likewise.
 140
 141 2016-05-19  Alan Modra  <amodra@gmail.com>
 142
 143         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 144
 145 2016-05-19  Alan Modra  <amodra@gmail.com>
 146
 147         * ppc-opc.c: Formatting.
 148         (NSISIGNOPT): Define.
 149         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 150
 151 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 152
 153         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 154         replacing references to `micromips_ase' throughout.
 155         (_print_insn_mips): Don't use file-level microMIPS annotation to
 156         determine the disassembly mode with the symbol table.
 157
 158 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 159
 160         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 161
 162 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 163
 164         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 165         mips64r6.
 166         * mips-opc.c (D34): New macro.
 167         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 168
 169 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 170
 171         * i386-dis.c (prefix_table): Add RDPID instruction.
 172         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 173         (cpu_flags): Add RDPID bitfield.
 174         * i386-opc.h (enum): Add RDPID element.
 175         (i386_cpu_flags): Add RDPID field.
 176         * i386-opc.tbl: Add RDPID instruction.
 177         * i386-init.h: Regenerate.
 178         * i386-tbl.h: Regenerate.
 179
 180 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 181
 182         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 183         branch type of a symbol.
 184         (print_insn): Likewise.
 185
 186 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 187
 188         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 189         Mainline Security Extensions instructions.
 190         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 191         Extensions instructions.
 192         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 193         instructions.
 194         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 195         special registers.
 196
 197 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 198
 199         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 200
 201 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 202
 203         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 204         (arcExtMap_genOpcode): Likewise.
 205         * arc-opc.c (arg_32bit_rc): Define new variable.
 206         (arg_32bit_u6): Likewise.
 207         (arg_32bit_limm): Likewise.
 208
 209 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 210
 211         * aarch64-gen.c (VERIFIER): Define.
 212         * aarch64-opc.c (VERIFIER): Define.
 213         (verify_ldpsw): Use static linkage.
 214         * aarch64-opc.h (verify_ldpsw): Remove.
 215         * aarch64-tbl.h: Use VERIFIER for verifiers.
 216
 217 2016-04-28  Nick Clifton  <nickc@redhat.com>
 218
 219         PR target/19722
 220         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 221         * aarch64-opc.c (verify_ldpsw): New function.
 222         * aarch64-opc.h (verify_ldpsw): New prototype.
 223         * aarch64-tbl.h: Add initialiser for verifier field.
 224         (LDPSW): Set verifier to verify_ldpsw.
 225
 226 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 227
 228         PR binutils/19983
 229         PR binutils/19984
 230         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 231         smaller than address size.
 232
 233 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 234
 235         * alpha-dis.c: Regenerate.
 236         * crx-dis.c: Likewise.
 237         * disassemble.c: Likewise.
 238         * epiphany-opc.c: Likewise.
 239         * fr30-opc.c: Likewise.
 240         * frv-opc.c: Likewise.
 241         * ip2k-opc.c: Likewise.
 242         * iq2000-opc.c: Likewise.
 243         * lm32-opc.c: Likewise.
 244         * lm32-opinst.c: Likewise.
 245         * m32c-opc.c: Likewise.
 246         * m32r-opc.c: Likewise.
 247         * m32r-opinst.c: Likewise.
 248         * mep-opc.c: Likewise.
 249         * mt-opc.c: Likewise.
 250         * or1k-opc.c: Likewise.
 251         * or1k-opinst.c: Likewise.
 252         * tic80-opc.c: Likewise.
 253         * xc16x-opc.c: Likewise.
 254         * xstormy16-opc.c: Likewise.
 255
 256 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 257
 258         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 259         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 260         calcsd, and calcxd instructions.
 261         * arc-opc.c (insert_nps_bitop_size): Delete.
 262         (extract_nps_bitop_size): Delete.
 263         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 264         (extract_nps_qcmp_m3): Define.
 265         (extract_nps_qcmp_m2): Define.
 266         (extract_nps_qcmp_m1): Define.
 267         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 268         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 269         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 270         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 271         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 272         NPS_QCMP_M3.
 273
 274 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 275
 276         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 277
 278 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 279
 280         * Makefile.in: Regenerated with automake 1.11.6.
 281         * aclocal.m4: Likewise.
 282
 283 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 284
 285         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 286         instructions.
 287         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 288         (extract_nps_cmem_uimm16): New function.
 289         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 290
 291 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 292
 293         * arc-dis.c (arc_insn_length): New function.
 294         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 295         (find_format): Change insnLen parameter to unsigned.
 296
 297 2016-04-13  Nick Clifton  <nickc@redhat.com>
 298
 299         PR target/19937
 300         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 301         the LD.B and LD.BU instructions.
 302
 303 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 304
 305         * arc-dis.c (find_format): Check for extension flags.
 306         (print_flags): New function.
 307         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 308         .extAuxRegister.
 309         * arc-ext.c (arcExtMap_coreRegName): Use
 310         LAST_EXTENSION_CORE_REGISTER.
 311         (arcExtMap_coreReadWrite): Likewise.
 312         (dump_ARC_extmap): Update printing.
 313         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 314         (arc_aux_regs): Add cpu field.
 315         * arc-regs.h: Add cpu field, lower case name aux registers.
 316
 317 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 318
 319         * arc-tbl.h: Add rtsc, sleep with no arguments.
 320
 321 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 322
 323         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 324         Initialize.
 325         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 326         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 327         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 328         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 329         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 330         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 331         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 332         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 333         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 334         (arc_opcode arc_opcodes): Null terminate the array.
 335         (arc_num_opcodes): Remove.
 336         * arc-ext.h (INSERT_XOP): Define.
 337         (extInstruction_t): Likewise.
 338         (arcExtMap_instName): Delete.
 339         (arcExtMap_insn): New function.
 340         (arcExtMap_genOpcode): Likewise.
 341         * arc-ext.c (ExtInstruction): Remove.
 342         (create_map): Zero initialize instruction fields.
 343         (arcExtMap_instName): Remove.
 344         (arcExtMap_insn): New function.
 345         (dump_ARC_extmap): More info while debuging.
 346         (arcExtMap_genOpcode): New function.
 347         * arc-dis.c (find_format): New function.
 348         (print_insn_arc): Use find_format.
 349         (arc_get_disassembler): Enable dump_ARC_extmap only when
 350         debugging.
 351
 352 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 353
 354         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 355         instruction bits out.
 356
 357 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 358
 359         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 360         * arc-opc.c (arc_flag_operands): Add new flags.
 361         (arc_flag_classes): Add new classes.
 362
 363 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 364
 365         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 366
 367 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 368
 369         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 370         encode1, rflt, crc16, and crc32 instructions.
 371         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 372         (arc_flag_classes): Add C_NPS_R.
 373         (insert_nps_bitop_size_2b): New function.
 374         (extract_nps_bitop_size_2b): Likewise.
 375         (insert_nps_bitop_uimm8): Likewise.
 376         (extract_nps_bitop_uimm8): Likewise.
 377         (arc_operands): Add new operand entries.
 378
 379 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 380
 381         * arc-regs.h: Add a new subclass field.  Add double assist
 382         accumulator register values.
 383         * arc-tbl.h: Use DPA subclass to mark the double assist
 384         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 385         * arc-opc.c (RSP): Define instead of SP.
 386         (arc_aux_regs): Add the subclass field.
 387
 388 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 389
 390         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 391
 392 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 393
 394         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 395         NPS_R_SRC1.
 396
 397 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 398
 399         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 400         issues.  No functional changes.
 401
 402 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 403
 404         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 405         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 406         (RTT): Remove duplicate.
 407         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 408         (PCT_CONFIG*): Remove.
 409         (D1L, D1H, D2H, D2L): Define.
 410
 411 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 412
 413         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 414
 415 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 416
 417         * arc-tbl.h (invld07): Remove.
 418         * arc-ext-tbl.h: New file.
 419         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 420         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 421
 422 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 423
 424         Fix -Wstack-usage warnings.
 425         * aarch64-dis.c (print_operands): Substitute size.
 426         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 427
 428 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 429
 430         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 431         to get a proper diagnostic when an invalid ASR register is used.
 432
 433 2016-03-22  Nick Clifton  <nickc@redhat.com>
 434
 435         * configure: Regenerate.
 436
 437 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 438
 439         * arc-nps400-tbl.h: New file.
 440         * arc-opc.c: Add top level comment.
 441         (insert_nps_3bit_dst): New function.
 442         (extract_nps_3bit_dst): New function.
 443         (insert_nps_3bit_src2): New function.
 444         (extract_nps_3bit_src2): New function.
 445         (insert_nps_bitop_size): New function.
 446         (extract_nps_bitop_size): New function.
 447         (arc_flag_operands): Add nps400 entries.
 448         (arc_flag_classes): Add nps400 entries.
 449         (arc_operands): Add nps400 entries.
 450         (arc_opcodes): Add nps400 include.
 451
 452 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 453
 454         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 455         the new class enum values.
 456
 457 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 458
 459         * arc-dis.c (print_insn_arc): Handle nps400.
 460
 461 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 462
 463         * arc-opc.c (BASE): Delete.
 464
 465 2016-03-18  Nick Clifton  <nickc@redhat.com>
 466
 467         PR target/19721
 468         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 469         of MOV insn that aliases an ORR insn.
 470
 471 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 472
 473         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 474
 475 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 476
 477         * mcore-opc.h: Add const qualifiers.
 478         * microblaze-opc.h (struct op_code_struct): Likewise.
 479         * sh-opc.h: Likewise.
 480         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 481         (tic4x_print_op): Likewise.
 482
 483 2016-03-02  Alan Modra  <amodra@gmail.com>
 484
 485         * or1k-desc.h: Regenerate.
 486         * fr30-ibld.c: Regenerate.
 487         * rl78-decode.c: Regenerate.
 488
 489 2016-03-01  Nick Clifton  <nickc@redhat.com>
 490
 491         PR target/19747
 492         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 493
 494 2016-02-24  Renlin Li  <renlin.li@arm.com>
 495
 496         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 497         (print_insn_coprocessor): Support fp16 instructions.
 498
 499 2016-02-24  Renlin Li  <renlin.li@arm.com>
 500
 501         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 502         vminnm, vrint(mpna).
 503
 504 2016-02-24  Renlin Li  <renlin.li@arm.com>
 505
 506         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 507         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 508
 509 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 510
 511         * i386-dis.c (print_insn): Parenthesize expression to prevent
 512         truncated addresses.
 513         (OP_J): Likewise.
 514
 515 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 516             Janek van Oirschot  <jvanoirs@synopsys.com>
 517
 518         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 519         variable.
 520
 521 2016-02-04  Nick Clifton  <nickc@redhat.com>
 522
 523         PR target/19561
 524         * msp430-dis.c (print_insn_msp430): Add a special case for
 525         decoding an RRC instruction with the ZC bit set in the extension
 526         word.
 527
 528 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 529
 530         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 531         * epiphany-ibld.c: Regenerate.
 532         * fr30-ibld.c: Regenerate.
 533         * frv-ibld.c: Regenerate.
 534         * ip2k-ibld.c: Regenerate.
 535         * iq2000-ibld.c: Regenerate.
 536         * lm32-ibld.c: Regenerate.
 537         * m32c-ibld.c: Regenerate.
 538         * m32r-ibld.c: Regenerate.
 539         * mep-ibld.c: Regenerate.
 540         * mt-ibld.c: Regenerate.
 541         * or1k-ibld.c: Regenerate.
 542         * xc16x-ibld.c: Regenerate.
 543         * xstormy16-ibld.c: Regenerate.
 544
 545 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 546
 547         * epiphany-dis.c: Regenerated from latest cpu files.
 548
 549 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 550
 551         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 552         test bit.
 553
 554 2016-01-25  Renlin Li  <renlin.li@arm.com>
 555
 556         * arm-dis.c (mapping_symbol_for_insn): New function.
 557         (find_ifthen_state): Call mapping_symbol_for_insn().
 558
 559 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 560
 561         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 562         of MSR UAO immediate operand.
 563
 564 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 565
 566         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 567         instruction support.
 568
 569 2016-01-17  Alan Modra  <amodra@gmail.com>
 570
 571         * configure: Regenerate.
 572
 573 2016-01-14  Nick Clifton  <nickc@redhat.com>
 574
 575         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 576         instructions that can support stack pointer operations.
 577         * rl78-decode.c: Regenerate.
 578         * rl78-dis.c: Fix display of stack pointer in MOVW based
 579         instructions.
 580
 581 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 582
 583         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 584         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 585         erxtatus_el1 and erxaddr_el1.
 586
 587 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 588
 589         * arm-dis.c (arm_opcodes): Add "esb".
 590         (thumb_opcodes): Likewise.
 591
 592 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 593
 594         * ppc-opc.c <xscmpnedp>: Delete.
 595         <xvcmpnedp>: Likewise.
 596         <xvcmpnedp.>: Likewise.
 597         <xvcmpnesp>: Likewise.
 598         <xvcmpnesp.>: Likewise.
 599
 600 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 601
 602         PR gas/13050
 603         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 604         addition to ISA_A.
 605
 606 2016-01-01  Alan Modra  <amodra@gmail.com>
 607
 608         Update year range in copyright notice of all files.
 609
 610 For older changes see ChangeLog-2015
 611 \f
 612 Copyright (C) 2016 Free Software Foundation, Inc.
 613
 614 Copying and distribution of this file, with or without modification,
 615 are permitted in any medium without royalty provided the copyright
 616 notice and this notice are preserved.
 617
 618 Local Variables:
 619 mode: change-log
 620 left-margin: 8
 621 fill-column: 74
 622 version-control: never
 623 End: