opcodes/ChangeLog

   1 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
   4         meaningless.
   5         * i386-tbl.h: Re-generate.
   6
   7 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
  10         meaningless.
  11         * i386-tbl.h: Re-generate.
  12
  13 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
  16         meaningless.
  17         * i386-tbl.h: Re-generate.
  18
  19 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  20
  21         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
  22         meaningless.
  23         * i386-tbl.h: Re-generate.
  24
  25 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
  28         meaningless.
  29         * i386-tbl.h: Re-generate.
  30
  31 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  32
  33         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
  34         * i386-tbl.h: Re-generate.
  35
  36 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
  39         * i386-tbl.h: Re-generate.
  40
  41 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
  44         meaningless.
  45         * i386-tbl.h: Re-generate.
  46
  47 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  48
  49         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
  50         meaningless.
  51         * i386-tbl.h: Re-generate.
  52
  53 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  54
  55         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
  56         * i386-tbl.h: Re-generate.
  57
  58 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  59
  60         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
  61         * i386-tbl.h: Re-generate.
  62
  63 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  64
  65         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
  66         * i386-tbl.h: Re-generate.
  67
  68 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  69
  70         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
  71         meaningless.
  72         * i386-tbl.h: Re-generate.
  73
  74 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
  77         meaningless.
  78         * i386-tbl.h: Re-generate.
  79
  80 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  81
  82         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
  83         meaningless.
  84         * i386-tbl.h: Re-generate.
  85
  86 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  87
  88         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
  89         * i386-tbl.h: Re-generate.
  90
  91 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
  94         * i386-tbl.h: Re-generate.
  95
  96 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
  99         * i386-tbl.h: Re-generate.
 100
 101 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 102
 103         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 104         (vpbroadcastw, rdpid): Drop NoRex64.
 105         * i386-tbl.h: Re-generate.
 106
 107 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 110         store templates, adding D.
 111         * i386-tbl.h: Re-generate.
 112
 113 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 116         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 117         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 118         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 119         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 120         Fold load and store templates where possible, adding D. Drop
 121         IgnoreSize where it was pointlessly present. Drop redundant
 122         *word.
 123         * i386-tbl.h: Re-generate.
 124
 125 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 128         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 129         (intel_operand_size): Handle v_bndmk_mode.
 130         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 131
 132 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 133
 134         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 135
 136 2018-08-31  Kito Cheng  <kito@andestech.com>
 137
 138         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 139         compressed floating point instructions.
 140
 141 2018-08-30  Kito Cheng  <kito@andestech.com>
 142
 143         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 144         riscv_opcode.xlen_requirement.
 145         * riscv-opc.c (riscv_opcodes): Update for struct change.
 146
 147 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 148
 149         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 150         psr (PWRPSR) instruction.
 151
 152 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 153
 154         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 155
 156 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 157
 158         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 159
 160 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 161
 162         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 163         loongson3a as an alias of gs464 for compatibility.
 164         * mips-opc.c (mips_opcodes): Change Comments.
 165
 166 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 167
 168         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 169         option.
 170         (print_mips_disassembler_options): Document -M loongson-ext.
 171         * mips-opc.c (LEXT2): New macro.
 172         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 173
 174 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 175
 176          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 177          descriptors.
 178          (parse_mips_ase_option): Handle -M loongson-ext option.
 179          (print_mips_disassembler_options): Document -M loongson-ext.
 180          * mips-opc.c (IL3A): Delete.
 181          * mips-opc.c (LEXT): New macro.
 182          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 183          instructions.
 184
 185 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 186
 187         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 188         descriptors.
 189         (parse_mips_ase_option): Handle -M loongson-cam option.
 190         (print_mips_disassembler_options): Document -M loongson-cam.
 191         * mips-opc.c (LCAM): New macro.
 192         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 193         instructions.
 194
 195 2018-08-21  Alan Modra  <amodra@gmail.com>
 196
 197         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 198         (skip_optional_operands): Count optional operands, and update
 199         ppc_optional_operand_value call.
 200         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 201         (extract_vlensi): Likewise.
 202         (extract_fxm): Return default value for missing optional operand.
 203         (extract_ls, extract_raq, extract_tbr): Likewise.
 204         (insert_sxl, extract_sxl): New functions.
 205         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 206         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 207         flag and extra entry.
 208         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 209         extract_sxl.
 210
 211 2018-08-20  Alan Modra  <amodra@gmail.com>
 212
 213         * sh-opc.h (MASK): Simplify.
 214
 215 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 216
 217         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 218         BM_RESERVED0 or BM_RESERVED1
 219         (bm_rel_decode, bm_n_bytes): Ditto.
 220
 221 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 222
 223         * s12z.h: Delete.
 224
 225 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 226
 227         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 228         address with the addr32 prefix and without base nor index
 229         registers.
 230
 231 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 232
 233         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 234         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 235         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 236         (cpu_flags): Add CpuCMOV and CpuFXSR.
 237         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 238         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 239         * i386-init.h: Regenerated.
 240         * i386-tbl.h: Likewise.
 241
 242 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 243
 244         * arc-regs.h: Update auxiliary registers.
 245
 246 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 249         (RegIP, RegIZ): Define.
 250         * i386-reg.tbl: Adjust comments.
 251         (rip): Use Qword instead of BaseIndex. Use RegIP.
 252         (eip): Use Dword instead of BaseIndex. Use RegIP.
 253         (riz): Add Qword. Use RegIZ.
 254         (eiz): Add Dword. Use RegIZ.
 255         * i386-tbl.h: Re-generate.
 256
 257 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 258
 259         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 260         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 261         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 262         * i386-tbl.h: Re-generate.
 263
 264 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-gen.c (operand_types): Remove Mem field.
 267         * i386-opc.h (union i386_operand_type): Remove mem field.
 268         * i386-init.h, i386-tbl.h: Re-generate.
 269
 270 2018-08-01  Alan Modra  <amodra@gmail.com>
 271
 272         * po/POTFILES.in: Regenerate.
 273
 274 2018-07-31  Nick Clifton  <nickc@redhat.com>
 275
 276         * po/sv.po: Updated Swedish translation.
 277
 278 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 279
 280         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 281         * i386-init.h, i386-tbl.h: Re-generate.
 282
 283 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 284
 285         * i386-opc.h (ZEROING_MASKING) Rename to ...
 286         (DYNAMIC_MASKING): ... this. Adjust comment.
 287         * i386-opc.tbl (MaskingMorZ): Define.
 288         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 289         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 290         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 291         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 292         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 293         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 294         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 295         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 296         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 297
 298 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-opc.tbl: Use element rather than vector size for AVX512*
 301         scatter/gather insns.
 302         * i386-tbl.h: Re-generate.
 303
 304 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 305
 306         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 307         (cpu_flags): Drop CpuVREX.
 308         * i386-opc.h (CpuVREX): Delete.
 309         (union i386_cpu_flags): Remove cpuvrex.
 310         * i386-init.h, i386-tbl.h: Re-generate.
 311
 312 2018-07-30  Jim Wilson  <jimw@sifive.com>
 313
 314         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 315         fields.
 316         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 317
 318 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 319
 320         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 321         * Makefile.in: Regenerated.
 322         * configure.ac: Add C-SKY.
 323         * configure: Regenerated.
 324         * csky-dis.c: New file.
 325         * csky-opc.h: New file.
 326         * disassemble.c (ARCH_csky): Define.
 327         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 328         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 329
 330 2018-07-27  Alan Modra  <amodra@gmail.com>
 331
 332         * ppc-opc.c (insert_sprbat): Correct function parameter and
 333         return type.
 334         (extract_sprbat): Likewise, variable too.
 335
 336 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 337             Alan Modra  <amodra@gmail.com>
 338
 339         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 340         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 341         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 342         support disjointed BAT.
 343         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 344         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 345         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 346
 347 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 348             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 349
 350         * i386-gen.c (adjust_broadcast_modifier): New function.
 351         (process_i386_opcode_modifier): Add an argument for operands.
 352         Adjust the Broadcast value based on operands.
 353         (output_i386_opcode): Pass operand_types to
 354         process_i386_opcode_modifier.
 355         (process_i386_opcodes): Pass NULL as operands to
 356         process_i386_opcode_modifier.
 357         * i386-opc.h (BYTE_BROADCAST): New.
 358         (WORD_BROADCAST): Likewise.
 359         (DWORD_BROADCAST): Likewise.
 360         (QWORD_BROADCAST): Likewise.
 361         (i386_opcode_modifier): Expand broadcast to 3 bits.
 362         * i386-tbl.h: Regenerated.
 363
 364 2018-07-24  Alan Modra  <amodra@gmail.com>
 365
 366         PR 23430
 367         * or1k-desc.h: Regenerate.
 368
 369 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 370
 371         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 372         vcvtusi2ss, and vcvtusi2sd.
 373         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 374         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 375         * i386-tbl.h: Re-generate.
 376
 377 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 378
 379         * arc-opc.c (extract_w6): Fix extending the sign.
 380
 381 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 382
 383         * arc-tbl.h (vewt): Allow it for ARC EM family.
 384
 385 2018-07-23  Alan Modra  <amodra@gmail.com>
 386
 387         PR 23419
 388         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 389         opcode variants for mtspr/mfspr encodings.
 390
 391 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 392             Maciej W. Rozycki  <macro@mips.com>
 393
 394         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 395         loongson3a descriptors.
 396         (parse_mips_ase_option): Handle -M loongson-mmi option.
 397         (print_mips_disassembler_options): Document -M loongson-mmi.
 398         * mips-opc.c (LMMI): New macro.
 399         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 400         instructions.
 401
 402 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 403
 404         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 405         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 406         IgnoreSize and [XYZ]MMword where applicable.
 407         * i386-tbl.h: Re-generate.
 408
 409 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 410
 411         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 412         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 413         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 414         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 415         * i386-tbl.h: Re-generate.
 416
 417 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 418
 419         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 420         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 421         VPCLMULQDQ templates into their respective AVX512VL counterparts
 422         where possible, using Disp8ShiftVL and CheckRegSize instead of
 423         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 424         * i386-tbl.h: Re-generate.
 425
 426 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 427
 428         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 429         AVX512VL counterparts where possible, using Disp8ShiftVL and
 430         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 431         IgnoreSize) as appropriate.
 432         * i386-tbl.h: Re-generate.
 433
 434 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 435
 436         * i386-opc.tbl: Fold AVX512BW templates into their respective
 437         AVX512VL counterparts where possible, using Disp8ShiftVL and
 438         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 439         IgnoreSize) as appropriate.
 440         * i386-tbl.h: Re-generate.
 441
 442 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 443
 444         * i386-opc.tbl: Fold AVX512CD templates into their respective
 445         AVX512VL counterparts where possible, using Disp8ShiftVL and
 446         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 447         IgnoreSize) as appropriate.
 448         * i386-tbl.h: Re-generate.
 449
 450 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 451
 452         * i386-opc.h (DISP8_SHIFT_VL): New.
 453         * i386-opc.tbl (Disp8ShiftVL):  Define.
 454         (various): Fold AVX512VL templates into their respective
 455         AVX512F counterparts where possible, using Disp8ShiftVL and
 456         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 457         IgnoreSize) as appropriate.
 458         * i386-tbl.h: Re-generate.
 459
 460 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 461
 462         * Makefile.am: Change dependencies and rule for
 463         $(srcdir)/i386-init.h.
 464         * Makefile.in: Re-generate.
 465         * i386-gen.c (process_i386_opcodes): New local variable
 466         "marker". Drop opening of input file. Recognize marker and line
 467         number directives.
 468         * i386-opc.tbl (OPCODE_I386_H): Define.
 469         (i386-opc.h): Include it.
 470         (None): Undefine.
 471
 472 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 473
 474         PR gas/23418
 475         * i386-opc.h (Byte): Update comments.
 476         (Word): Likewise.
 477         (Dword): Likewise.
 478         (Fword): Likewise.
 479         (Qword): Likewise.
 480         (Tbyte): Likewise.
 481         (Xmmword): Likewise.
 482         (Ymmword): Likewise.
 483         (Zmmword): Likewise.
 484         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 485         vcvttps2uqq.
 486         * i386-tbl.h: Regenerated.
 487
 488 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 489
 490         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 491         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 492         * aarch64-asm-2.c: Regenerate.
 493         * aarch64-dis-2.c: Regenerate.
 494         * aarch64-opc-2.c: Regenerate.
 495
 496 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 497
 498         PR binutils/23192
 499         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 500         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 501         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 502         sqdmulh, sqrdmulh): Use Em16.
 503
 504 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 505
 506         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 507         csdb together with them.
 508         (thumb32_opcodes): Likewise.
 509
 510 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 511
 512         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 513         requiring 32-bit registers as operands 2 and 3. Improve
 514         comments.
 515         (mwait, mwaitx): Fold templates. Improve comments.
 516         OPERAND_TYPE_INOUTPORTREG.
 517         * i386-tbl.h: Re-generate.
 518
 519 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 520
 521         * i386-gen.c (operand_type_init): Remove
 522         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 523         OPERAND_TYPE_INOUTPORTREG.
 524         * i386-init.h: Re-generate.
 525
 526 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 527
 528         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 529         (wrssq, wrussq): Add Qword.
 530         * i386-tbl.h: Re-generate.
 531
 532 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 533
 534         * i386-opc.h: Rename OTMax to OTNum.
 535         (OTNumOfUints): Adjust calculation.
 536         (OTUnused): Directly alias to OTNum.
 537
 538 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 539
 540         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 541         `reg_xys'.
 542         (lea_reg_xys): Likewise.
 543         (print_insn_loop_primitive): Rename `reg' local variable to
 544         `reg_dxy'.
 545
 546 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 547
 548         PR binutils/23242
 549         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 550
 551 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 552
 553         PR binutils/23369
 554         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 555         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 556
 557 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 558
 559         PR tdep/8282
 560         * mips-dis.c (mips_option_arg_t): New enumeration.
 561         (mips_options): New variable.
 562         (disassembler_options_mips): New function.
 563         (print_mips_disassembler_options): Reimplement in terms of
 564         `disassembler_options_mips'.
 565         * arm-dis.c (disassembler_options_arm): Adapt to using the
 566         `disasm_options_and_args_t' structure.
 567         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 568         * s390-dis.c (disassembler_options_s390): Likewise.
 569
 570 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 571
 572         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 573         expected result.
 574         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 575         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 576         * testsuite/ld-arm/tls-longplt.d: Likewise.
 577
 578 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 579
 580         PR binutils/23192
 581         * aarch64-asm-2.c: Regenerate.
 582         * aarch64-dis-2.c: Likewise.
 583         * aarch64-opc-2.c: Likewise.
 584         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 585         * aarch64-opc.c (operand_general_constraint_met_p,
 586         aarch64_print_operand): Likewise.
 587         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 588         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 589         fmlal2, fmlsl2.
 590         (AARCH64_OPERANDS): Add Em2.
 591
 592 2018-06-26  Nick Clifton  <nickc@redhat.com>
 593
 594         * po/uk.po: Updated Ukranian translation.
 595         * po/de.po: Updated German translation.
 596         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 597
 598 2018-06-26  Nick Clifton  <nickc@redhat.com>
 599
 600         * nfp-dis.c: Fix spelling mistake.
 601
 602 2018-06-24  Nick Clifton  <nickc@redhat.com>
 603
 604         * configure: Regenerate.
 605         * po/opcodes.pot: Regenerate.
 606
 607 2018-06-24  Nick Clifton  <nickc@redhat.com>
 608
 609         2.31 branch created.
 610
 611 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 612
 613         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 614         * aarch64-asm-2.c: Regenerate.
 615         * aarch64-dis-2.c: Likewise.
 616
 617 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 618
 619         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 620         `-M ginv' option description.
 621
 622 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 623
 624         PR gas/23305
 625         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 626         la and lla.
 627
 628 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 629
 630         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 631         * configure.ac: Remove AC_PREREQ.
 632         * Makefile.in: Re-generate.
 633         * aclocal.m4: Re-generate.
 634         * configure: Re-generate.
 635
 636 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 637
 638         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 639         mips64r6 descriptors.
 640         (parse_mips_ase_option): Handle -Mginv option.
 641         (print_mips_disassembler_options): Document -Mginv.
 642         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 643         (GINV): New macro.
 644         (mips_opcodes): Define ginvi and ginvt.
 645
 646 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 647             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 648
 649         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 650         * mips-opc.c (CRC, CRC64): New macros.
 651         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 652         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 653         crc32cd for CRC64.
 654
 655 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 656
 657         PR 20319
 658         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 659         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 660
 661 2018-06-06  Alan Modra  <amodra@gmail.com>
 662
 663         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 664         setjmp.  Move init for some other vars later too.
 665
 666 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 667
 668         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 669         (dis_private): Add new fields for property section tracking.
 670         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 671         (xtensa_instruction_fits): New functions.
 672         (fetch_data): Bump minimal fetch size to 4.
 673         (print_insn_xtensa): Make struct dis_private static.
 674         Load and prepare property table on section change.
 675         Don't disassemble literals. Don't disassemble instructions that
 676         cross property table boundaries.
 677
 678 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 679
 680         * configure: Regenerated.
 681
 682 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 683
 684         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 685         * i386-tbl.h: Re-generate.
 686
 687 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 688
 689         * i386-opc.tbl (sldt, str): Add NoRex64.
 690         * i386-tbl.h: Re-generate.
 691
 692 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-opc.tbl (invpcid): Add Oword.
 695         * i386-tbl.h: Re-generate.
 696
 697 2018-06-01  Alan Modra  <amodra@gmail.com>
 698
 699         * sysdep.h (_bfd_error_handler): Don't declare.
 700         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 701         * rl78-decode.opc: Likewise.
 702         * msp430-decode.c: Regenerate.
 703         * rl78-decode.c: Regenerate.
 704
 705 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 706
 707         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 708         * i386-init.h : Regenerated.
 709
 710 2018-05-25  Alan Modra  <amodra@gmail.com>
 711
 712         * Makefile.in: Regenerate.
 713         * po/POTFILES.in: Regenerate.
 714
 715 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 716
 717         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 718         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 719         (insert_bab, extract_bab, insert_btab, extract_btab,
 720         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 721         (BAT, BBA VBA RBS XB6S): Delete macros.
 722         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 723         (BB, BD, RBX, XC6): Update for new macros.
 724         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 725         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 726         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 727         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 728
 729 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 730
 731         * Makefile.am: Add support for s12z architecture.
 732         * configure.ac: Likewise.
 733         * disassemble.c: Likewise.
 734         * disassemble.h: Likewise.
 735         * Makefile.in: Regenerate.
 736         * configure: Regenerate.
 737         * s12z-dis.c: New file.
 738         * s12z.h: New file.
 739
 740 2018-05-18  Alan Modra  <amodra@gmail.com>
 741
 742         * nfp-dis.c: Don't #include libbfd.h.
 743         (init_nfp3200_priv): Use bfd_get_section_contents.
 744         (nit_nfp6000_mecsr_sec): Likewise.
 745
 746 2018-05-17  Nick Clifton  <nickc@redhat.com>
 747
 748         * po/zh_CN.po: Updated simplified Chinese translation.
 749
 750 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 751
 752         PR binutils/23109
 753         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 754         * aarch64-dis-2.c: Regenerate.
 755
 756 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 757
 758         PR binutils/21446
 759         * aarch64-asm.c (opintl.h): Include.
 760         (aarch64_ins_sysreg): Enforce read/write constraints.
 761         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 762         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 763         (F_REG_READ, F_REG_WRITE): New.
 764         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 765         AARCH64_OPND_SYSREG.
 766         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 767         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 768         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 769         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 770         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 771         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 772         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 773         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 774         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 775         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 776         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 777         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 778         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 779         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 780         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 781         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 782         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 783
 784 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 785
 786         PR binutils/21446
 787         * aarch64-dis.c (no_notes: New.
 788         (parse_aarch64_dis_option): Support notes.
 789         (aarch64_decode_insn, print_operands): Likewise.
 790         (print_aarch64_disassembler_options): Document notes.
 791         * aarch64-opc.c (aarch64_print_operand): Support notes.
 792
 793 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 794
 795         PR binutils/21446
 796         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 797         and take error struct.
 798         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 799         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 800         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 801         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 802         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 803         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 804         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 805         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 806         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 807         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 808         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 809         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 810         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 811         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 812         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 813         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 814         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 815         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 816         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 817         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 818         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 819         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 820         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 821         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 822         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 823         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 824         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 825         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 826         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 827         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 828         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 829         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 830         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 831         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 832         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 833         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 834         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 835         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 836         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 837         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 838         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 839         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 840         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 841         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 842         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 843         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 844         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 845         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 846         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 847         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 848         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 849         (determine_disassembling_preference, aarch64_decode_insn,
 850         print_insn_aarch64_word, print_insn_data): Take errors struct.
 851         (print_insn_aarch64): Use errors.
 852         * aarch64-asm-2.c: Regenerate.
 853         * aarch64-dis-2.c: Regenerate.
 854         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 855         boolean in aarch64_insert_operan.
 856         (print_operand_extractor): Likewise.
 857         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 858
 859 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 860
 861         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 862
 863 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 864
 865         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 866
 867 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 868
 869         * cr16-opc.c (cr16_instruction): Comment typo fix.
 870         * hppa-dis.c (print_insn_hppa): Likewise.
 871
 872 2018-05-08  Jim Wilson  <jimw@sifive.com>
 873
 874         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 875         (match_c_slli64, match_srxi_as_c_srxi): New.
 876         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 877         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 878         <c.slli, c.srli, c.srai>: Use match_s_slli.
 879         <c.slli64, c.srli64, c.srai64>: New.
 880
 881 2018-05-08  Alan Modra  <amodra@gmail.com>
 882
 883         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 884         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 885         partition opcode space for index lookup.
 886
 887 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 888
 889         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 890         <insn_length>: ...with this.  Update usage.
 891         Remove duplicate call to *info->memory_error_func.
 892
 893 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 894             H.J. Lu  <hongjiu.lu@intel.com>
 895
 896         * i386-dis.c (Gva): New.
 897         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 898         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 899         (prefix_table): New instructions (see prefix above).
 900         (mod_table): New instructions (see prefix above).
 901         (OP_G): Handle va_mode.
 902         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 903         CPU_MOVDIR64B_FLAGS.
 904         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 905         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 906         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 907         * i386-opc.tbl: Add movidir{i,64b}.
 908         * i386-init.h: Regenerated.
 909         * i386-tbl.h: Likewise.
 910
 911 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 912
 913         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 914         AddrPrefixOpReg.
 915         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 916         (AddrPrefixOpReg): This.
 917         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 918         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 919
 920 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 921
 922         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 923         (vle_num_opcodes): Likewise.
 924         (spe2_num_opcodes): Likewise.
 925         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 926         initialization loop.
 927         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 928         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 929         only once.
 930
 931 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 932
 933         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 934
 935 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 936
 937         Makefile.am: Added nfp-dis.c.
 938         configure.ac: Added bfd_nfp_arch.
 939         disassemble.h: Added print_insn_nfp prototype.
 940         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 941         nfp-dis.c: New, for NFP support.
 942         po/POTFILES.in: Added nfp-dis.c to the list.
 943         Makefile.in: Regenerate.
 944         configure: Regenerate.
 945
 946 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 949         templates into their base ones.
 950         * i386-tlb.h: Re-generate.
 951
 952 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 955         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 956         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 957         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 958         * i386-init.h: Re-generate.
 959
 960 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 961
 962         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 963         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 964         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 965         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 966         comment.
 967         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 968         and CpuRegMask.
 969         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 970         CpuRegMask: Delete.
 971         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 972         cpuregzmm, and cpuregmask.
 973         * i386-init.h: Re-generate.
 974         * i386-tbl.h: Re-generate.
 975
 976 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 977
 978         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 979         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 980         * i386-init.h: Re-generate.
 981
 982 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-gen.c (VexImmExt): Delete.
 985         * i386-opc.h (VexImmExt, veximmext): Delete.
 986         * i386-opc.tbl: Drop all VexImmExt uses.
 987         * i386-tlb.h: Re-generate.
 988
 989 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 990
 991         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 992         register-only forms.
 993         * i386-tlb.h: Re-generate.
 994
 995 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 996
 997         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 998
 999 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1000
1001         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1002         PREFIX_0F1C.
1003         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1004         (cpu_flags): Add CpuCLDEMOTE.
1005         * i386-init.h: Regenerate.
1006         * i386-opc.h (enum): Add CpuCLDEMOTE,
1007         (i386_cpu_flags): Add cpucldemote.
1008         * i386-opc.tbl: Add cldemote.
1009         * i386-tbl.h: Regenerate.
1010
1011 2018-04-16  Alan Modra  <amodra@gmail.com>
1012
1013         * Makefile.am: Remove sh5 and sh64 support.
1014         * configure.ac: Likewise.
1015         * disassemble.c: Likewise.
1016         * disassemble.h: Likewise.
1017         * sh-dis.c: Likewise.
1018         * sh64-dis.c: Delete.
1019         * sh64-opc.c: Delete.
1020         * sh64-opc.h: Delete.
1021         * Makefile.in: Regenerate.
1022         * configure: Regenerate.
1023         * po/POTFILES.in: Regenerate.
1024
1025 2018-04-16  Alan Modra  <amodra@gmail.com>
1026
1027         * Makefile.am: Remove w65 support.
1028         * configure.ac: Likewise.
1029         * disassemble.c: Likewise.
1030         * disassemble.h: Likewise.
1031         * w65-dis.c: Delete.
1032         * w65-opc.h: Delete.
1033         * Makefile.in: Regenerate.
1034         * configure: Regenerate.
1035         * po/POTFILES.in: Regenerate.
1036
1037 2018-04-16  Alan Modra  <amodra@gmail.com>
1038
1039         * configure.ac: Remove we32k support.
1040         * configure: Regenerate.
1041
1042 2018-04-16  Alan Modra  <amodra@gmail.com>
1043
1044         * Makefile.am: Remove m88k support.
1045         * configure.ac: Likewise.
1046         * disassemble.c: Likewise.
1047         * disassemble.h: Likewise.
1048         * m88k-dis.c: Delete.
1049         * Makefile.in: Regenerate.
1050         * configure: Regenerate.
1051         * po/POTFILES.in: Regenerate.
1052
1053 2018-04-16  Alan Modra  <amodra@gmail.com>
1054
1055         * Makefile.am: Remove i370 support.
1056         * configure.ac: Likewise.
1057         * disassemble.c: Likewise.
1058         * disassemble.h: Likewise.
1059         * i370-dis.c: Delete.
1060         * i370-opc.c: Delete.
1061         * Makefile.in: Regenerate.
1062         * configure: Regenerate.
1063         * po/POTFILES.in: Regenerate.
1064
1065 2018-04-16  Alan Modra  <amodra@gmail.com>
1066
1067         * Makefile.am: Remove h8500 support.
1068         * configure.ac: Likewise.
1069         * disassemble.c: Likewise.
1070         * disassemble.h: Likewise.
1071         * h8500-dis.c: Delete.
1072         * h8500-opc.h: Delete.
1073         * Makefile.in: Regenerate.
1074         * configure: Regenerate.
1075         * po/POTFILES.in: Regenerate.
1076
1077 2018-04-16  Alan Modra  <amodra@gmail.com>
1078
1079         * configure.ac: Remove tahoe support.
1080         * configure: Regenerate.
1081
1082 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1083
1084         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1085         umwait.
1086         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1087         64-bit mode.
1088         * i386-tbl.h: Regenerated.
1089
1090 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1091
1092         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1093         PREFIX_MOD_1_0FAE_REG_6.
1094         (va_mode): New.
1095         (OP_E_register): Use va_mode.
1096         * i386-dis-evex.h (prefix_table):
1097         New instructions (see prefixes above).
1098         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1099         (cpu_flags): Likewise.
1100         * i386-opc.h (enum): Likewise.
1101         (i386_cpu_flags): Likewise.
1102         * i386-opc.tbl: Add umonitor, umwait, tpause.
1103         * i386-init.h: Regenerate.
1104         * i386-tbl.h: Likewise.
1105
1106 2018-04-11  Alan Modra  <amodra@gmail.com>
1107
1108         * opcodes/i860-dis.c: Delete.
1109         * opcodes/i960-dis.c: Delete.
1110         * Makefile.am: Remove i860 and i960 support.
1111         * configure.ac: Likewise.
1112         * disassemble.c: Likewise.
1113         * disassemble.h: Likewise.
1114         * Makefile.in: Regenerate.
1115         * configure: Regenerate.
1116         * po/POTFILES.in: Regenerate.
1117
1118 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1119
1120         PR binutils/23025
1121         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1122         to 0.
1123         (print_insn): Clear vex instead of vex.evex.
1124
1125 2018-04-04  Nick Clifton  <nickc@redhat.com>
1126
1127         * po/es.po: Updated Spanish translation.
1128
1129 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1130
1131         * i386-gen.c (opcode_modifiers): Delete VecESize.
1132         * i386-opc.h (VecESize): Delete.
1133         (struct i386_opcode_modifier): Delete vecesize.
1134         * i386-opc.tbl: Drop VecESize.
1135         * i386-tlb.h: Re-generate.
1136
1137 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1140         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1141         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1142         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1143         * i386-tlb.h: Re-generate.
1144
1145 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1146
1147         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1148         Fold AVX512 forms
1149         * i386-tlb.h: Re-generate.
1150
1151 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1152
1153         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1154         (vex_len_table): Drop Y for vcvt*2si.
1155         (putop): Replace plain 'Y' handling by abort().
1156
1157 2018-03-28  Nick Clifton  <nickc@redhat.com>
1158
1159         PR 22988
1160         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1161         instructions with only a base address register.
1162         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1163         handle AARHC64_OPND_SVE_ADDR_R.
1164         (aarch64_print_operand): Likewise.
1165         * aarch64-asm-2.c: Regenerate.
1166         * aarch64_dis-2.c: Regenerate.
1167         * aarch64-opc-2.c: Regenerate.
1168
1169 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1170
1171         * i386-opc.tbl: Drop VecESize from register only insn forms and
1172         memory forms not allowing broadcast.
1173         * i386-tlb.h: Re-generate.
1174
1175 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1176
1177         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1178         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1179         sha256*): Drop Disp<N>.
1180
1181 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1182
1183         * i386-dis.c (EbndS, bnd_swap_mode): New.
1184         (prefix_table): Use EbndS.
1185         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1186         * i386-opc.tbl (bndmov): Move misplaced Load.
1187         * i386-tlb.h: Re-generate.
1188
1189 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1190
1191         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1192         templates allowing memory operands and folded ones for register
1193         only flavors.
1194         * i386-tlb.h: Re-generate.
1195
1196 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1197
1198         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1199         256-bit templates. Drop redundant leftover Disp<N>.
1200         * i386-tlb.h: Re-generate.
1201
1202 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1203
1204         * riscv-opc.c (riscv_insn_types): New.
1205
1206 2018-03-13  Nick Clifton  <nickc@redhat.com>
1207
1208         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1209
1210 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1211
1212         * i386-opc.tbl: Add Optimize to clr.
1213         * i386-tbl.h: Regenerated.
1214
1215 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1216
1217         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1218         * i386-opc.h (OldGcc): Removed.
1219         (i386_opcode_modifier): Remove oldgcc.
1220         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1221         instructions for old (<= 2.8.1) versions of gcc.
1222         * i386-tbl.h: Regenerated.
1223
1224 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1225
1226         * i386-opc.h (EVEXDYN): New.
1227         * i386-opc.tbl: Fold various AVX512VL templates.
1228         * i386-tlb.h: Re-generate.
1229
1230 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1231
1232         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1233         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1234         vpexpandd, vpexpandq): Fold AFX512VF templates.
1235         * i386-tlb.h: Re-generate.
1236
1237 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1238
1239         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1240         Fold 128- and 256-bit VEX-encoded templates.
1241         * i386-tlb.h: Re-generate.
1242
1243 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1244
1245         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1246         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1247         vpexpandd, vpexpandq): Fold AVX512F templates.
1248         * i386-tlb.h: Re-generate.
1249
1250 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1251
1252         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1253         64-bit templates. Drop Disp<N>.
1254         * i386-tlb.h: Re-generate.
1255
1256 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1257
1258         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1259         and 256-bit templates.
1260         * i386-tlb.h: Re-generate.
1261
1262 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1263
1264         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1265         * i386-tlb.h: Re-generate.
1266
1267 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1268
1269         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1270         Drop NoAVX.
1271         * i386-tlb.h: Re-generate.
1272
1273 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1274
1275         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1276         * i386-tlb.h: Re-generate.
1277
1278 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1279
1280         * i386-gen.c (opcode_modifiers): Delete FloatD.
1281         * i386-opc.h (FloatD): Delete.
1282         (struct i386_opcode_modifier): Delete floatd.
1283         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1284         FloatD by D.
1285         * i386-tlb.h: Re-generate.
1286
1287 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1288
1289         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1290
1291 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1292
1293         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1294         * i386-tlb.h: Re-generate.
1295
1296 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1297
1298         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1299         forms.
1300         * i386-tlb.h: Re-generate.
1301
1302 2018-03-07  Alan Modra  <amodra@gmail.com>
1303
1304         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1305         bfd_arch_rs6000.
1306         * disassemble.h (print_insn_rs6000): Delete.
1307         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1308         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1309         (print_insn_rs6000): Delete.
1310
1311 2018-03-03  Alan Modra  <amodra@gmail.com>
1312
1313         * sysdep.h (opcodes_error_handler): Define.
1314         (_bfd_error_handler): Declare.
1315         * Makefile.am: Remove stray #.
1316         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1317         EDIT" comment.
1318         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1319         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1320         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1321         opcodes_error_handler to print errors.  Standardize error messages.
1322         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1323         and include opintl.h.
1324         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1325         * i386-gen.c: Standardize error messages.
1326         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1327         * Makefile.in: Regenerate.
1328         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1329         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1330         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1331         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1332         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1333         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1334         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1335         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1336         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1337         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1338         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1339         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1340         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1341
1342 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1343
1344         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1345         vpsub[bwdq] instructions.
1346         * i386-tbl.h: Regenerated.
1347
1348 2018-03-01  Alan Modra  <amodra@gmail.com>
1349
1350         * configure.ac (ALL_LINGUAS): Sort.
1351         * configure: Regenerate.
1352
1353 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1354
1355         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1356         macro by assignements.
1357
1358 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1359
1360         PR gas/22871
1361         * i386-gen.c (opcode_modifiers): Add Optimize.
1362         * i386-opc.h (Optimize): New enum.
1363         (i386_opcode_modifier): Add optimize.
1364         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1365         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1366         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1367         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1368         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1369         vpxord and vpxorq.
1370         * i386-tbl.h: Regenerated.
1371
1372 2018-02-26  Alan Modra  <amodra@gmail.com>
1373
1374         * crx-dis.c (getregliststring): Allocate a large enough buffer
1375         to silence false positive gcc8 warning.
1376
1377 2018-02-22  Shea Levy <shea@shealevy.com>
1378
1379         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1380
1381 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1382
1383         * i386-opc.tbl: Add {rex},
1384         * i386-tbl.h: Regenerated.
1385
1386 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1387
1388         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1389         (mips16_opcodes): Replace `M' with `m' for "restore".
1390
1391 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1392
1393         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1394
1395 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1396
1397         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1398         variable to `function_index'.
1399
1400 2018-02-13  Nick Clifton  <nickc@redhat.com>
1401
1402         PR 22823
1403         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1404         about truncation of printing.
1405
1406 2018-02-12  Henry Wong <henry@stuffedcow.net>
1407
1408         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1409
1410 2018-02-05  Nick Clifton  <nickc@redhat.com>
1411
1412         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1413
1414 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1415
1416         * i386-dis.c (enum): Add pconfig.
1417         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1418         (cpu_flags): Add CpuPCONFIG.
1419         * i386-opc.h (enum): Add CpuPCONFIG.
1420         (i386_cpu_flags): Add cpupconfig.
1421         * i386-opc.tbl: Add PCONFIG instruction.
1422         * i386-init.h: Regenerate.
1423         * i386-tbl.h: Likewise.
1424
1425 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1426
1427         * i386-dis.c (enum): Add PREFIX_0F09.
1428         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1429         (cpu_flags): Add CpuWBNOINVD.
1430         * i386-opc.h (enum): Add CpuWBNOINVD.
1431         (i386_cpu_flags): Add cpuwbnoinvd.
1432         * i386-opc.tbl: Add WBNOINVD instruction.
1433         * i386-init.h: Regenerate.
1434         * i386-tbl.h: Likewise.
1435
1436 2018-01-17  Jim Wilson  <jimw@sifive.com>
1437
1438         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1439
1440 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1441
1442         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1443         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1444         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1445         (cpu_flags): Add CpuIBT, CpuSHSTK.
1446         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1447         (i386_cpu_flags): Add cpuibt, cpushstk.
1448         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1449         * i386-init.h: Regenerate.
1450         * i386-tbl.h: Likewise.
1451
1452 2018-01-16  Nick Clifton  <nickc@redhat.com>
1453
1454         * po/pt_BR.po: Updated Brazilian Portugese translation.
1455         * po/de.po: Updated German translation.
1456
1457 2018-01-15  Jim Wilson  <jimw@sifive.com>
1458
1459         * riscv-opc.c (match_c_nop): New.
1460         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1461
1462 2018-01-15  Nick Clifton  <nickc@redhat.com>
1463
1464         * po/uk.po: Updated Ukranian translation.
1465
1466 2018-01-13  Nick Clifton  <nickc@redhat.com>
1467
1468         * po/opcodes.pot: Regenerated.
1469
1470 2018-01-13  Nick Clifton  <nickc@redhat.com>
1471
1472         * configure: Regenerate.
1473
1474 2018-01-13  Nick Clifton  <nickc@redhat.com>
1475
1476         2.30 branch created.
1477
1478 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1479
1480         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1481         * i386-tbl.h: Regenerate.
1482
1483 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1484
1485         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1486         * i386-tbl.h: Re-generate.
1487
1488 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1489
1490         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1491         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1492         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1493         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1494         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1495         Disp8MemShift of AVX512VL forms.
1496         * i386-tbl.h: Re-generate.
1497
1498 2018-01-09  Jim Wilson  <jimw@sifive.com>
1499
1500         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1501         then the hi_addr value is zero.
1502
1503 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1504
1505         * arm-dis.c (arm_opcodes): Add csdb.
1506         (thumb32_opcodes): Add csdb.
1507
1508 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1509
1510         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1511         * aarch64-asm-2.c: Regenerate.
1512         * aarch64-dis-2.c: Regenerate.
1513         * aarch64-opc-2.c: Regenerate.
1514
1515 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1516
1517         PR gas/22681
1518         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1519         Remove AVX512 vmovd with 64-bit operands.
1520         * i386-tbl.h: Regenerated.
1521
1522 2018-01-05  Jim Wilson  <jimw@sifive.com>
1523
1524         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1525         jalr.
1526
1527 2018-01-03  Alan Modra  <amodra@gmail.com>
1528
1529         Update year range in copyright notice of all files.
1530
1531 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1532
1533         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1534         and OPERAND_TYPE_REGZMM entries.
1535
1536 For older changes see ChangeLog-2017
1537 \f
1538 Copyright (C) 2018 Free Software Foundation, Inc.
1539
1540 Copying and distribution of this file, with or without modification,
1541 are permitted in any medium without royalty provided the copyright
1542 notice and this notice are preserved.
1543
1544 Local Variables:
1545 mode: change-log
1546 left-margin: 8
1547 fill-column: 74
1548 version-control: never
1549 End: