opcodes/ChangeLog

   1 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
   2
   3         * aarch64-asm-2.c: Regenerated.
   4         * aarch64-dis-2.c: Regenerated.
   5         * aarch64-opc-2.c: Regenerated.
   6         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
   7         for SVE_IMM_ROT3.
   8         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
   9         (fields): Handle SVE_rot3 field.
  10         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
  11         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
  12
  13 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  14
  15         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
  16         instructions.
  17
  18 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  19
  20         * aarch64-tbl.h
  21         (aarch64_feature_sve2, aarch64_feature_sve2aes,
  22         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
  23         aarch64_feature_sve2bitperm): New feature sets.
  24         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
  25         for feature set addresses.
  26         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
  27         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
  28
  29 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
  30             Faraz Shahbazker  <fshahbazker@wavecomp.com>
  31
  32         * mips-dis.c (mips_calculate_combination_ases): Add ISA
  33         argument and set ASE_EVA_R6 appropriately.
  34         (set_default_mips_dis_options): Pass ISA to above.
  35         (parse_mips_dis_option): Likewise.
  36         * mips-opc.c (EVAR6): New macro.
  37         (mips_builtin_opcodes): Add llwpe, scwpe.
  38
  39 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
  40
  41         * aarch64-asm-2.c: Regenerated.
  42         * aarch64-dis-2.c: Regenerated.
  43         * aarch64-opc-2.c: Regenerated.
  44         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
  45         AARCH64_OPND_TME_UIMM16.
  46         (aarch64_print_operand): Likewise.
  47         * aarch64-tbl.h (QL_IMM_NIL): New.
  48         (TME): New.
  49         (_TME_INSN): New.
  50         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
  51
  52 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
  53
  54         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
  55
  56 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
  57             Faraz Shahbazker  <fshahbazker@wavecomp.com>
  58
  59         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
  60
  61 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
  62
  63         * s12z-opc.h: Add extern "C" bracketing to help
  64         users who wish to use this interface in c++ code.
  65
  66 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
  67
  68         * s12z-opc.c (bm_decode): Handle bit map operations with the
  69         "reserved0" mode.
  70
  71 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  72
  73         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
  74         specifier.  Add entries for VLDR and VSTR of system registers.
  75         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
  76         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
  77         of %J and %K format specifier.
  78
  79 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  80
  81         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
  82         Add new entries for VSCCLRM instruction.
  83         (print_insn_coprocessor): Handle new %C format control code.
  84
  85 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  86
  87         * arm-dis.c (enum isa): New enum.
  88         (struct sopcode32): New structure.
  89         (coprocessor_opcodes): change type of entries to struct sopcode32 and
  90         set isa field of all current entries to ANY.
  91         (print_insn_coprocessor): Change type of insn to struct sopcode32.
  92         Only match an entry if its isa field allows the current mode.
  93
  94 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  95
  96         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
  97         CLRM.
  98         (print_insn_thumb32): Add logic to print %n CLRM register list.
  99
 100 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 101
 102         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 103         and %Q patterns.
 104
 105 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 106
 107         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 108         (print_insn_thumb32): Edit the switch case for %Z.
 109
 110 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 111
 112         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 113
 114 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 115
 116         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 117
 118 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 119
 120         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 121
 122 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 123
 124         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 125         Arm register with r13 and r15 unpredictable.
 126         (thumb32_opcodes): New instructions for bfx and bflx.
 127
 128 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 129
 130         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 131
 132 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 133
 134         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 135
 136 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 137
 138         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 139
 140 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 141
 142         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 143
 144 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 145
 146         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 147         "optr". ("operator" is a reserved word in c++).
 148
 149 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 150
 151         * aarch64-opc.c (aarch64_print_operand): Add case for
 152         AARCH64_OPND_Rt_SP.
 153         (verify_constraints): Likewise.
 154         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 155         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 156         to accept Rt|SP as first operand.
 157         (AARCH64_OPERANDS): Add new Rt_SP.
 158         * aarch64-asm-2.c: Regenerated.
 159         * aarch64-dis-2.c: Regenerated.
 160         * aarch64-opc-2.c: Regenerated.
 161
 162 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 163
 164         * aarch64-asm-2.c: Regenerated.
 165         * aarch64-dis-2.c: Likewise.
 166         * aarch64-opc-2.c: Likewise.
 167         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 168
 169 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 170
 171         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 172
 173 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 174
 175         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 176         * i386-init.h: Regenerated.
 177
 178 2019-04-07  Alan Modra  <amodra@gmail.com>
 179
 180         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 181         op_separator to control printing of spaces, comma and parens
 182         rather than need_comma, need_paren and spaces vars.
 183
 184 2019-04-07  Alan Modra  <amodra@gmail.com>
 185
 186         PR 24421
 187         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 188         (print_insn_neon, print_insn_arm): Likewise.
 189
 190 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 191
 192         * i386-dis-evex.h (evex_table): Updated to support BF16
 193         instructions.
 194         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 195         and EVEX_W_0F3872_P_3.
 196         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 197         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 198         * i386-opc.h (enum): Add CpuAVX512_BF16.
 199         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 200         * i386-opc.tbl: Add AVX512 BF16 instructions.
 201         * i386-init.h: Regenerated.
 202         * i386-tbl.h: Likewise.
 203
 204 2019-04-05  Alan Modra  <amodra@gmail.com>
 205
 206         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 207         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 208         to favour printing of "-" branch hint when using the "y" bit.
 209         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 210
 211 2019-04-05  Alan Modra  <amodra@gmail.com>
 212
 213         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 214         opcode until first operand is output.
 215
 216 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 217
 218         PR gas/24349
 219         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 220         (valid_bo_post_v2): Add support for 'at' branch hints.
 221         (insert_bo): Only error on branch on ctr.
 222         (get_bo_hint_mask): New function.
 223         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 224         for inserting 'at' branch hints.
 225         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 226         for extracting 'at' branch hints.
 227         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 228         (BOE): Delete operand.
 229         (BOM, BOP): New operands.
 230         (RM): Update value.
 231         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 232         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 233         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 234         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 235         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 236         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 237         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 238         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 239         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 240         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 241         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 242         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 243         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 244         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 245         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 246         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 247         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 248         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 249         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 250         bttarl+>: New extended mnemonics.
 251
 252 2019-03-28  Alan Modra  <amodra@gmail.com>
 253
 254         PR 24390
 255         * ppc-opc.c (BTF): Define.
 256         (powerpc_opcodes): Use for mtfsb*.
 257         * ppc-dis.c (print_insn_powerpc): Print fields with both
 258         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 259
 260 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 261
 262         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 263         (mapping_symbol_for_insn): Implement new algorithm.
 264         (print_insn): Remove duplicate code.
 265
 266 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 267
 268         * aarch64-dis.c (print_insn_aarch64):
 269         Implement override.
 270
 271 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 272
 273         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 274         order.
 275
 276 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 277
 278         * aarch64-dis.c (last_stop_offset): New.
 279         (print_insn_aarch64): Use stop_offset.
 280
 281 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 282
 283         PR gas/24359
 284         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 285         CPU_ANY_AVX2_FLAGS.
 286         * i386-init.h: Regenerated.
 287
 288 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 289
 290         PR gas/24348
 291         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 292         vmovdqu16, vmovdqu32 and vmovdqu64.
 293         * i386-tbl.h: Regenerated.
 294
 295 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 296
 297         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 298         from vstrszb, vstrszh, and vstrszf.
 299
 300 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 301
 302         * s390-opc.txt: Add instruction descriptions.
 303
 304 2019-02-08  Jim Wilson  <jimw@sifive.com>
 305
 306         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 307         <bne>: Likewise.
 308
 309 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 310
 311         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 312
 313 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 314
 315         PR binutils/23212
 316         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 317         * aarch64-opc.c (verify_elem_sd): New.
 318         (fields): Add FLD_sz entr.
 319         * aarch64-tbl.h (_SIMD_INSN): New.
 320         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 321         fmulx scalar and vector by element isns.
 322
 323 2019-02-07  Nick Clifton  <nickc@redhat.com>
 324
 325         * po/sv.po: Updated Swedish translation.
 326
 327 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 328
 329         * s390-mkopc.c (main): Accept arch13 as cpu string.
 330         * s390-opc.c: Add new instruction formats and instruction opcode
 331         masks.
 332         * s390-opc.txt: Add new arch13 instructions.
 333
 334 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 335
 336         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 337         (aarch64_opcode): Change encoding for stg, stzg
 338         st2g and st2zg.
 339         * aarch64-asm-2.c: Regenerated.
 340         * aarch64-dis-2.c: Regenerated.
 341         * aarch64-opc-2.c: Regenerated.
 342
 343 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 344
 345         * aarch64-asm-2.c: Regenerated.
 346         * aarch64-dis-2.c: Likewise.
 347         * aarch64-opc-2.c: Likewise.
 348         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 349
 350 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 351             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 352
 353         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 354         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 355         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 356         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 357         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 358         case for ldstgv_indexed.
 359         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 360         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 361         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 362         * aarch64-asm-2.c: Regenerated.
 363         * aarch64-dis-2.c: Regenerated.
 364         * aarch64-opc-2.c: Regenerated.
 365
 366 2019-01-23  Nick Clifton  <nickc@redhat.com>
 367
 368         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 369
 370 2019-01-21  Nick Clifton  <nickc@redhat.com>
 371
 372         * po/de.po: Updated German translation.
 373         * po/uk.po: Updated Ukranian translation.
 374
 375 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 376         * mips-dis.c (mips_arch_choices): Fix typo in
 377         gs464, gs464e and gs264e descriptors.
 378
 379 2019-01-19  Nick Clifton  <nickc@redhat.com>
 380
 381         * configure: Regenerate.
 382         * po/opcodes.pot: Regenerate.
 383
 384 2018-06-24  Nick Clifton  <nickc@redhat.com>
 385
 386         2.32 branch created.
 387
 388 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 389
 390         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 391         if it is null.
 392         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 393         zero.
 394
 395 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 396
 397         * configure: Regenerate.
 398
 399 2019-01-07  Alan Modra  <amodra@gmail.com>
 400
 401         * configure: Regenerate.
 402         * po/POTFILES.in: Regenerate.
 403
 404 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 405
 406         * s12z-opc.c: New file.
 407         * s12z-opc.h: New file.
 408         * s12z-dis.c: Removed all code not directly related to display
 409         of instructions.  Used the interface provided by the new files
 410         instead.
 411         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 412         * Makefile.in: Regenerate.
 413         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 414         * configure: Regenerate.
 415
 416 2019-01-01  Alan Modra  <amodra@gmail.com>
 417
 418         Update year range in copyright notice of all files.
 419
 420 For older changes see ChangeLog-2018
 421 \f
 422 Copyright (C) 2019 Free Software Foundation, Inc.
 423
 424 Copying and distribution of this file, with or without modification,
 425 are permitted in any medium without royalty provided the copyright
 426 notice and this notice are preserved.
 427
 428 Local Variables:
 429 mode: change-log
 430 left-margin: 8
 431 fill-column: 74
 432 version-control: never
 433 End: