opcodes/ChangeLog

   1 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
   4         entries to the MSA ASE instruction block.
   5
   6 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
   7             Maciej W. Rozycki  <macro@imgtec.com>
   8
   9         * micromips-opc.c (XPA, XPAVZ): New macros.
  10         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
  11         "mthgc0".
  12
  13 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
  14             Maciej W. Rozycki  <macro@imgtec.com>
  15
  16         * micromips-opc.c (I36): New macro.
  17         (micromips_opcodes): Add "eretnc".
  18
  19 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
  20             Andrew Bennett  <andrew.bennett@imgtec.com>
  21
  22         * mips-dis.c (mips_calculate_combination_ases): Handle the
  23         ASE_XPA_VIRT flag.
  24         (parse_mips_ase_option): New function.
  25         (parse_mips_dis_option): Factor out ASE option handling to the
  26         new function.  Call `mips_calculate_combination_ases'.
  27         * mips-opc.c (XPAVZ): New macro.
  28         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
  29         "mfhgc0", "mthc0" and "mthgc0".
  30
  31 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
  32
  33         * mips-dis.c (mips_calculate_combination_ases): New function.
  34         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
  35         calculation to the new function.
  36         (set_default_mips_dis_options): Call the new function.
  37
  38 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  39
  40         * arc-dis.c (parse_disassembler_options): Use
  41         FOR_EACH_DISASSEMBLER_OPTION.
  42
  43 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  44
  45         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
  46         disassembler option strings.
  47         (parse_cpu_option): Likewise.
  48
  49 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
  50
  51         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
  52         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
  53         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
  54         (aarch64_feature_dotprod, DOT_INSN): New.
  55         (udot, sdot): New.
  56         * aarch64-dis-2.c: Regenerated.
  57
  58 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
  59
  60         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
  61
  62 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
  63             Matthew Fortune  <matthew.fortune@imgtec.com>
  64             Andrew Bennett  <andrew.bennett@imgtec.com>
  65
  66         * mips-formats.h (INT_BIAS): New macro.
  67         (INT_ADJ): Redefine in INT_BIAS terms.
  68         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
  69         (mips_print_save_restore): New function.
  70         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
  71         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
  72         call.
  73         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
  74         (print_mips16_insn_arg): Call `mips_print_save_restore' for
  75         OP_SAVE_RESTORE_LIST handling, factored out from here.
  76         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
  77         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
  78         (mips_builtin_opcodes): Add "restore" and "save" entries.
  79         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
  80         (IAMR2): New macro.
  81         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
  82
  83 2017-06-23  Andrew Waterman  <andrew@sifive.com>
  84
  85         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
  86         alias; do not mark SLTI instruction as an alias.
  87
  88 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  89
  90         * i386-dis.c (RM_0FAE_REG_5): Removed.
  91         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  92         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
  93         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
  94         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
  95         PREFIX_MOD_3_0F01_REG_5_RM_0.
  96         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
  97         PREFIX_MOD_3_0FAE_REG_5.
  98         (mod_table): Update MOD_0FAE_REG_5.
  99         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 100         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 101         * i386-tbl.h: Regenerated.
 102
 103 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 104
 105         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 106         * i386-opc.tbl: Likewise.
 107         * i386-tbl.h: Regenerated.
 108
 109 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 110
 111         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 112         and "jmp{&|}".
 113         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 114         prefix.
 115
 116 2017-06-19  Nick Clifton  <nickc@redhat.com>
 117
 118         PR binutils/21614
 119         * score-dis.c (score_opcodes): Add sentinel.
 120
 121 2017-06-16  Alan Modra  <amodra@gmail.com>
 122
 123         * rx-decode.c: Regenerate.
 124
 125 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 126
 127         PR binutils/21594
 128         * i386-dis.c (OP_E_register): Check valid bnd register.
 129         (OP_G): Likewise.
 130
 131 2017-06-15  Nick Clifton  <nickc@redhat.com>
 132
 133         PR binutils/21595
 134         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 135         range value.
 136
 137 2017-06-15  Nick Clifton  <nickc@redhat.com>
 138
 139         PR binutils/21588
 140         * rl78-decode.opc (OP_BUF_LEN): Define.
 141         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 142         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 143         array.
 144         * rl78-decode.c: Regenerate.
 145
 146 2017-06-15  Nick Clifton  <nickc@redhat.com>
 147
 148         PR binutils/21586
 149         * bfin-dis.c (gregs): Clip index to prevent overflow.
 150         (regs): Likewise.
 151         (regs_lo): Likewise.
 152         (regs_hi): Likewise.
 153
 154 2017-06-14  Nick Clifton  <nickc@redhat.com>
 155
 156         PR binutils/21576
 157         * score7-dis.c (score_opcodes): Add sentinel.
 158
 159 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 160
 161         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 162         * arm-dis.c: Likewise.
 163         * ia64-dis.c: Likewise.
 164         * mips-dis.c: Likewise.
 165         * spu-dis.c: Likewise.
 166         * disassemble.h (print_insn_aarch64): New declaration, moved from
 167         include/dis-asm.h.
 168         (print_insn_big_arm, print_insn_big_mips): Likewise.
 169         (print_insn_i386, print_insn_ia64): Likewise.
 170         (print_insn_little_arm, print_insn_little_mips): Likewise.
 171
 172 2017-06-14  Nick Clifton  <nickc@redhat.com>
 173
 174         PR binutils/21587
 175         * rx-decode.opc: Include libiberty.h
 176         (GET_SCALE): New macro - validates access to SCALE array.
 177         (GET_PSCALE): New macro - validates access to PSCALE array.
 178         (DIs, SIs, S2Is, rx_disp): Use new macros.
 179         * rx-decode.c: Regenerate.
 180
 181 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 182
 183         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 184
 185 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 186
 187         * arc-dis.c (enforced_isa_mask): Declare.
 188         (cpu_types): Likewise.
 189         (parse_cpu_option): New function.
 190         (parse_disassembler_options): Use it.
 191         (print_insn_arc): Use enforced_isa_mask.
 192         (print_arc_disassembler_options): Document new options.
 193
 194 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 195
 196         * alpha-dis.c: Include disassemble.h, don't include
 197         dis-asm.h.
 198         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 199         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 200         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 201         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 202         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 203         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 204         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 205         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 206         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 207         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 208         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 209         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 210         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 211         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 212         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 213         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 214         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 215         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 216         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 217         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 218         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 219         * z80-dis.c, z8k-dis.c: Likewise.
 220         * disassemble.h: New file.
 221
 222 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 223
 224         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 225         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 226
 227 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 228
 229         * disassemble.c (disassembler): Add arguments a, big and mach.
 230         Use them.
 231
 232 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 233
 234         * i386-dis.c (NOTRACK_Fixup): New.
 235         (NOTRACK): Likewise.
 236         (NOTRACK_PREFIX): Likewise.
 237         (last_active_prefix): Likewise.
 238         (reg_table): Use NOTRACK on indirect call and jmp.
 239         (ckprefix): Set last_active_prefix.
 240         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 241         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 242         * i386-opc.h (NoTrackPrefixOk): New.
 243         (i386_opcode_modifier): Add notrackprefixok.
 244         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 245         Add notrack.
 246         * i386-tbl.h: Regenerated.
 247
 248 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 249
 250         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 251         (X_IMM2): Define.
 252         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 253         bfd_mach_sparc_v9m8.
 254         (print_insn_sparc): Handle new operand types.
 255         * sparc-opc.c (MASK_M8): Define.
 256         (v6): Add MASK_M8.
 257         (v6notlet): Likewise.
 258         (v7): Likewise.
 259         (v8): Likewise.
 260         (v9): Likewise.
 261         (v9a): Likewise.
 262         (v9b): Likewise.
 263         (v9c): Likewise.
 264         (v9d): Likewise.
 265         (v9e): Likewise.
 266         (v9v): Likewise.
 267         (v9m): Likewise.
 268         (v9andleon): Likewise.
 269         (m8): Define.
 270         (HWS_VM8): Define.
 271         (HWS2_VM8): Likewise.
 272         (sparc_opcode_archs): Add entry for "m8".
 273         (sparc_opcodes): Add OSA2017 and M8 instructions
 274         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 275         fpx{ll,ra,rl}64x,
 276         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 277         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 278         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 279         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 280         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 281         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 282         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 283         ASI_CORE_SELECT_COMMIT_NHT.
 284
 285 2017-05-18  Alan Modra  <amodra@gmail.com>
 286
 287         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 288         * aarch64-dis.c: Likewise.
 289         * aarch64-gen.c: Likewise.
 290         * aarch64-opc.c: Likewise.
 291
 292 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 293             Matthew Fortune  <matthew.fortune@imgtec.com>
 294
 295         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 296         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 297         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 298         (print_insn_arg) <OP_REG28>: Add handler.
 299         (validate_insn_args) <OP_REG28>: Handle.
 300         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 301         32-bit encoding and 9-bit immediates.
 302         (print_insn_mips16): Handle MIPS16 instructions that require
 303         32-bit encoding and MFC0/MTC0 operand decoding.
 304         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 305         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 306         (RD_C0, WR_C0, E2, E2MT): New macros.
 307         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 308         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 309         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 310         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 311         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 312         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 313         instructions, "swl", "swr", "sync" and its "sync_acquire",
 314         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 315         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 316         regular/extended entries for original MIPS16 ISA revision
 317         instructions whose extended forms are subdecoded in the MIPS16e2
 318         ISA revision: "li", "sll" and "srl".
 319
 320 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 321
 322         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 323         reference in CP0 move operand decoding.
 324
 325 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 326
 327         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 328         type to hexadecimal.
 329         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 330
 331 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 332
 333         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 334         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 335         "sync_rmb" and "sync_wmb" as aliases.
 336         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 337         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 338
 339 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 340
 341         * arc-dis.c (parse_option): Update quarkse_em option..
 342         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 343         QUARKSE1.
 344         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 345
 346 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 347
 348         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 349
 350 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 351
 352         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 353         register.
 354
 355 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 356
 357         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 358         and branches and not synthetic data instructions.
 359
 360 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 361
 362         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 363
 364 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 365
 366         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 367         * arc-opc.c (insert_r13el): New function.
 368         (R13_EL): Define.
 369         * arc-tbl.h: Add new enter/leave variants.
 370
 371 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 372
 373         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 374
 375 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 376
 377         * mips-dis.c (print_mips_disassembler_options): Add
 378         `no-aliases'.
 379
 380 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 381
 382         * mips16-opc.c (AL): New macro.
 383         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 384         of "ld" and "lw" as aliases.
 385
 386 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 387
 388         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 389         arguments.
 390
 391 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 392             Alan Modra  <amodra@gmail.com>
 393
 394         * ppc-opc.c (ELEV): Define.
 395         (vle_opcodes): Add se_rfgi and e_sc.
 396         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 397         for E200Z4.
 398
 399 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 400
 401         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 402
 403 2017-04-21  Nick Clifton  <nickc@redhat.com>
 404
 405         PR binutils/21380
 406         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 407         LD3R and LD4R.
 408
 409 2017-04-13  Alan Modra  <amodra@gmail.com>
 410
 411         * epiphany-desc.c: Regenerate.
 412         * fr30-desc.c: Regenerate.
 413         * frv-desc.c: Regenerate.
 414         * ip2k-desc.c: Regenerate.
 415         * iq2000-desc.c: Regenerate.
 416         * lm32-desc.c: Regenerate.
 417         * m32c-desc.c: Regenerate.
 418         * m32r-desc.c: Regenerate.
 419         * mep-desc.c: Regenerate.
 420         * mt-desc.c: Regenerate.
 421         * or1k-desc.c: Regenerate.
 422         * xc16x-desc.c: Regenerate.
 423         * xstormy16-desc.c: Regenerate.
 424
 425 2017-04-11  Alan Modra  <amodra@gmail.com>
 426
 427         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 428         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 429         PPC_OPCODE_TMR for e6500.
 430         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 431         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 432         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 433         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 434         (PPCHTM): Define as PPC_OPCODE_POWER8.
 435         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 436
 437 2017-04-10  Alan Modra  <amodra@gmail.com>
 438
 439         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 440         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 441         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 442         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 443
 444 2017-04-09  Pip Cet  <pipcet@gmail.com>
 445
 446         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 447         appropriate floating-point precision directly.
 448
 449 2017-04-07  Alan Modra  <amodra@gmail.com>
 450
 451         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 452         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 453         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 454         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 455         vector instructions with E6500 not PPCVEC2.
 456
 457 2017-04-06  Pip Cet  <pipcet@gmail.com>
 458
 459         * Makefile.am: Add wasm32-dis.c.
 460         * configure.ac: Add wasm32-dis.c to wasm32 target.
 461         * disassemble.c: Add wasm32 disassembler code.
 462         * wasm32-dis.c: New file.
 463         * Makefile.in: Regenerate.
 464         * configure: Regenerate.
 465         * po/POTFILES.in: Regenerate.
 466         * po/opcodes.pot: Regenerate.
 467
 468 2017-04-05  Pedro Alves  <palves@redhat.com>
 469
 470         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 471         * arm-dis.c (parse_arm_disassembler_options): Constify.
 472         * ppc-dis.c (powerpc_init_dialect): Constify local.
 473         * vax-dis.c (parse_disassembler_options): Constify.
 474
 475 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 476
 477         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 478         RISCV_GP_SYMBOL.
 479
 480 2017-03-30  Pip Cet  <pipcet@gmail.com>
 481
 482         * configure.ac: Add (empty) bfd_wasm32_arch target.
 483         * configure: Regenerate
 484         * po/opcodes.pot: Regenerate.
 485
 486 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 487
 488         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 489         OSA2015.
 490         * opcodes/sparc-opc.c (asi_table): New ASIs.
 491
 492 2017-03-29  Alan Modra  <amodra@gmail.com>
 493
 494         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 495         "raw" option.
 496         (lookup_powerpc): Don't special case -1 dialect.  Handle
 497         PPC_OPCODE_RAW.
 498         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 499         lookup_powerpc call, pass it on second.
 500
 501 2017-03-27  Alan Modra  <amodra@gmail.com>
 502
 503         PR 21303
 504         * ppc-dis.c (struct ppc_mopt): Comment.
 505         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 506
 507 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 508
 509         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 510         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 511         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 512         (insert_nps_misc_imm_offset): New function.
 513         (extract_nps_misc imm_offset): New function.
 514         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 515         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 516
 517 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 518
 519         * s390-mkopc.c (main): Remove vx2 check.
 520         * s390-opc.txt: Remove vx2 instruction flags.
 521
 522 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 523
 524         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 525         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 526         (insert_nps_imm_offset): New function.
 527         (extract_nps_imm_offset): New function.
 528         (insert_nps_imm_entry): New function.
 529         (extract_nps_imm_entry): New function.
 530
 531 2017-03-17  Alan Modra  <amodra@gmail.com>
 532
 533         PR 21248
 534         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 535         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 536         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 537
 538 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 539
 540         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 541         <c.andi>: Likewise.
 542         <c.addiw> Likewise.
 543
 544 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 545
 546         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 547
 548 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 549
 550         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 551         <srl> Likewise.
 552         <srai> Likewise.
 553         <sra> Likewise.
 554
 555 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 556
 557         * i386-gen.c (opcode_modifiers): Replace S with Load.
 558         * i386-opc.h (S): Removed.
 559         (Load): New.
 560         (i386_opcode_modifier): Replace s with load.
 561         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 562         and {evex}.  Replace S with Load.
 563         * i386-tbl.h: Regenerated.
 564
 565 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 566
 567         * i386-opc.tbl: Use CpuCET on rdsspq.
 568         * i386-tbl.h: Regenerated.
 569
 570 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 571
 572         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 573         <vsx>: Do not use PPC_OPCODE_VSX3;
 574
 575 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 576
 577         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 578
 579 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 580
 581         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 582         (MOD_0F1E_PREFIX_1): Likewise.
 583         (MOD_0F38F5_PREFIX_2): Likewise.
 584         (MOD_0F38F6_PREFIX_0): Likewise.
 585         (RM_0F1E_MOD_3_REG_7): Likewise.
 586         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 587         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 588         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 589         (PREFIX_0F1E): Likewise.
 590         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 591         (PREFIX_0F38F5): Likewise.
 592         (dis386_twobyte): Use PREFIX_0F1E.
 593         (reg_table): Add REG_0F1E_MOD_3.
 594         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 595         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 596         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 597         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 598         (three_byte_table): Use PREFIX_0F38F5.
 599         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 600         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 601         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 602         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 603         PREFIX_MOD_3_0F01_REG_5_RM_2.
 604         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 605         (cpu_flags): Add CpuCET.
 606         * i386-opc.h (CpuCET): New enum.
 607         (CpuUnused): Commented out.
 608         (i386_cpu_flags): Add cpucet.
 609         * i386-opc.tbl: Add Intel CET instructions.
 610         * i386-init.h: Regenerated.
 611         * i386-tbl.h: Likewise.
 612
 613 2017-03-06  Alan Modra  <amodra@gmail.com>
 614
 615         PR 21124
 616         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 617         (extract_raq, extract_ras, extract_rbx): New functions.
 618         (powerpc_operands): Use opposite corresponding insert function.
 619         (Q_MASK): Define.
 620         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 621         register restriction.
 622
 623 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 624
 625         * disassemble.c Include "safe-ctype.h".
 626         (disassemble_init_for_target): Handle s390 init.
 627         (remove_whitespace_and_extra_commas): New function.
 628         (disassembler_options_cmp): Likewise.
 629         * arm-dis.c: Include "libiberty.h".
 630         (NUM_ELEM): Delete.
 631         (regnames): Use long disassembler style names.
 632         Add force-thumb and no-force-thumb options.
 633         (NUM_ARM_REGNAMES): Rename from this...
 634         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 635         (get_arm_regname_num_options): Delete.
 636         (set_arm_regname_option): Likewise.
 637         (get_arm_regnames): Likewise.
 638         (parse_disassembler_options): Likewise.
 639         (parse_arm_disassembler_option): Rename from this...
 640         (parse_arm_disassembler_options): ...to this.  Make static.
 641         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 642         (print_insn): Use parse_arm_disassembler_options.
 643         (disassembler_options_arm): New function.
 644         (print_arm_disassembler_options): Handle updated regnames.
 645         * ppc-dis.c: Include "libiberty.h".
 646         (ppc_opts): Add "32" and "64" entries.
 647         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 648         (powerpc_init_dialect): Add break to switch statement.
 649         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 650         (disassembler_options_powerpc): New function.
 651         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 652         Remove printing of "32" and "64".
 653         * s390-dis.c: Include "libiberty.h".
 654         (init_flag): Remove unneeded variable.
 655         (struct s390_options_t): New structure type.
 656         (options): New structure.
 657         (init_disasm): Rename from this...
 658         (disassemble_init_s390): ...to this.  Add initializations for
 659         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 660         (print_insn_s390): Delete call to init_disasm.
 661         (disassembler_options_s390): New function.
 662         (print_s390_disassembler_options): Print using information from
 663         struct 'options'.
 664         * po/opcodes.pot: Regenerate.
 665
 666 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 667
 668         * i386-dis.c (PCMPESTR_Fixup): New.
 669         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 670         (prefix_table): Use PCMPESTR_Fixup.
 671         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 672         PCMPESTR_Fixup.
 673         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 674         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 675         Split 64-bit and non-64-bit variants.
 676         * opcodes/i386-tbl.h: Re-generate.
 677
 678 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 679
 680         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 681         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 682         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 683         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 684         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 685         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 686         (OP_SVE_V_HSD): New macros.
 687         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 688         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 689         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 690         (aarch64_opcode_table): Add new SVE instructions.
 691         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 692         for rotation operands.  Add new SVE operands.
 693         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 694         (ins_sve_quad_index): Likewise.
 695         (ins_imm_rotate): Split into...
 696         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 697         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 698         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 699         functions.
 700         (aarch64_ins_sve_addr_ri_s4): New function.
 701         (aarch64_ins_sve_quad_index): Likewise.
 702         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 703         * aarch64-asm-2.c: Regenerate.
 704         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 705         (ext_sve_quad_index): Likewise.
 706         (ext_imm_rotate): Split into...
 707         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 708         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 709         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 710         functions.
 711         (aarch64_ext_sve_addr_ri_s4): New function.
 712         (aarch64_ext_sve_quad_index): Likewise.
 713         (aarch64_ext_sve_index): Allow quad indices.
 714         (do_misc_decoding): Likewise.
 715         * aarch64-dis-2.c: Regenerate.
 716         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 717         aarch64_field_kinds.
 718         (OPD_F_OD_MASK): Widen by one bit.
 719         (OPD_F_NO_ZR): Bump accordingly.
 720         (get_operand_field_width): New function.
 721         * aarch64-opc.c (fields): Add new SVE fields.
 722         (operand_general_constraint_met_p): Handle new SVE operands.
 723         (aarch64_print_operand): Likewise.
 724         * aarch64-opc-2.c: Regenerate.
 725
 726 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 727
 728         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 729         (aarch64_feature_compnum): ...this.
 730         (SIMD_V8_3): Replace with...
 731         (COMPNUM): ...this.
 732         (CNUM_INSN): New macro.
 733         (aarch64_opcode_table): Use it for the complex number instructions.
 734
 735 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 736
 737         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 738
 739 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 740
 741         Add support for associating SPARC ASIs with an architecture level.
 742         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 743         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 744         decoding of SPARC ASIs.
 745
 746 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 749         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 750
 751 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 752
 753         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 754         1 (instead of to itself). Correct typo.
 755
 756 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 757
 758         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 759         pseudoinstructions.
 760
 761 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 762
 763         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 764         (aarch64_sys_reg_supported_p): Handle them.
 765
 766 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 767
 768         * arc-opc.c (UIMM6_20R): Define.
 769         (SIMM12_20): Use above.
 770         (SIMM12_20R): Define.
 771         (SIMM3_5_S): Use above.
 772         (UIMM7_A32_11R_S): Define.
 773         (UIMM7_9_S): Use above.
 774         (UIMM3_13R_S): Define.
 775         (SIMM11_A32_7_S): Use above.
 776         (SIMM9_8R): Define.
 777         (UIMM10_A32_8_S): Use above.
 778         (UIMM8_8R_S): Define.
 779         (W6): Use above.
 780         (arc_relax_opcodes): Use all above defines.
 781
 782 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 783
 784         * arc-regs.h: Distinguish some of the registers different on
 785         ARC700 and HS38 cpus.
 786
 787 2017-02-14  Alan Modra  <amodra@gmail.com>
 788
 789         PR 21118
 790         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 791         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 792
 793 2017-02-11  Stafford Horne  <shorne@gmail.com>
 794             Alan Modra  <amodra@gmail.com>
 795
 796         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 797         Use insn_bytes_value and insn_int_value directly instead.  Don't
 798         free allocated memory until function exit.
 799
 800 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 801
 802         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 803
 804 2017-02-03  Nick Clifton  <nickc@redhat.com>
 805
 806         PR 21096
 807         * aarch64-opc.c (print_register_list): Ensure that the register
 808         list index will fir into the tb buffer.
 809         (print_register_offset_address): Likewise.
 810         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 811
 812 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 813
 814         PR 21056
 815         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 816         instructions when the previous fetch packet ends with a 32-bit
 817         instruction.
 818
 819 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 820
 821         * pru-opc.c: Remove vague reference to a future GDB port.
 822
 823 2017-01-20  Nick Clifton  <nickc@redhat.com>
 824
 825         * po/ga.po: Updated Irish translation.
 826
 827 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 828
 829         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 830
 831 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 832
 833         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 834         if FETCH_DATA returns 0.
 835         (m68k_scan_mask): Likewise.
 836         (print_insn_m68k): Update code to handle -1 return value.
 837
 838 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 839
 840         * m68k-dis.c (enum print_insn_arg_error): New.
 841         (NEXTBYTE): Replace -3 with
 842         PRINT_INSN_ARG_MEMORY_ERROR.
 843         (NEXTULONG): Likewise.
 844         (NEXTSINGLE): Likewise.
 845         (NEXTDOUBLE): Likewise.
 846         (NEXTDOUBLE): Likewise.
 847         (NEXTPACKED): Likewise.
 848         (FETCH_ARG): Likewise.
 849         (FETCH_DATA): Update comments.
 850         (print_insn_arg): Update comments. Replace magic numbers with
 851         enum.
 852         (match_insn_m68k): Likewise.
 853
 854 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 855
 856         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 857         * i386-dis-evex.h (evex_table): Updated.
 858         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 859         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 860         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 861         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 862         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 863         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 864         * i386-init.h: Regenerate.
 865         * i386-tbl.h: Ditto.
 866
 867 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 868
 869         * msp430-dis.c (msp430_singleoperand): Return -1 if
 870         msp430dis_opcode_signed returns false.
 871         (msp430_doubleoperand): Likewise.
 872         (msp430_branchinstr): Return -1 if
 873         msp430dis_opcode_unsigned returns false.
 874         (msp430x_calla_instr): Likewise.
 875         (print_insn_msp430): Likewise.
 876
 877 2017-01-05  Nick Clifton  <nickc@redhat.com>
 878
 879         PR 20946
 880         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 881         could not be matched.
 882         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 883         NULL.
 884
 885 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 886
 887         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 888         (aarch64_opcode_table): Use RCPC_INSN.
 889
 890 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 891
 892         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 893         extension.
 894         * riscv-opcodes/all-opcodes: Likewise.
 895
 896 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 897
 898         * riscv-dis.c (print_insn_args): Add fall through comment.
 899
 900 2017-01-03  Nick Clifton  <nickc@redhat.com>
 901
 902         * po/sr.po: New Serbian translation.
 903         * configure.ac (ALL_LINGUAS): Add sr.
 904         * configure: Regenerate.
 905
 906 2017-01-02  Alan Modra  <amodra@gmail.com>
 907
 908         * epiphany-desc.h: Regenerate.
 909         * epiphany-opc.h: Regenerate.
 910         * fr30-desc.h: Regenerate.
 911         * fr30-opc.h: Regenerate.
 912         * frv-desc.h: Regenerate.
 913         * frv-opc.h: Regenerate.
 914         * ip2k-desc.h: Regenerate.
 915         * ip2k-opc.h: Regenerate.
 916         * iq2000-desc.h: Regenerate.
 917         * iq2000-opc.h: Regenerate.
 918         * lm32-desc.h: Regenerate.
 919         * lm32-opc.h: Regenerate.
 920         * m32c-desc.h: Regenerate.
 921         * m32c-opc.h: Regenerate.
 922         * m32r-desc.h: Regenerate.
 923         * m32r-opc.h: Regenerate.
 924         * mep-desc.h: Regenerate.
 925         * mep-opc.h: Regenerate.
 926         * mt-desc.h: Regenerate.
 927         * mt-opc.h: Regenerate.
 928         * or1k-desc.h: Regenerate.
 929         * or1k-opc.h: Regenerate.
 930         * xc16x-desc.h: Regenerate.
 931         * xc16x-opc.h: Regenerate.
 932         * xstormy16-desc.h: Regenerate.
 933         * xstormy16-opc.h: Regenerate.
 934
 935 2017-01-02  Alan Modra  <amodra@gmail.com>
 936
 937         Update year range in copyright notice of all files.
 938
 939 For older changes see ChangeLog-2016
 940 \f
 941 Copyright (C) 2017 Free Software Foundation, Inc.
 942
 943 Copying and distribution of this file, with or without modification,
 944 are permitted in any medium without royalty provided the copyright
 945 notice and this notice are preserved.
 946
 947 Local Variables:
 948 mode: change-log
 949 left-margin: 8
 950 fill-column: 74
 951 version-control: never
 952 End: