opcodes/ChangeLog

   1 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
   2
   3         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
   4         <c.andi>: Likewise.
   5         <c.addiw> Likewise.
   6
   7 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
   8
   9         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
  10
  11 2017-03-13  Andrew Waterman  <andrew@sifive.com>
  12
  13         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
  14         <srl> Likewise.
  15         <srai> Likewise.
  16         <sra> Likewise.
  17
  18 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  19
  20         * i386-gen.c (opcode_modifiers): Replace S with Load.
  21         * i386-opc.h (S): Removed.
  22         (Load): New.
  23         (i386_opcode_modifier): Replace s with load.
  24         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
  25         and {evex}.  Replace S with Load.
  26         * i386-tbl.h: Regenerated.
  27
  28 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  29
  30         * i386-opc.tbl: Use CpuCET on rdsspq.
  31         * i386-tbl.h: Regenerated.
  32
  33 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
  34
  35         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
  36         <vsx>: Do not use PPC_OPCODE_VSX3;
  37
  38 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
  39
  40         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
  41
  42 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
  43
  44         * i386-dis.c (REG_0F1E_MOD_3): New enum.
  45         (MOD_0F1E_PREFIX_1): Likewise.
  46         (MOD_0F38F5_PREFIX_2): Likewise.
  47         (MOD_0F38F6_PREFIX_0): Likewise.
  48         (RM_0F1E_MOD_3_REG_7): Likewise.
  49         (PREFIX_MOD_0_0F01_REG_5): Likewise.
  50         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  51         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
  52         (PREFIX_0F1E): Likewise.
  53         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
  54         (PREFIX_0F38F5): Likewise.
  55         (dis386_twobyte): Use PREFIX_0F1E.
  56         (reg_table): Add REG_0F1E_MOD_3.
  57         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
  58         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
  59         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
  60         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
  61         (three_byte_table): Use PREFIX_0F38F5.
  62         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
  63         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
  64         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
  65         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
  66         PREFIX_MOD_3_0F01_REG_5_RM_2.
  67         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
  68         (cpu_flags): Add CpuCET.
  69         * i386-opc.h (CpuCET): New enum.
  70         (CpuUnused): Commented out.
  71         (i386_cpu_flags): Add cpucet.
  72         * i386-opc.tbl: Add Intel CET instructions.
  73         * i386-init.h: Regenerated.
  74         * i386-tbl.h: Likewise.
  75
  76 2017-03-06  Alan Modra  <amodra@gmail.com>
  77
  78         PR 21124
  79         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
  80         (extract_raq, extract_ras, extract_rbx): New functions.
  81         (powerpc_operands): Use opposite corresponding insert function.
  82         (Q_MASK): Define.
  83         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
  84         register restriction.
  85
  86 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
  87
  88         * disassemble.c Include "safe-ctype.h".
  89         (disassemble_init_for_target): Handle s390 init.
  90         (remove_whitespace_and_extra_commas): New function.
  91         (disassembler_options_cmp): Likewise.
  92         * arm-dis.c: Include "libiberty.h".
  93         (NUM_ELEM): Delete.
  94         (regnames): Use long disassembler style names.
  95         Add force-thumb and no-force-thumb options.
  96         (NUM_ARM_REGNAMES): Rename from this...
  97         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
  98         (get_arm_regname_num_options): Delete.
  99         (set_arm_regname_option): Likewise.
 100         (get_arm_regnames): Likewise.
 101         (parse_disassembler_options): Likewise.
 102         (parse_arm_disassembler_option): Rename from this...
 103         (parse_arm_disassembler_options): ...to this.  Make static.
 104         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 105         (print_insn): Use parse_arm_disassembler_options.
 106         (disassembler_options_arm): New function.
 107         (print_arm_disassembler_options): Handle updated regnames.
 108         * ppc-dis.c: Include "libiberty.h".
 109         (ppc_opts): Add "32" and "64" entries.
 110         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 111         (powerpc_init_dialect): Add break to switch statement.
 112         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 113         (disassembler_options_powerpc): New function.
 114         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 115         Remove printing of "32" and "64".
 116         * s390-dis.c: Include "libiberty.h".
 117         (init_flag): Remove unneeded variable.
 118         (struct s390_options_t): New structure type.
 119         (options): New structure.
 120         (init_disasm): Rename from this...
 121         (disassemble_init_s390): ...to this.  Add initializations for
 122         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 123         (print_insn_s390): Delete call to init_disasm.
 124         (disassembler_options_s390): New function.
 125         (print_s390_disassembler_options): Print using information from
 126         struct 'options'.
 127         * po/opcodes.pot: Regenerate.
 128
 129 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 130
 131         * i386-dis.c (PCMPESTR_Fixup): New.
 132         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 133         (prefix_table): Use PCMPESTR_Fixup.
 134         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 135         PCMPESTR_Fixup.
 136         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 137         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 138         Split 64-bit and non-64-bit variants.
 139         * opcodes/i386-tbl.h: Re-generate.
 140
 141 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 142
 143         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 144         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 145         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 146         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 147         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 148         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 149         (OP_SVE_V_HSD): New macros.
 150         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 151         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 152         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 153         (aarch64_opcode_table): Add new SVE instructions.
 154         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 155         for rotation operands.  Add new SVE operands.
 156         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 157         (ins_sve_quad_index): Likewise.
 158         (ins_imm_rotate): Split into...
 159         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 160         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 161         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 162         functions.
 163         (aarch64_ins_sve_addr_ri_s4): New function.
 164         (aarch64_ins_sve_quad_index): Likewise.
 165         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 166         * aarch64-asm-2.c: Regenerate.
 167         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 168         (ext_sve_quad_index): Likewise.
 169         (ext_imm_rotate): Split into...
 170         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 171         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 172         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 173         functions.
 174         (aarch64_ext_sve_addr_ri_s4): New function.
 175         (aarch64_ext_sve_quad_index): Likewise.
 176         (aarch64_ext_sve_index): Allow quad indices.
 177         (do_misc_decoding): Likewise.
 178         * aarch64-dis-2.c: Regenerate.
 179         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 180         aarch64_field_kinds.
 181         (OPD_F_OD_MASK): Widen by one bit.
 182         (OPD_F_NO_ZR): Bump accordingly.
 183         (get_operand_field_width): New function.
 184         * aarch64-opc.c (fields): Add new SVE fields.
 185         (operand_general_constraint_met_p): Handle new SVE operands.
 186         (aarch64_print_operand): Likewise.
 187         * aarch64-opc-2.c: Regenerate.
 188
 189 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 190
 191         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 192         (aarch64_feature_compnum): ...this.
 193         (SIMD_V8_3): Replace with...
 194         (COMPNUM): ...this.
 195         (CNUM_INSN): New macro.
 196         (aarch64_opcode_table): Use it for the complex number instructions.
 197
 198 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 199
 200         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 201
 202 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 203
 204         Add support for associating SPARC ASIs with an architecture level.
 205         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 206         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 207         decoding of SPARC ASIs.
 208
 209 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 210
 211         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 212         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 213
 214 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 215
 216         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 217         1 (instead of to itself). Correct typo.
 218
 219 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 220
 221         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 222         pseudoinstructions.
 223
 224 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 225
 226         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 227         (aarch64_sys_reg_supported_p): Handle them.
 228
 229 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 230
 231         * arc-opc.c (UIMM6_20R): Define.
 232         (SIMM12_20): Use above.
 233         (SIMM12_20R): Define.
 234         (SIMM3_5_S): Use above.
 235         (UIMM7_A32_11R_S): Define.
 236         (UIMM7_9_S): Use above.
 237         (UIMM3_13R_S): Define.
 238         (SIMM11_A32_7_S): Use above.
 239         (SIMM9_8R): Define.
 240         (UIMM10_A32_8_S): Use above.
 241         (UIMM8_8R_S): Define.
 242         (W6): Use above.
 243         (arc_relax_opcodes): Use all above defines.
 244
 245 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 246
 247         * arc-regs.h: Distinguish some of the registers different on
 248         ARC700 and HS38 cpus.
 249
 250 2017-02-14  Alan Modra  <amodra@gmail.com>
 251
 252         PR 21118
 253         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 254         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 255
 256 2017-02-11  Stafford Horne  <shorne@gmail.com>
 257             Alan Modra  <amodra@gmail.com>
 258
 259         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 260         Use insn_bytes_value and insn_int_value directly instead.  Don't
 261         free allocated memory until function exit.
 262
 263 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 264
 265         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 266
 267 2017-02-03  Nick Clifton  <nickc@redhat.com>
 268
 269         PR 21096
 270         * aarch64-opc.c (print_register_list): Ensure that the register
 271         list index will fir into the tb buffer.
 272         (print_register_offset_address): Likewise.
 273         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 274
 275 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 276
 277         PR 21056
 278         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 279         instructions when the previous fetch packet ends with a 32-bit
 280         instruction.
 281
 282 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 283
 284         * pru-opc.c: Remove vague reference to a future GDB port.
 285
 286 2017-01-20  Nick Clifton  <nickc@redhat.com>
 287
 288         * po/ga.po: Updated Irish translation.
 289
 290 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 291
 292         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 293
 294 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 295
 296         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 297         if FETCH_DATA returns 0.
 298         (m68k_scan_mask): Likewise.
 299         (print_insn_m68k): Update code to handle -1 return value.
 300
 301 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 302
 303         * m68k-dis.c (enum print_insn_arg_error): New.
 304         (NEXTBYTE): Replace -3 with
 305         PRINT_INSN_ARG_MEMORY_ERROR.
 306         (NEXTULONG): Likewise.
 307         (NEXTSINGLE): Likewise.
 308         (NEXTDOUBLE): Likewise.
 309         (NEXTDOUBLE): Likewise.
 310         (NEXTPACKED): Likewise.
 311         (FETCH_ARG): Likewise.
 312         (FETCH_DATA): Update comments.
 313         (print_insn_arg): Update comments. Replace magic numbers with
 314         enum.
 315         (match_insn_m68k): Likewise.
 316
 317 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 318
 319         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 320         * i386-dis-evex.h (evex_table): Updated.
 321         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 322         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 323         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 324         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 325         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 326         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 327         * i386-init.h: Regenerate.
 328         * i386-tbl.h: Ditto.
 329
 330 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 331
 332         * msp430-dis.c (msp430_singleoperand): Return -1 if
 333         msp430dis_opcode_signed returns false.
 334         (msp430_doubleoperand): Likewise.
 335         (msp430_branchinstr): Return -1 if
 336         msp430dis_opcode_unsigned returns false.
 337         (msp430x_calla_instr): Likewise.
 338         (print_insn_msp430): Likewise.
 339
 340 2017-01-05  Nick Clifton  <nickc@redhat.com>
 341
 342         PR 20946
 343         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 344         could not be matched.
 345         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 346         NULL.
 347
 348 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 349
 350         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 351         (aarch64_opcode_table): Use RCPC_INSN.
 352
 353 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 354
 355         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 356         extension.
 357         * riscv-opcodes/all-opcodes: Likewise.
 358
 359 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 360
 361         * riscv-dis.c (print_insn_args): Add fall through comment.
 362
 363 2017-01-03  Nick Clifton  <nickc@redhat.com>
 364
 365         * po/sr.po: New Serbian translation.
 366         * configure.ac (ALL_LINGUAS): Add sr.
 367         * configure: Regenerate.
 368
 369 2017-01-02  Alan Modra  <amodra@gmail.com>
 370
 371         * epiphany-desc.h: Regenerate.
 372         * epiphany-opc.h: Regenerate.
 373         * fr30-desc.h: Regenerate.
 374         * fr30-opc.h: Regenerate.
 375         * frv-desc.h: Regenerate.
 376         * frv-opc.h: Regenerate.
 377         * ip2k-desc.h: Regenerate.
 378         * ip2k-opc.h: Regenerate.
 379         * iq2000-desc.h: Regenerate.
 380         * iq2000-opc.h: Regenerate.
 381         * lm32-desc.h: Regenerate.
 382         * lm32-opc.h: Regenerate.
 383         * m32c-desc.h: Regenerate.
 384         * m32c-opc.h: Regenerate.
 385         * m32r-desc.h: Regenerate.
 386         * m32r-opc.h: Regenerate.
 387         * mep-desc.h: Regenerate.
 388         * mep-opc.h: Regenerate.
 389         * mt-desc.h: Regenerate.
 390         * mt-opc.h: Regenerate.
 391         * or1k-desc.h: Regenerate.
 392         * or1k-opc.h: Regenerate.
 393         * xc16x-desc.h: Regenerate.
 394         * xc16x-opc.h: Regenerate.
 395         * xstormy16-desc.h: Regenerate.
 396         * xstormy16-opc.h: Regenerate.
 397
 398 2017-01-02  Alan Modra  <amodra@gmail.com>
 399
 400         Update year range in copyright notice of all files.
 401
 402 For older changes see ChangeLog-2016
 403 \f
 404 Copyright (C) 2017 Free Software Foundation, Inc.
 405
 406 Copying and distribution of this file, with or without modification,
 407 are permitted in any medium without royalty provided the copyright
 408 notice and this notice are preserved.
 409
 410 Local Variables:
 411 mode: change-log
 412 left-margin: 8
 413 fill-column: 74
 414 version-control: never
 415 End: