opcodes/ChangeLog

   1 2011-06-14  Alan Modra  <amodra@gmail.com>
   2
   3         * Makefile.in: Regenerate.
   4
   5 2011-06-13  Walter Lee  <walt@tilera.com>
   6
   7         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
   8         tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
   9         * Makefile.in: Regenerate.
  10         * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
  11         * configure: Regenerate.
  12         * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
  13         * po/POTFILES.in: Regenerate.
  14         * tilegx-dis.c: New file.
  15         * tilegx-opc.c: New file.
  16         * tilepro-dis.c: New file.
  17         * tilepro-opc.c: New file.
  18
  19 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
  20
  21         AVX Programming Reference (June, 2011)
  22         * i386-dis.c (XMGatherQ): New.
  23         * i386-dis.c (EXxmm_mb): New.
  24         (EXxmm_mb): Likewise.
  25         (EXxmm_mw): Likewise.
  26         (EXxmm_md): Likewise.
  27         (EXxmm_mq): Likewise.
  28         (EXxmmdw): Likewise.
  29         (EXxmmqd): Likewise.
  30         (VexGatherQ): Likewise.
  31         (MVexVSIBDWpX): Likewise.
  32         (MVexVSIBQWpX): Likewise.
  33         (xmm_mb_mode): Likewise.
  34         (xmm_mw_mode): Likewise.
  35         (xmm_md_mode): Likewise.
  36         (xmm_mq_mode): Likewise.
  37         (xmmdw_mode): Likewise.
  38         (xmmqd_mode): Likewise.
  39         (ymmxmm_mode): Likewise.
  40         (vex_vsib_d_w_dq_mode): Likewise.
  41         (vex_vsib_q_w_dq_mode): Likewise.
  42         (MOD_VEX_0F385A_PREFIX_2): Likewise.
  43         (MOD_VEX_0F388C_PREFIX_2): Likewise.
  44         (MOD_VEX_0F388E_PREFIX_2): Likewise.
  45         (PREFIX_0F3882): Likewise.
  46         (PREFIX_VEX_0F3816): Likewise.
  47         (PREFIX_VEX_0F3836): Likewise.
  48         (PREFIX_VEX_0F3845): Likewise.
  49         (PREFIX_VEX_0F3846): Likewise.
  50         (PREFIX_VEX_0F3847): Likewise.
  51         (PREFIX_VEX_0F3858): Likewise.
  52         (PREFIX_VEX_0F3859): Likewise.
  53         (PREFIX_VEX_0F385A): Likewise.
  54         (PREFIX_VEX_0F3878): Likewise.
  55         (PREFIX_VEX_0F3879): Likewise.
  56         (PREFIX_VEX_0F388C): Likewise.
  57         (PREFIX_VEX_0F388E): Likewise.
  58         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
  59         (PREFIX_VEX_0F38F5): Likewise.
  60         (PREFIX_VEX_0F38F6): Likewise.
  61         (PREFIX_VEX_0F3A00): Likewise.
  62         (PREFIX_VEX_0F3A01): Likewise.
  63         (PREFIX_VEX_0F3A02): Likewise.
  64         (PREFIX_VEX_0F3A38): Likewise.
  65         (PREFIX_VEX_0F3A39): Likewise.
  66         (PREFIX_VEX_0F3A46): Likewise.
  67         (PREFIX_VEX_0F3AF0): Likewise.
  68         (VEX_LEN_0F3816_P_2): Likewise.
  69         (VEX_LEN_0F3819_P_2): Likewise.
  70         (VEX_LEN_0F3836_P_2): Likewise.
  71         (VEX_LEN_0F385A_P_2_M_0): Likewise.
  72         (VEX_LEN_0F38F5_P_0): Likewise.
  73         (VEX_LEN_0F38F5_P_1): Likewise.
  74         (VEX_LEN_0F38F5_P_3): Likewise.
  75         (VEX_LEN_0F38F6_P_3): Likewise.
  76         (VEX_LEN_0F38F7_P_1): Likewise.
  77         (VEX_LEN_0F38F7_P_2): Likewise.
  78         (VEX_LEN_0F38F7_P_3): Likewise.
  79         (VEX_LEN_0F3A00_P_2): Likewise.
  80         (VEX_LEN_0F3A01_P_2): Likewise.
  81         (VEX_LEN_0F3A38_P_2): Likewise.
  82         (VEX_LEN_0F3A39_P_2): Likewise.
  83         (VEX_LEN_0F3A46_P_2): Likewise.
  84         (VEX_LEN_0F3AF0_P_3): Likewise.
  85         (VEX_W_0F3816_P_2): Likewise.
  86         (VEX_W_0F3818_P_2): Likewise.
  87         (VEX_W_0F3819_P_2): Likewise.
  88         (VEX_W_0F3836_P_2): Likewise.
  89         (VEX_W_0F3846_P_2): Likewise.
  90         (VEX_W_0F3858_P_2): Likewise.
  91         (VEX_W_0F3859_P_2): Likewise.
  92         (VEX_W_0F385A_P_2_M_0): Likewise.
  93         (VEX_W_0F3878_P_2): Likewise.
  94         (VEX_W_0F3879_P_2): Likewise.
  95         (VEX_W_0F3A00_P_2): Likewise.
  96         (VEX_W_0F3A01_P_2): Likewise.
  97         (VEX_W_0F3A02_P_2): Likewise.
  98         (VEX_W_0F3A38_P_2): Likewise.
  99         (VEX_W_0F3A39_P_2): Likewise.
 100         (VEX_W_0F3A46_P_2): Likewise.
 101         (MOD_VEX_0F3818_PREFIX_2): Removed.
 102         (MOD_VEX_0F3819_PREFIX_2): Likewise.
 103         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
 104         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
 105         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
 106         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
 107         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
 108         (VEX_LEN_0F3A0E_P_2): Likewise.
 109         (VEX_LEN_0F3A0F_P_2): Likewise.
 110         (VEX_LEN_0F3A42_P_2): Likewise.
 111         (VEX_LEN_0F3A4C_P_2): Likewise.
 112         (VEX_W_0F3818_P_2_M_0): Likewise.
 113         (VEX_W_0F3819_P_2_M_0): Likewise.
 114         (prefix_table): Updated.
 115         (three_byte_table): Likewise.
 116         (vex_table): Likewise.
 117         (vex_len_table): Likewise.
 118         (vex_w_table): Likewise.
 119         (mod_table): Likewise.
 120         (putop): Handle "LW".
 121         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 122         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 123         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 124         (OP_EX): Likewise.
 125         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 126         vex_vsib_q_w_dq_mode.
 127         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 128         (OP_VEX): Likewise.
 129
 130         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 131         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 132         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 133         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 134         (opcode_modifiers): Add VecSIB.
 135
 136         * i386-opc.h (CpuAVX2): New.
 137         (CpuBMI2): Likewise.
 138         (CpuLZCNT): Likewise.
 139         (CpuINVPCID): Likewise.
 140         (VecSIB128): Likewise.
 141         (VecSIB256): Likewise.
 142         (VecSIB): Likewise.
 143         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 144         (i386_opcode_modifier): Add vecsib.
 145
 146         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 147         * i386-init.h: Regenerated.
 148         * i386-tbl.h: Likewise.
 149
 150 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 151
 152         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 153         * i386-init.h: Regenerated.
 154
 155 2011-06-03  Nick Clifton  <nickc@redhat.com>
 156
 157         PR binutils/12752
 158         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 159         computing address offsets.
 160         (print_arm_address): Likewise.
 161         (print_insn_arm): Likewise.
 162         (print_insn_thumb16): Likewise.
 163         (print_insn_thumb32): Likewise.
 164
 165 2011-06-02  Jie Zhang <jie@codesourcery.com>
 166             Nathan Sidwell <nathan@codesourcery.com>
 167             Maciej Rozycki <macro@codesourcery.com>
 168
 169         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 170         as address offset.
 171         (print_arm_address): Likewise. Elide positive #0 appropriately.
 172         (print_insn_arm): Likewise.
 173
 174 2011-06-02  Nick Clifton  <nickc@redhat.com>
 175
 176         PR gas/12752
 177         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 178         passed to print_address_func.
 179
 180 2011-06-02  Nick Clifton  <nickc@redhat.com>
 181
 182         * arm-dis.c: Fix spelling mistakes.
 183         * op/opcodes.pot: Regenerate.
 184
 185 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 186
 187         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 188         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 189         * s390-opc.txt: Fix cxr instruction type.
 190
 191 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 192
 193         * s390-opc.c: Add new instruction types marking register pair
 194         operands.
 195         * s390-opc.txt: Match instructions having register pair operands
 196         to the new instruction types.
 197
 198 2011-05-19  Nick Clifton  <nickc@redhat.com>
 199
 200         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 201         operands.
 202
 203 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 204
 205         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 206         * i386-init.h: Regenerated.
 207
 208 2011-04-27  Nick Clifton  <nickc@redhat.com>
 209
 210         * po/da.po: Updated Danish translation.
 211
 212 2011-04-26  Anton Blanchard  <anton@samba.org>
 213
 214         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 215
 216 2011-04-21  DJ Delorie  <dj@redhat.com>
 217
 218         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 219         * rx-decode.c: Regenerate.
 220
 221 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 222
 223         * i386-init.h: Regenerated.
 224
 225 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 226
 227         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 228         from bdver1 flags.
 229
 230 2011-04-13  Nick Clifton  <nickc@redhat.com>
 231
 232         * v850-dis.c (disassemble): Always print a closing square brace if
 233         an opening square brace was printed.
 234
 235 2011-04-12  Nick Clifton  <nickc@redhat.com>
 236
 237         PR binutils/12534
 238         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 239         patterns.
 240         (print_insn_thumb32): Handle %L.
 241
 242 2011-04-11  Julian Brown  <julian@codesourcery.com>
 243
 244         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 245         (print_insn_thumb32): Add APSR bitmask support.
 246
 247 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 248
 249         * arm-dis.c (print_insn): init vars moved into private_data structure.
 250
 251 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 252
 253         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 254
 255 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 256
 257         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 258         post-increment to support LPM Z+ instruction. Add support for 'E'
 259         constraint for DES instruction.
 260         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 261
 262 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 263
 264         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 265
 266 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 267
 268         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 269         Use branch types instead.
 270         (print_insn): Likewise.
 271
 272 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 273
 274         * mips-opc.c (mips_builtin_opcodes): Correct register use
 275         annotation of "alnv.ps".
 276
 277 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 278
 279         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 280
 281 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 282
 283         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 284
 285 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 286
 287         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 288
 289 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 290
 291         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 292         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 293         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 294         exception, end_of_registers, msize, memory, bfd_mach.
 295         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 296         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 297         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 298         (get_allreg): Change to new defines.  Fallback to abort().
 299
 300 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 301
 302         * bfin-dis.c: Add whitespace/parenthesis where needed.
 303
 304 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 305
 306         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 307         than 7.
 308
 309 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 310
 311         * configure: Regenerate.
 312
 313 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 314
 315         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 316
 317 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 318
 319         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 320         dregs only when P is set, and dregs_lo otherwise.
 321
 322 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 323
 324         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 325
 326 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 327
 328         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 329
 330 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 331
 332         * bfin-dis.c (machine_registers): Delete REG_GP.
 333         (reg_names): Delete "GP".
 334         (decode_allregs): Change REG_GP to REG_LASTREG.
 335
 336 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 337
 338         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 339         M_IH, M_IU): Delete.
 340
 341 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 342
 343         * bfin-dis.c (reg_names): Add const.
 344         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 345         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 346         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 347         decode_counters, decode_allregs): Likewise.
 348
 349 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 350
 351         * i386-dis.c (OP_J): Parenthesize expression to prevent
 352         truncated addresses.
 353         (print_insn): Fix indentation off-by-one.
 354
 355 2011-02-01  Nick Clifton  <nickc@redhat.com>
 356
 357         * po/da.po: Updated Danish translation.
 358
 359 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 360
 361         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 362
 363 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 364
 365         * i386-dis.c (sIbT): New.
 366         (b_T_mode): Likewise.
 367         (dis386): Replace sIb with sIbT on "pushT".
 368         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 369         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 370
 371 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 372
 373         * i386-init.h: Regenerated.
 374         * i386-tbl.h: Regenerated
 375
 376 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 377
 378         * i386-dis.c (REG_XOP_TBM_01): New.
 379         (REG_XOP_TBM_02): New.
 380         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 381         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 382         entries, and add bextr instruction.
 383
 384         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 385         (cpu_flags): Add CpuTBM.
 386
 387         * i386-opc.h (CpuTBM) New.
 388         (i386_cpu_flags): Add bit cputbm.
 389
 390         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 391         blcs, blsfill, blsic, t1mskc, and tzmsk.
 392
 393 2011-01-12  DJ Delorie  <dj@redhat.com>
 394
 395         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 396
 397 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 398
 399         * mips-dis.c (print_insn_args): Adjust the value to print the real
 400         offset for "+c" argument.
 401
 402 2011-01-10  Nick Clifton  <nickc@redhat.com>
 403
 404         * po/da.po: Updated Danish translation.
 405
 406 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 407
 408         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 409
 410 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 411
 412         * i386-dis.c (REG_VEX_38F3): New.
 413         (PREFIX_0FBC): Likewise.
 414         (PREFIX_VEX_38F2): Likewise.
 415         (PREFIX_VEX_38F3_REG_1): Likewise.
 416         (PREFIX_VEX_38F3_REG_2): Likewise.
 417         (PREFIX_VEX_38F3_REG_3): Likewise.
 418         (PREFIX_VEX_38F7): Likewise.
 419         (VEX_LEN_38F2_P_0): Likewise.
 420         (VEX_LEN_38F3_R_1_P_0): Likewise.
 421         (VEX_LEN_38F3_R_2_P_0): Likewise.
 422         (VEX_LEN_38F3_R_3_P_0): Likewise.
 423         (VEX_LEN_38F7_P_0): Likewise.
 424         (dis386_twobyte): Use PREFIX_0FBC.
 425         (reg_table): Add REG_VEX_38F3.
 426         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 427         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 428         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 429         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 430         PREFIX_VEX_38F7.
 431         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 432         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 433         VEX_LEN_38F7_P_0.
 434
 435         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 436         (cpu_flags): Add CpuBMI.
 437
 438         * i386-opc.h (CpuBMI): New.
 439         (i386_cpu_flags): Add cpubmi.
 440
 441         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 442         * i386-init.h: Regenerated.
 443         * i386-tbl.h: Likewise.
 444
 445 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 446
 447         * i386-dis.c (VexGdq): New.
 448         (OP_VEX): Handle dq_mode.
 449
 450 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         * i386-gen.c (process_copyright): Update copyright to 2011.
 453
 454 For older changes see ChangeLog-2010
 455 \f
 456 Local Variables:
 457 mode: change-log
 458 left-margin: 8
 459 fill-column: 74
 460 version-control: never
 461 End: