opcodes/ChangeLog

   1 2020-03-22  Alan Modra  <amodra@gmail.com>
   2
   3         * arc-dis.c (find_format): Use ISO C string concatenation rather
   4         than line continuation within a string.  Don't access needs_limm
   5         before testing opcode != NULL.
   6
   7 2020-03-22  Alan Modra  <amodra@gmail.com>
   8
   9         * ns32k-dis.c (print_insn_arg): Update comment.
  10         (print_insn_ns32k): Reduce size of index_offset array, and
  11         initialize, passing -1 to print_insn_arg for args that are not
  12         an index.  Don't exit arg loop early.  Abort on bad arg number.
  13
  14 2020-03-22  Alan Modra  <amodra@gmail.com>
  15
  16         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
  17         * s12z-opc.c: Formatting.
  18         (operands_f): Return an int.
  19         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
  20         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
  21         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
  22         (exg_sex_discrim): Likewise.
  23         (create_immediate_operand, create_bitfield_operand),
  24         (create_register_operand_with_size, create_register_all_operand),
  25         (create_register_all16_operand, create_simple_memory_operand),
  26         (create_memory_operand, create_memory_auto_operand): Don't
  27         segfault on malloc failure.
  28         (z_ext24_decode): Return an int status, negative on fail, zero
  29         on success.
  30         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
  31         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
  32         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
  33         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
  34         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
  35         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
  36         (loop_primitive_decode, shift_decode, psh_pul_decode),
  37         (bit_field_decode): Similarly.
  38         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
  39         to return value, update callers.
  40         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
  41         Don't segfault on NULL operand.
  42         (decode_operation): Return OP_INVALID on first fail.
  43         (decode_s12z): Check all reads, returning -1 on fail.
  44
  45 2020-03-20  Alan Modra  <amodra@gmail.com>
  46
  47         * metag-dis.c (print_insn_metag): Don't ignore status from
  48         read_memory_func.
  49
  50 2020-03-20  Alan Modra  <amodra@gmail.com>
  51
  52         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
  53         Initialize parts of buffer not written when handling a possible
  54         2-byte insn at end of section.  Don't attempt decoding of such
  55         an insn by the 4-byte machinery.
  56
  57 2020-03-20  Alan Modra  <amodra@gmail.com>
  58
  59         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
  60         partially filled buffer.  Prevent lookup of 4-byte insns when
  61         only VLE 2-byte insns are possible due to section size.  Print
  62         ".word" rather than ".long" for 2-byte leftovers.
  63
  64 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
  65
  66         PR 25641
  67         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
  68
  69 2020-03-13  Jan Beulich  <jbeulich@suse.com>
  70
  71         * i386-dis.c (X86_64_0D): Rename to ...
  72         (X86_64_0E): ... this.
  73
  74 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  75
  76         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
  77         * Makefile.in: Regenerated.
  78
  79 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
  82         3-operand pseudos.
  83         * i386-tbl.h: Re-generate.
  84
  85 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
  88         vprot*, vpsha*, and vpshl*.
  89         * i386-tbl.h: Re-generate.
  90
  91 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
  94         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
  95         * i386-tbl.h: Re-generate.
  96
  97 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 100         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 101         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 102         * i386-tbl.h: Re-generate.
 103
 104 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 105
 106         * i386-gen.c (struct template_arg, struct template_instance,
 107         struct template_param, struct template, templates,
 108         parse_template, expand_templates): New.
 109         (process_i386_opcodes): Various local variables moved to
 110         expand_templates. Call parse_template and expand_templates.
 111         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 112         * i386-tbl.h: Re-generate.
 113
 114 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 115
 116         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 117         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 118         register and memory source templates. Replace VexW= by VexW*
 119         where applicable.
 120         * i386-tbl.h: Re-generate.
 121
 122 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 123
 124         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 125         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 126         * i386-tbl.h: Re-generate.
 127
 128 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 129
 130         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 131         * i386-tbl.h: Re-generate.
 132
 133 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 134
 135         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 136         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 137         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 138         VexW0 on SSE2AVX variants.
 139         (vmovq): Drop NoRex64 from XMM/XMM variants.
 140         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 141         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 142         applicable use VexW0.
 143         * i386-tbl.h: Re-generate.
 144
 145 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 146
 147         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 148         * i386-opc.h (Rex64): Delete.
 149         (struct i386_opcode_modifier): Remove rex64 field.
 150         * i386-opc.tbl (crc32): Drop Rex64.
 151         Replace Rex64 with Size64 everywhere else.
 152         * i386-tbl.h: Re-generate.
 153
 154 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-dis.c (OP_E_memory): Exclude recording of used address
 157         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 158         addressed memory operands for MPX insns.
 159
 160 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 161
 162         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 163         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 164         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 165         (ptwrite): Split into non-64-bit and 64-bit forms.
 166         * i386-tbl.h: Re-generate.
 167
 168 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 171         template.
 172         * i386-tbl.h: Re-generate.
 173
 174 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 177         (prefix_table): Move vmmcall here. Add vmgexit.
 178         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 179         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 180         (cpu_flags): Add CpuSEV_ES entry.
 181         * i386-opc.h (CpuSEV_ES): New.
 182         (union i386_cpu_flags): Add cpusev_es field.
 183         * i386-opc.tbl (vmgexit): New.
 184         * i386-init.h, i386-tbl.h: Re-generate.
 185
 186 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 187
 188         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 189         with MnemonicSize.
 190         * i386-opc.h (IGNORESIZE): New.
 191         (DEFAULTSIZE): Likewise.
 192         (IgnoreSize): Removed.
 193         (DefaultSize): Likewise.
 194         (MnemonicSize): New.
 195         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 196         mnemonicsize.
 197         * i386-opc.tbl (IgnoreSize): New.
 198         (DefaultSize): Likewise.
 199         * i386-tbl.h: Regenerated.
 200
 201 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 202
 203         PR 25627
 204         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 205         instructions.
 206
 207 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 208
 209         PR gas/25622
 210         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 211         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 212         * i386-tbl.h: Regenerated.
 213
 214 2020-02-26  Alan Modra  <amodra@gmail.com>
 215
 216         * aarch64-asm.c: Indent labels correctly.
 217         * aarch64-dis.c: Likewise.
 218         * aarch64-gen.c: Likewise.
 219         * aarch64-opc.c: Likewise.
 220         * alpha-dis.c: Likewise.
 221         * i386-dis.c: Likewise.
 222         * nds32-asm.c: Likewise.
 223         * nfp-dis.c: Likewise.
 224         * visium-dis.c: Likewise.
 225
 226 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 227
 228         * arc-regs.h (int_vector_base): Make it available for all ARC
 229         CPUs.
 230
 231 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 232
 233         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 234         changed.
 235
 236 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 237
 238         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 239         c.mv/c.li if rs1 is zero.
 240
 241 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 242
 243         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 244         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 245         CPU_POPCNT_FLAGS.
 246         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 247         * i386-opc.h (CpuABM): Removed.
 248         (CpuPOPCNT): New.
 249         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 250         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 251         popcnt.  Remove CpuABM from lzcnt.
 252         * i386-init.h: Regenerated.
 253         * i386-tbl.h: Likewise.
 254
 255 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 256
 257         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 258         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 259         VexW1 instead of open-coding them.
 260         * i386-tbl.h: Re-generate.
 261
 262 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 263
 264         * i386-opc.tbl (AddrPrefixOpReg): Define.
 265         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 266         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 267         templates. Drop NoRex64.
 268         * i386-tbl.h: Re-generate.
 269
 270 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 271
 272         PR gas/6518
 273         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 274         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 275         into Intel syntax instance (with Unpsecified) and AT&T one
 276         (without).
 277         (vcvtneps2bf16): Likewise, along with folding the two so far
 278         separate ones.
 279         * i386-tbl.h: Re-generate.
 280
 281 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 282
 283         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 284         CPU_ANY_SSE4A_FLAGS.
 285
 286 2020-02-17  Alan Modra  <amodra@gmail.com>
 287
 288         * i386-gen.c (cpu_flag_init): Correct last change.
 289
 290 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 291
 292         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 293         CPU_ANY_SSE4_FLAGS.
 294
 295 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 296
 297         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 298         (movzx): Likewise.
 299
 300 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 301
 302         PR gas/25438
 303         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 304         destination for Cpu64-only variant.
 305         (movzx): Fold patterns.
 306         * i386-tbl.h: Re-generate.
 307
 308 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 309
 310         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 311         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 312         CPU_ANY_SSE4_FLAGS entry.
 313         * i386-init.h: Re-generate.
 314
 315 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 316
 317         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 318         with Unspecified, making the present one AT&T syntax only.
 319         * i386-tbl.h: Re-generate.
 320
 321 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 324         * i386-tbl.h: Re-generate.
 325
 326 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 327
 328         PR gas/24546
 329         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 330         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 331         Amd64 and Intel64 templates.
 332         (call, jmp): Likewise for far indirect variants. Dro
 333         Unspecified.
 334         * i386-tbl.h: Re-generate.
 335
 336 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 339         * i386-opc.h (ShortForm): Delete.
 340         (struct i386_opcode_modifier): Remove shortform field.
 341         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 342         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 343         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 344         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 345         Drop ShortForm.
 346         * i386-tbl.h: Re-generate.
 347
 348 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 351         fucompi): Drop ShortForm from operand-less templates.
 352         * i386-tbl.h: Re-generate.
 353
 354 2020-02-11  Alan Modra  <amodra@gmail.com>
 355
 356         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 357         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 358         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 359         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 360         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 361
 362 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 363
 364         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 365         (cde_opcodes): Add VCX* instructions.
 366
 367 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 368             Matthew Malcomson  <matthew.malcomson@arm.com>
 369
 370         * arm-dis.c (struct cdeopcode32): New.
 371         (CDE_OPCODE): New macro.
 372         (cde_opcodes): New disassembly table.
 373         (regnames): New option to table.
 374         (cde_coprocs): New global variable.
 375         (print_insn_cde): New
 376         (print_insn_thumb32): Use print_insn_cde.
 377         (parse_arm_disassembler_options): Parse coprocN args.
 378
 379 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 380
 381         PR gas/25516
 382         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 383         with ISA64.
 384         * i386-opc.h (AMD64): Removed.
 385         (Intel64): Likewose.
 386         (AMD64): New.
 387         (INTEL64): Likewise.
 388         (INTEL64ONLY): Likewise.
 389         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 390         * i386-opc.tbl (Amd64): New.
 391         (Intel64): Likewise.
 392         (Intel64Only): Likewise.
 393         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 394         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 395         * i386-tbl.h: Regenerated.
 396
 397 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 398
 399         PR 25469
 400         * z80-dis.c: Add support for GBZ80 opcodes.
 401
 402 2020-02-04  Alan Modra  <amodra@gmail.com>
 403
 404         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 405
 406 2020-02-03  Alan Modra  <amodra@gmail.com>
 407
 408         * m32c-ibld.c: Regenerate.
 409
 410 2020-02-01  Alan Modra  <amodra@gmail.com>
 411
 412         * frv-ibld.c: Regenerate.
 413
 414 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 415
 416         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 417         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 418         (OP_E_memory): Replace xmm_mdq_mode case label by
 419         vex_scalar_w_dq_mode one.
 420         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 421
 422 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 423
 424         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 425         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 426         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 427         (intel_operand_size): Drop vex_w_dq_mode case label.
 428
 429 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 430
 431         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 432         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 433
 434 2020-01-30  Alan Modra  <amodra@gmail.com>
 435
 436         * m32c-ibld.c: Regenerate.
 437
 438 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 439
 440         * bpf-opc.c: Regenerate.
 441
 442 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 443
 444         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 445         (dis386): Use them to replace C2/C3 table entries.
 446         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 447         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 448         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 449         * i386-tbl.h: Re-generate.
 450
 451 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 452
 453         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 454         forms.
 455         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 456         DefaultSize.
 457         * i386-tbl.h: Re-generate.
 458
 459 2020-01-30  Alan Modra  <amodra@gmail.com>
 460
 461         * tic4x-dis.c (tic4x_dp): Make unsigned.
 462
 463 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 464             Jan Beulich  <jbeulich@suse.com>
 465
 466         PR binutils/25445
 467         * i386-dis.c (MOVSXD_Fixup): New function.
 468         (movsxd_mode): New enum.
 469         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 470         (intel_operand_size): Handle movsxd_mode.
 471         (OP_E_register): Likewise.
 472         (OP_G): Likewise.
 473         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 474         register on movsxd.  Add movsxd with 16-bit destination register
 475         for AMD64 and Intel64 ISAs.
 476         * i386-tbl.h: Regenerated.
 477
 478 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 479
 480         PR 25403
 481         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 482         * aarch64-asm-2.c: Regenerate
 483         * aarch64-dis-2.c: Likewise.
 484         * aarch64-opc-2.c: Likewise.
 485
 486 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 487
 488         * i386-opc.tbl (sysret): Drop DefaultSize.
 489         * i386-tbl.h: Re-generate.
 490
 491 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 494         Dword.
 495         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 496         * i386-tbl.h: Re-generate.
 497
 498 2020-01-20  Nick Clifton  <nickc@redhat.com>
 499
 500         * po/de.po: Updated German translation.
 501         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 502         * po/uk.po: Updated Ukranian translation.
 503
 504 2020-01-20  Alan Modra  <amodra@gmail.com>
 505
 506         * hppa-dis.c (fput_const): Remove useless cast.
 507
 508 2020-01-20  Alan Modra  <amodra@gmail.com>
 509
 510         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 511
 512 2020-01-18  Nick Clifton  <nickc@redhat.com>
 513
 514         * configure: Regenerate.
 515         * po/opcodes.pot: Regenerate.
 516
 517 2020-01-18  Nick Clifton  <nickc@redhat.com>
 518
 519         Binutils 2.34 branch created.
 520
 521 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 522
 523         * opintl.h: Fix spelling error (seperate).
 524
 525 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 526
 527         * i386-opc.tbl: Add {vex} pseudo prefix.
 528         * i386-tbl.h: Regenerated.
 529
 530 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 531
 532         PR 25376
 533         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 534         (neon_opcodes): Likewise.
 535         (select_arm_features): Make sure we enable MVE bits when selecting
 536         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 537         any architecture.
 538
 539 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 540
 541         * i386-opc.tbl: Drop stale comment from XOP section.
 542
 543 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 544
 545         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 546         (extractps): Add VexWIG to SSE2AVX forms.
 547         * i386-tbl.h: Re-generate.
 548
 549 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 552         Size64 from and use VexW1 on SSE2AVX forms.
 553         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 554         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 555         * i386-tbl.h: Re-generate.
 556
 557 2020-01-15  Alan Modra  <amodra@gmail.com>
 558
 559         * tic4x-dis.c (tic4x_version): Make unsigned long.
 560         (optab, optab_special, registernames): New file scope vars.
 561         (tic4x_print_register): Set up registernames rather than
 562         malloc'd registertable.
 563         (tic4x_disassemble): Delete optable and optable_special.  Use
 564         optab and optab_special instead.  Throw away old optab,
 565         optab_special and registernames when info->mach changes.
 566
 567 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 568
 569         PR 25377
 570         * z80-dis.c (suffix): Use .db instruction to generate double
 571         prefix.
 572
 573 2020-01-14  Alan Modra  <amodra@gmail.com>
 574
 575         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 576         values to unsigned before shifting.
 577
 578 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 579
 580         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 581         flow instructions.
 582         (print_insn_thumb16, print_insn_thumb32): Likewise.
 583         (print_insn): Initialize the insn info.
 584         * i386-dis.c (print_insn): Initialize the insn info fields, and
 585         detect jumps.
 586
 587 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 588
 589         * arc-opc.c (C_NE): Make it required.
 590
 591 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 592
 593         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 594         reserved register name.
 595
 596 2020-01-13  Alan Modra  <amodra@gmail.com>
 597
 598         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 599         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 600
 601 2020-01-13  Alan Modra  <amodra@gmail.com>
 602
 603         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 604         result of wasm_read_leb128 in a uint64_t and check that bits
 605         are not lost when copying to other locals.  Use uint32_t for
 606         most locals.  Use PRId64 when printing int64_t.
 607
 608 2020-01-13  Alan Modra  <amodra@gmail.com>
 609
 610         * score-dis.c: Formatting.
 611         * score7-dis.c: Formatting.
 612
 613 2020-01-13  Alan Modra  <amodra@gmail.com>
 614
 615         * score-dis.c (print_insn_score48): Use unsigned variables for
 616         unsigned values.  Don't left shift negative values.
 617         (print_insn_score32): Likewise.
 618         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 619
 620 2020-01-13  Alan Modra  <amodra@gmail.com>
 621
 622         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 623
 624 2020-01-13  Alan Modra  <amodra@gmail.com>
 625
 626         * fr30-ibld.c: Regenerate.
 627
 628 2020-01-13  Alan Modra  <amodra@gmail.com>
 629
 630         * xgate-dis.c (print_insn): Don't left shift signed value.
 631         (ripBits): Formatting, use 1u.
 632
 633 2020-01-10  Alan Modra  <amodra@gmail.com>
 634
 635         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 636         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 637
 638 2020-01-10  Alan Modra  <amodra@gmail.com>
 639
 640         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 641         and XRREG value earlier to avoid a shift with negative exponent.
 642         * m10200-dis.c (disassemble): Similarly.
 643
 644 2020-01-09  Nick Clifton  <nickc@redhat.com>
 645
 646         PR 25224
 647         * z80-dis.c (ld_ii_ii): Use correct cast.
 648
 649 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 650
 651         PR 25224
 652         * z80-dis.c (ld_ii_ii): Use character constant when checking
 653         opcode byte value.
 654
 655 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 656
 657         * i386-dis.c (SEP_Fixup): New.
 658         (SEP): Define.
 659         (dis386_twobyte): Use it for sysenter/sysexit.
 660         (enum x86_64_isa): Change amd64 enumerator to value 1.
 661         (OP_J): Compare isa64 against intel64 instead of amd64.
 662         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 663         forms.
 664         * i386-tbl.h: Re-generate.
 665
 666 2020-01-08  Alan Modra  <amodra@gmail.com>
 667
 668         * z8k-dis.c: Include libiberty.h
 669         (instr_data_s): Make max_fetched unsigned.
 670         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 671         Don't exceed byte_info bounds.
 672         (output_instr): Make num_bytes unsigned.
 673         (unpack_instr): Likewise for nibl_count and loop.
 674         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 675         idx unsigned.
 676         * z8k-opc.h: Regenerate.
 677
 678 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 679
 680         * arc-tbl.h (llock): Use 'LLOCK' as class.
 681         (llockd): Likewise.
 682         (scond): Use 'SCOND' as class.
 683         (scondd): Likewise.
 684         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 685         (scondd): Likewise.
 686
 687 2020-01-06  Alan Modra  <amodra@gmail.com>
 688
 689         * m32c-ibld.c: Regenerate.
 690
 691 2020-01-06  Alan Modra  <amodra@gmail.com>
 692
 693         PR 25344
 694         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 695         Peek at next byte to prevent recursion on repeated prefix bytes.
 696         Ensure uninitialised "mybuf" is not accessed.
 697         (print_insn_z80): Don't zero n_fetch and n_used here,..
 698         (print_insn_z80_buf): ..do it here instead.
 699
 700 2020-01-04  Alan Modra  <amodra@gmail.com>
 701
 702         * m32r-ibld.c: Regenerate.
 703
 704 2020-01-04  Alan Modra  <amodra@gmail.com>
 705
 706         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 707
 708 2020-01-04  Alan Modra  <amodra@gmail.com>
 709
 710         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 711
 712 2020-01-04  Alan Modra  <amodra@gmail.com>
 713
 714         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 715
 716 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 717
 718         * aarch64-tbl.h (aarch64_opcode_table): Use
 719         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 720
 721 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 722
 723         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 724         forms of SUDOT and USDOT.
 725
 726 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 727
 728         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 729         uzip{1,2}.
 730         * opcodes/aarch64-dis-2.c: Re-generate.
 731
 732 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 733
 734         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 735         FMMLA encoding.
 736         * opcodes/aarch64-dis-2.c: Re-generate.
 737
 738 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 739
 740         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 741
 742 2020-01-01  Alan Modra  <amodra@gmail.com>
 743
 744         Update year range in copyright notice of all files.
 745
 746 For older changes see ChangeLog-2019
 747 \f
 748 Copyright (C) 2020 Free Software Foundation, Inc.
 749
 750 Copying and distribution of this file, with or without modification,
 751 are permitted in any medium without royalty provided the copyright
 752 notice and this notice are preserved.
 753
 754 Local Variables:
 755 mode: change-log
 756 left-margin: 8
 757 fill-column: 74
 758 version-control: never
 759 End: